commit	9e314b9ee3de1b0feb510430b969385ebff7ec21	[log] [tgz]
author	embelon <78412338+embelon@users.noreply.github.com>	Thu Nov 25 21:23:21 2021 +0100
committer	embelon <78412338+embelon@users.noreply.github.com>	Thu Nov 25 21:23:21 2021 +0100
tree	441fdcb8ceefca9b562cb6bc8aa96a7f269ced70
parent	af9dbfc2c5dfc5b94da72f89eee773c01f641f0d [diff]

Fixed unaligned access over Wishbone bus that results in picorv32 hang. Improved readability.

verilog/dv/wb_openram/wb_openram.c[diff]

1 file changed

tree: 441fdcb8ceefca9b562cb6bc8aa96a7f269ced70

README.md

Caravel User Project

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory block	Space	Address	Size
HyperRAM ext. chip	RAM	0x3000_0000 - 0x307f_ffff	8MB
HyperRAM ext. chip	Registers	0x3080_0000 - 0x3080_ffff	max 64k registers, 16bit each
HyperRAM driver	CSRs	0x3081_0000 - 0x3081_ffff	max 64kB, 16k CSRs
OpenRAM	RAM	0x30c0_0000 - 0x30c0_ffff	max 64kB