Added wb_openram_wrapper as a submodule to use verilog blackbox, gds and lef.
diff --git a/.gitmodules b/.gitmodules
index 638a740..1be944d 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,3 +4,6 @@
[submodule "openram_testchip"]
path = openram_testchip
url = https://github.com/VLSIDA/openram_testchip
+[submodule "wb_openram_wrapper"]
+ path = wb_openram_wrapper
+ url = https://github.com/embelon/wb_openram_wrapper
diff --git a/wb_openram_wrapper b/wb_openram_wrapper
new file mode 160000
index 0000000..d2662bc
--- /dev/null
+++ b/wb_openram_wrapper
@@ -0,0 +1 @@
+Subproject commit d2662bc42bdcf328d31bf5de1bc471532d2378b2
