Added openram_testchip as a submodule to use verilog blackbox, gds and lef.
diff --git a/.gitmodules b/.gitmodules
index c73b442..638a740 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
[submodule "caravel-lite"]
path = caravel
url = https://github.com/efabless/caravel-lite
+[submodule "openram_testchip"]
+ path = openram_testchip
+ url = https://github.com/VLSIDA/openram_testchip
diff --git a/openram_testchip b/openram_testchip
new file mode 160000
index 0000000..f2cb18b
--- /dev/null
+++ b/openram_testchip
@@ -0,0 +1 @@
+Subproject commit f2cb18b735872621722a1a63c7b5a95585e5d270
