Added gtkw file.
diff --git a/verilog/dv/wb_openram/wb_openram.gtkw b/verilog/dv/wb_openram/wb_openram.gtkw
new file mode 100644
index 0000000..b120cf7
--- /dev/null
+++ b/verilog/dv/wb_openram/wb_openram.gtkw
@@ -0,0 +1,90 @@
+[*]
+[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
+[*] Fri Nov 12 11:24:56 2021
+[*]
+[dumpfile] "/home/zwierzak/Projects/ZeroToAsic/OpenRAM_mpw3a_1kB/caravel_wb_openram/verilog/dv/wb_openram/wb_openram.vcd"
+[dumpfile_mtime] "Fri Nov 12 10:17:54 2021"
+[dumpfile_size] 1260766068
+[savefile] "/home/zwierzak/Projects/ZeroToAsic/OpenRAM_mpw3a_1kB/caravel_wb_openram/verilog/dv/wb_openram/wb_openram.gtkw"
+[timestart] 1201270000
+[size] 1000 600
+[pos] -1 -1
+*-24.000000 1256043000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] wb_openram_tb.
+[treeopen] wb_openram_tb.uut.
+[treeopen] wb_openram_tb.uut.mprj.
+[sst_width] 43
+[signals_width] 195
+[sst_expanded] 0
+[sst_vpaned_height] 236
+@28
+wb_openram_tb.uut.mprj.wb_clk_i
+wb_openram_tb.uut.mprj.wb_rst_i
+wb_openram_tb.uut.mprj.wbs_cyc_i
+wb_openram_tb.uut.mprj.wbs_stb_i
+wb_openram_tb.uut.mprj.wbs_we_i
+@22
+wb_openram_tb.uut.mprj.wbs_sel_i[3:0]
+wb_openram_tb.uut.mprj.wbs_adr_i[31:0]
+wb_openram_tb.uut.mprj.wbs_dat_i[31:0]
+wb_openram_tb.uut.mprj.wbs_dat_o[31:0]
+@28
+wb_openram_tb.uut.mprj.wbs_ack_o
+wb_openram_tb.uut.mprj.openram_clk0
+wb_openram_tb.uut.mprj.openram_csb0
+wb_openram_tb.uut.mprj.openram_web0
+@22
+wb_openram_tb.uut.mprj.openram_wmask0[3:0]
+wb_openram_tb.uut.mprj.openram_addr0[7:0]
+wb_openram_tb.uut.mprj.openram_din0[31:0]
+wb_openram_tb.uut.mprj.openram_dout0[31:0]
+@28
+wb_openram_tb.uut.mprj.wbs_hr_cyc
+wb_openram_tb.uut.mprj.wbs_hr_stb
+wb_openram_tb.uut.mprj.wbs_hr_we
+@22
+wb_openram_tb.uut.mprj.wbs_hr_sel[3:0]
+wb_openram_tb.uut.mprj.wbs_hr_dat_i[31:0]
+wb_openram_tb.uut.mprj.wbs_hr_dat_o[31:0]
+@28
+wb_openram_tb.uut.mprj.wbs_hr_ack
+@800022
+wb_openram_tb.uut.mprj.io_oeb[37:0]
+@28
+(17)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(18)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(19)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(20)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(21)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(22)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(23)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(24)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(25)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(26)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(27)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(28)wb_openram_tb.uut.mprj.io_oeb[37:0]
+(29)wb_openram_tb.uut.mprj.io_oeb[37:0]
+@1001200
+-group_end
+@800022
+wb_openram_tb.uut.mprj.io_out[37:0]
+@28
+(17)wb_openram_tb.uut.mprj.io_out[37:0]
+(18)wb_openram_tb.uut.mprj.io_out[37:0]
+(19)wb_openram_tb.uut.mprj.io_out[37:0]
+(20)wb_openram_tb.uut.mprj.io_out[37:0]
+(21)wb_openram_tb.uut.mprj.io_out[37:0]
+(22)wb_openram_tb.uut.mprj.io_out[37:0]
+(23)wb_openram_tb.uut.mprj.io_out[37:0]
+(24)wb_openram_tb.uut.mprj.io_out[37:0]
+(25)wb_openram_tb.uut.mprj.io_out[37:0]
+(26)wb_openram_tb.uut.mprj.io_out[37:0]
+(27)wb_openram_tb.uut.mprj.io_out[37:0]
+(28)wb_openram_tb.uut.mprj.io_out[37:0]
+(29)wb_openram_tb.uut.mprj.io_out[37:0]
+@1001200
+-group_end
+@28
+wb_openram_tb.uut.mprj.wb_hyperram.hb_read_timeout
+[pattern_trace] 1
+[pattern_trace] 0
