commit	3078083555378371ac4df8ae2f7a8f6e420688e8	[log] [tgz]
author	embelon <78412338+embelon@users.noreply.github.com>	Fri Nov 12 12:27:03 2021 +0100
committer	embelon <78412338+embelon@users.noreply.github.com>	Fri Nov 12 12:27:03 2021 +0100
tree	d1949e1489520c3823bda46b5093370510a68e52
parent	cfbec7b4eec97dcbc1044cc399e04bad3e68ac87 [diff]

Added gtkw file.

verilog/dv/wb_openram/wb_openram.gtkw[Added - diff]

1 file changed

tree: d1949e1489520c3823bda46b5093370510a68e52

README.md

Caravel User Project

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory block	Space	Address	Size
HyperRAM ext. chip	RAM	0x3000_0000 - 0x307f_ffff	8MB
HyperRAM ext. chip	Registers	0x3080_0000 - 0x3080_ffff	max 64k registers, 16bit each
HyperRAM driver	CSRs	0x3081_0000 - 0x3081_ffff	max 64kB, 16k CSRs
OpenRAM	RAM	0x30c0_0000 - 0x30c0_ffff	max 64kB