commit	18d883aed3f53f743a797477fcb130f1e621ca06	[log] [tgz]
author	embelon <78412338+embelon@users.noreply.github.com>	Fri Nov 12 12:27:40 2021 +0100
committer	embelon <78412338+embelon@users.noreply.github.com>	Fri Nov 12 12:27:40 2021 +0100
tree	96552a75863d6aba33ef77f56e72c5826d77e871
parent	3078083555378371ac4df8ae2f7a8f6e420688e8 [diff]

Updated clock generation for testbench.

verilog/dv/wb_openram/wb_openram_tb.v[diff]

1 file changed

tree: 96552a75863d6aba33ef77f56e72c5826d77e871

README.md

Caravel User Project

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory block	Space	Address	Size
HyperRAM ext. chip	RAM	0x3000_0000 - 0x307f_ffff	8MB
HyperRAM ext. chip	Registers	0x3080_0000 - 0x3080_ffff	max 64k registers, 16bit each
HyperRAM driver	CSRs	0x3081_0000 - 0x3081_ffff	max 64kB, 16k CSRs
OpenRAM	RAM	0x30c0_0000 - 0x30c0_ffff	max 64kB