)]}'
{
  "commit": "18d883aed3f53f743a797477fcb130f1e621ca06",
  "tree": "96552a75863d6aba33ef77f56e72c5826d77e871",
  "parents": [
    "3078083555378371ac4df8ae2f7a8f6e420688e8"
  ],
  "author": {
    "name": "embelon",
    "email": "78412338+embelon@users.noreply.github.com",
    "time": "Fri Nov 12 12:27:40 2021 +0100"
  },
  "committer": {
    "name": "embelon",
    "email": "78412338+embelon@users.noreply.github.com",
    "time": "Fri Nov 12 12:27:40 2021 +0100"
  },
  "message": "Updated clock generation for testbench.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2888820ac9f80bf1657cf17caa95a7141d2ddc54",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_openram/wb_openram_tb.v",
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}