commit: e015e317ce8066912dcb620bccf1b4307f999727
[log]
author: Amro Tork <amro_tork@mabrains.com>
Tue Oct 12 11:17:44 2021 +0200
committer: Amro Tork <amro_tork@mabrains.com>
Tue Oct 12 11:17:44 2021 +0200
tree: 91729344a6f7e60436b5ffc75ddde0200d0561f4

- First verison of Analog Caravel

LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/user_analog_project_wrapper.gds[Added - diff]
info.yaml[Added - diff]
mag/example_por.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag[Added - diff]
mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag[Added - diff]
mag/user_analog_proj_example.mag[Added - diff]
mag/user_analog_project_wrapper.mag[Added - diff]
mag/user_analog_project_wrapper_empty.mag[Added - diff]
netgen/comp.out[Added - diff]
netgen/example_por.spice[Added - diff]
netgen/run_lvs_por.sh[Added - diff]
netgen/run_lvs_wrapper_verilog.sh[Added - diff]
netgen/run_lvs_wrapper_xschem.sh[Added - diff]
netgen/user_analog_project_wrapper.spice[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/mprj_por/Makefile[Added - diff]
verilog/dv/mprj_por/mprj_por.c[Added - diff]
verilog/dv/mprj_por/mprj_por_tb.v[Added - diff]
verilog/rtl/example_por.v[Added - diff]
verilog/rtl/uprj_analog_netlists.v[Added - diff]
verilog/rtl/user_analog_proj_example.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[Added - diff]
xschem/.spiceinit[Added - diff]
xschem/analog_wrapper_tb.sch[Added - diff]
xschem/analog_wrapper_tb.spice[Added - diff]
xschem/current_test.spice[Added - diff]
xschem/example_por.sch[Added - diff]
xschem/example_por.sym[Added - diff]
xschem/example_por_tb.sch[Added - diff]
xschem/example_por_tb.spice[Added - diff]
xschem/example_por_tb.spice.orig[Added - diff]
xschem/test.data[Added - diff]
xschem/threshold_test_tb.spice[Added - diff]
xschem/user_analog_project_wrapper.sch[Added - diff]
xschem/user_analog_project_wrapper.spice[Added - diff]
xschem/user_analog_project_wrapper.sym[Added - diff]
xschem/xschemrc[Added - diff]

57 files changed

tree: 91729344a6f7e60436b5ffc75ddde0200d0561f4

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.