Updated to MPW3
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index e3d2bd1..fdd1ad7 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -14,7 +14,7 @@
# SPDX-License-Identifier: Apache-2.0
set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+#set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
set script_dir [file dirname [file normalize [info script]]]
@@ -47,17 +47,11 @@
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
-<<<<<<< HEAD
-#set ::env(DIE_AREA) "0 0 900 600"
-set ::env(DIE_AREA) "0 0 300 300"
-
-set ::env(DESIGN_IS_CORE) 0
+set ::env(DIE_AREA) "0 0 900 600"
+#set ::env(DIE_AREA) "0 0 300 300"
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-=======
-set ::env(DIE_AREA) "0 0 900 600"
->>>>>>> c5da9e9885e361d05dee2aa6303a69fc26423c8e
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -65,7 +59,6 @@
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.5
-<<<<<<< HEAD
# If you're going to use multiple power domains, then keep this disabled.
set ::env(RUN_CVC) 0
@@ -78,12 +71,14 @@
set ::env(CLK_BUFFER) "sky130_fd_sc_ls__clkbuf_4"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_ls"
+set ::env(STD_CELL_POWER_PINS) "VPWR VPB"
+set ::env(STD_CELL_GROUND_PINS) "VGND VNB"
+
# set ::env(GLB_RT_OBS) "met2 0 3519 2920 3540" # Might be needed for precheck
# The following is a workaround on the extraction issue with the power rails in the Libresilicon cells. This should be removed when the reason has been identified and solved:
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
-=======
# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper)
# where the PDN is planned on metal 5. So, to avoid having shorts between routes
@@ -91,10 +86,7 @@
set ::env(GLB_RT_MAXLAYER) 5
# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]
+#set ::env(VDD_NETS) [list {vccd1}]
+#set ::env(GND_NETS) [list {vssd1}]
set ::env(DIODE_INSERTION_STRATEGY) 4
-# If you're going to use multiple power domains, then disable cvc run.
-set ::env(RUN_CVC) 1
->>>>>>> c5da9e9885e361d05dee2aa6303a69fc26423c8e
