commit: 05657df1a714cfe0c46c7efd0e0422ff48975c24
[log] [tgz]
author: Mehdi Saligane <mehdi@vlsipool-j06.eecs.umich.edu>
Thu Jul 29 13:35:37 2021 -0400
committer: Mehdi Saligane <mehdi@vlsipool-j06.eecs.umich.edu>
Thu Jul 29 13:35:37 2021 -0400
tree: 429f656573abb3f9e80e44f5965a2360b41aacdd
parent: b81e1be67607390110be0c5efa62106246fb2b36 [diff]

1st commit MPW-II including LDOs, Opentitan SoC and voltage references

gds/ldo_all.gds[Added - diff]
gds/opentitan_soc_top.gds[Added - diff]
gds/user_analog_project_wrapper.gds.gz[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/interactive.tcl[Added - diff]
verilog/rtl/ldo_all.v[Added - diff]
verilog/rtl/opentitan_soc_top.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[diff]

9 files changed

tree: 429f656573abb3f9e80e44f5965a2360b41aacdd

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.