sha1: Change the la_data_in[32+3] to [32+4]
Signed-off-by: Konrad Rzeszutek Wilk <konrad@kernel.org>
diff --git a/verilog/dv/caravel_test/wrapper.c b/verilog/dv/caravel_test/wrapper.c
index edb30cd..89d8db6 100644
--- a/verilog/dv/caravel_test/wrapper.c
+++ b/verilog/dv/caravel_test/wrapper.c
@@ -88,10 +88,10 @@
* All data go on la_data_in[127:0] , which starts
* at 0x2500,0000
*/
- reg_la1_iena = 0 << 3; /* 0x25000024: Input enable off */
- reg_la1_oenb = 0 << 3; /* 0x25000014: 32th, corresponds to active */
+ reg_la1_iena = 0 << 4; /* 0x25000024: Input enable off */
+ reg_la1_oenb = 0 << 4; /* 0x25000014: 32th, corresponds to active */
/* .active() HIGH */
- reg_la1_data = 1 << 3; /* 0x25000004 */
+ reg_la1_data = 1 << 4; /* 0x25000004 */
}
void reset(void)
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 67a612a..7bcb77b 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -53,7 +53,7 @@
output [31:0] wbs_dat_o;
input [3:0] wbs_sel_i;
- wrapper_sha1 wrapper_sha1 (.active(la_data_in[35]),
+ wrapper_sha1 wrapper_sha1 (.active(la_data_in[36]),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_ack_o(wbs_ack_o),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index a74edc1..2201b8e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,7 +25,7 @@
`include "gl/user_project_wrapper.v"
`else
`include "user_project_wrapper.v"
- // 3 ('SHA1',) : /home/konrad/sha1
+ // 4 ('SHA1',) : /home/konrad/sha1
`include "sha1/src/wrapper_sha1.v"
`include "sha1/src/sha1_wb.v"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 12d1dec..762568d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -117,7 +117,7 @@
.irq (user_irq),
// active input, only connect tristated outputs if this is high
- .active (la_data_in[32+3])
+ .active (la_data_in[32+4])
);
