indexed ports correctly on the layout. subckt ports match schematic.
2 files changed
tree: 6e5d9c6839d703383d29987ae1ea1583b19cfbd5
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitmodules
  10. info.yaml
  11. LICENSE
  12. Makefile
  13. README.md
README.md

Caravel Analog User

License UPRJ_CI Caravan Build


:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.