indexed ports correctly on the layout. subckt ports match schematic.

mag/cellA.mag

diff --git a/mag/cellA.mag b/mag/cellA.mag
index d26a0d7..ad663ea 100644
--- a/mag/cellA.mag
+++ b/mag/cellA.mag
@@ -1,10 +1,12 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1621484808
+timestamp 1621722353
 << metal2 >>
 rect -390 2430 40 2670
-rect -404 2000 142 2398
+rect 1420 2540 1900 2694
+rect -400 2000 42 2400
+rect -340 1910 -160 1970
 use sky130_fd_pr__res_high_po_0p35_L6NJBM  sky130_fd_pr__res_high_po_0p35_L6NJBM_0
 timestamp 1621480569
 transform 0 1 742 -1 0 2619
@@ -14,11 +16,12 @@
 transform 1 0 -252 0 1 2198
 box -138 -288 138 288
 << labels >>
-rlabel metal2 -144 2194 -144 2194 1 in
-port 0 n
-rlabel space -238 1936 -238 1936 1 vss
 rlabel metal2 -200 2538 -200 2538 1 out
-port 1 n
-rlabel space 1662 2616 1662 2616 1 vdd
 port 2 n
+rlabel metal2 -166 1934 -166 1934 1 vss
+port 3 n
+rlabel metal2 -34 2194 -34 2194 1 in
+port 0 n
+rlabel metal2 1670 2560 1670 2560 1 vdd
+port 1 n
 << end >>

mag/cellA.spice

diff --git a/mag/cellA.spice b/mag/cellA.spice
index 3c47343..ed1e938 100644
--- a/mag/cellA.spice
+++ b/mag/cellA.spice
@@ -2,7 +2,7 @@
 
 .option scale=5000u
 
-.subckt cellA out
+.subckt cellA in vdd out vss
 X0 sky130_fd_pr__nfet_g5v0d10v5_CEXLE5_0/a_80_n200# sky130_fd_pr__nfet_g5v0d10v5_CEXLE5_0/a_n80_n288# sky130_fd_pr__nfet_g5v0d10v5_CEXLE5_0/a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 ad=23200 pd=916 as=23200 ps=916 w=400 l=160
 X1 sky130_fd_pr__res_high_po_0p35_L6NJBM_0/a_n35_n1132# sky130_fd_pr__res_high_po_0p35_L6NJBM_0/a_n35_700# VSUBS sky130_fd_pr__res_high_po_0p35 l=1400
 .ends