verilog/rtl/sky130_hilas_TopLevelProtectStructure.v

/** Copyright 2020 The Hilas PDK Authors
 *
 * This file is part of HILAS.
 *
 * HILAS is free software: you can redistribute it and/or modify
 * it under the terms of the GNU Lesser General Public License as published by
 * the Free Software Foundation, version 3 of the License.
 *
 * HILAS is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public License
 * along with HILAS.  If not, see <https://www.gnu.org/licenses/>.
 *
 * Licensed under the Lesser General Public License, Version 3.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * https://www.gnu.org/licenses/lgpl-3.0.en.html
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * SPDX-License-Identifier: LGPL-3.0
 *
 *
 */
`ifndef SKY130_HILAS_TOPLEVELTESTSTRUCTURE
`define SKY130_HILAS_TOPLEVELTESTSTRUCTURE

/**
 * sky130_hilas_TopLevelTestStructure: top level test structure
 *
 * Verilog wrapper for sky130_hilas_TopLevelTestStructure.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopLevelTestStructure (
    DIG23,
    DIG22,
    DIG21,
    DIG29,
    DIG28,
    DIG27,
    DIG26,
    DIG25,
    DIG20,
    DIG19,
    DIG18,
    DIG17,
    DIG16,
    DIG15,
    DIG14,
    DIG13,
    DIG12,
    DIG11,
    DIG10,
    DIG09,
    DIG08,
    DIG07,
    DIG06,
    DIG05,
    DIG04,
    DIG03,
    DIG02,
    DIG01,
    GENERALGATE02,
    DRAINOUT,
    ROWTERM2,
    COLUMN2,
    COLUMN1,
    GATE2,
    DRAININJECT,
    VTUN,
    VREFCHAR,
    CHAROUTPUT,
    LARGECAPACITOR,
    DRAIN6N,
    DRAIN6P,
    DRAIN5P,
    DRAIN4P,
    DRAIN5N,
    DRAIN4N,
    DRAIN3P,
    DRAIN2P,
    DRAIN3N,
    SOURCEN,
    SOURCEP,
    GATE1,
    VINJ,
    VGND,
    VPWR,
    VNB,
    VPB
);
        inout DIG23;
        inout DIG22;
        inout DIG21;
        inout DIG29;
        inout DIG28;
        inout DIG27;
        inout DIG26;
        inout DIG25;
        inout DIG20;
        inout DIG19;
        inout DIG18;
        inout DIG17;
        inout DIG16;
        inout DIG15;
        inout DIG14;
        inout DIG13;
        inout DIG12;
        inout DIG11;
        inout DIG10;
        inout DIG09;
        inout DIG08;
        inout DIG07;
        inout DIG06;
        inout DIG05;
        inout DIG04;
        inout DIG03;
        inout DIG02;
        inout DIG01;
        inout GENERALGATE02;
        inout DRAINOUT;
        inout ROWTERM2;
        inout COLUMN2;
        inout COLUMN1;
        inout GATE2;
        inout DRAININJECT;
        inout VTUN;
        inout VREFCHAR;
        inout CHAROUTPUT;
        inout LARGECAPACITOR;
        inout DRAIN6N;
        inout DRAIN6P;
        inout DRAIN5P;
        inout DRAIN4P;
        inout DRAIN5N;
        inout DRAIN4N;
        inout DRAIN3P;
        inout DRAIN2P;
        inout DRAIN3N;
        inout SOURCEN;
        inout SOURCEP;
        inout GATE1;
        inout VINJ;
        inout VGND;
        inout VPWR;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopLevelTestStructure (
    DIG23,
    DIG22,
    DIG21,
    DIG29,
    DIG28,
    DIG27,
    DIG26,
    DIG25,
    DIG20,
    DIG19,
    DIG18,
    DIG17,
    DIG16,
    DIG15,
    DIG14,
    DIG13,
    DIG12,
    DIG11,
    DIG10,
    DIG09,
    DIG08,
    DIG07,
    DIG06,
    DIG05,
    DIG04,
    DIG03,
    DIG02,
    DIG01,
    GENERALGATE02,
    DRAINOUT,
    ROWTERM2,
    COLUMN2,
    COLUMN1,
    GATE2,
    DRAININJECT,
    VTUN,
    VREFCHAR,
    CHAROUTPUT,
    LARGECAPACITOR,
    DRAIN6N,
    DRAIN6P,
    DRAIN5P,
    DRAIN4P,
    DRAIN5N,
    DRAIN4N,
    DRAIN3P,
    DRAIN2P,
    DRAIN3N,
    SOURCEN,
    SOURCEP,
    GATE1,
    VINJ
);
        inout DIG23;
        inout DIG22;
        inout DIG21;
        inout DIG29;
        inout DIG28;
        inout DIG27;
        inout DIG26;
        inout DIG25;
        inout DIG20;
        inout DIG19;
        inout DIG18;
        inout DIG17;
        inout DIG16;
        inout DIG15;
        inout DIG14;
        inout DIG13;
        inout DIG12;
        inout DIG11;
        inout DIG10;
        inout DIG09;
        inout DIG08;
        inout DIG07;
        inout DIG06;
        inout DIG05;
        inout DIG04;
        inout DIG03;
        inout DIG02;
        inout DIG01;
        inout GENERALGATE02;
        inout DRAINOUT;
        inout ROWTERM2;
        inout COLUMN2;
        inout COLUMN1;
        inout GATE2;
        inout DRAININJECT;
        inout VTUN;
        inout VREFCHAR;
        inout CHAROUTPUT;
        inout LARGECAPACITOR;
        inout DRAIN6N;
        inout DRAIN6P;
        inout DRAIN5P;
        inout DRAIN4P;
        inout DRAIN5N;
        inout DRAIN4N;
        inout DRAIN3P;
        inout DRAIN2P;
        inout DRAIN3N;
        inout SOURCEN;
        inout SOURCEP;
        inout GATE1;
        inout VINJ;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TOPLEVELTESTSTRUCTURE