blob: 13b933b3bfb9bb42dacb5173ca5cab3db50f5a27 [file] [log] [blame]
---
project:
description: "Analog Std. Cells and Test Structures for Audio Processing and Analog Computing"
foundry: "SkyWater"
git_url: "https://gitlab.com/um-ece/ftl-lab/hilas"
organization: "The University of Mississippi and Georgia Tech"
organization_url: "https://ece.olemiss.edu"
owner: "Barry Muldrey"
process: "SKY130"
project_name: "Hilas Analog Synthesis Cell Test"
project_id: "157"
tags:
- "Open MPW"
- "Test Harness"
category: "Test Harness"
top_level_netlist: "caravel/verilog/gl/caravan.v"
user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
version: "1.00"
cover_image: "docs/source/_static/hilastop.png"