refreshed after Magic update (v8.3.196)

commit: 9ec92fea442f25877ace30ebac0e6a9a1e004aa5 [log] [tgz]
author: Barry Muldrey <Barry Muldrey> Thu Aug 19 11:17:32 2021 -0500
committer: Barry Muldrey <Barry Muldrey> Thu Aug 19 11:17:32 2021 -0500
tree: b0ff80bcfbef7ed6c19a28d9b113921375a8f499
parent: dcc9b3419b1bb01239059501f3f8d89f9ac4e1f7 [diff]
diff --git a/checks/erase_box_user_analog_project_wrapper.gds.log b/checks/erase_box_user_analog_project_wrapper.gds.log
index a86b905..1408d61 100644
--- a/checks/erase_box_user_analog_project_wrapper.gds.log
+++ b/checks/erase_box_user_analog_project_wrapper.gds.log

@@ -1,6 +1,6 @@
 /home/bjmuld/work/mpw2/gds//user_analog_project_wrapper.gds /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_erased.gds user_analog_project_wrapper
 
-Magic 8.3 revision 182 - Compiled on Sat Jul 24 11:39:08 UTC 2021.
+Magic 8.3 revision 196 - Compiled on Tue Aug 10 18:40:01 UTC 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
 Using NULL graphics device.
@@ -34,7 +34,6 @@
 
 microns:  3006.00 x 37.00   (-43.00,  3520.00), ( 2963.00,  3557.00)  111222.00 
 lambda:     3006 x 37      (   -43,  3520 ), (  2963,  3557 )  111222    
-can't read "errorCode": no such variable
 Unrecognized layer: metal5
 Layer names are:
     mag or magnet

diff --git a/checks/erase_box_user_analog_project_wrapper_empty.gds.log b/checks/erase_box_user_analog_project_wrapper_empty.gds.log
index 45cabd9..0c83074 100644
--- a/checks/erase_box_user_analog_project_wrapper_empty.gds.log
+++ b/checks/erase_box_user_analog_project_wrapper_empty.gds.log

@@ -1,6 +1,6 @@
 /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty.gds /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds user_analog_project_wrapper
 
-Magic 8.3 revision 182 - Compiled on Sat Jul 24 11:39:08 UTC 2021.
+Magic 8.3 revision 196 - Compiled on Tue Aug 10 18:40:01 UTC 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
 Using NULL graphics device.
@@ -34,7 +34,6 @@
 
 microns:  3006.00 x 37.00   (-43.00,  3520.00), ( 2963.00,  3557.00)  111222.00 
 lambda:     3006 x 37      (   -43,  3520 ), (  2963,  3557 )  111222    
-can't read "errorCode": no such variable
 Unrecognized layer: metal5
 Layer names are:
     mag or magnet

diff --git a/checks/full_log.log b/checks/full_log.log
index f76ab70..0e9320d 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log

@@ -3,8 +3,8 @@
 Step 0 done without fatal errors.
  Executing Step 1 of 9: Project License Check
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- SPDX COMPLIANCE Found 61 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/bjmuld/work/mpw2/.gitmodules~', '/home/bjmuld/work/mpw2/README.md', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sch', '/home/bjmuld/work/mpw2/xschem/xschemrc', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sym']
+ SPDX COMPLIANCE Found 60 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/bjmuld/work/mpw2/README.md', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch']
  Executing Step 2 of 9: YAML File Check
  YAML file valid!
 Step 2 done without fatal errors.
@@ -40,7 +40,7 @@
 Step 6 done without fatal errors.
  Executing Step 7 of 9: KLayout DRC Violations Check
  Running Klayout DRC Checks...
- Klayout DRC Checks on GDS Failed, Reason: Total # of DRC violations is 4 Please check /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_klayout_drc.xmlFor more details
+ Klayout DRC Checks on GDS Failed, Reason: Total # of DRC violations is 5 Please check /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_klayout_drc.xmlFor more details
 TEST FAILED AT STEP 7
  Executing Klayout offgrid check.
  Klayout offgrid Checks on User Project GDS Passed!

diff --git a/checks/klayout_drc.log b/checks/klayout_drc.log
index dfc4ad3..eaa31ae 100644
--- a/checks/klayout_drc.log
+++ b/checks/klayout_drc.log

@@ -1,359 +1,528 @@
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-Elapsed: 0.010s
-"_output" in: sky130A_mr.lydrc:450
-Elapsed: 0.000s
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 1073.00M
+"isolated" in: sky130A_mr.lydrc:447
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:447
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1073.00M
+"enclosing" in: sky130A_mr.lydrc:448
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:448
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
+"enclosing" in: sky130A_mr.lydrc:449
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:449
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1073.00M
+"separation" in: sky130A_mr.lydrc:450
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:450
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
 FEOL section
 hvi
-"width_check" in: sky130A_mr.lydrc:766
-Elapsed: 0.010s
-"_output" in: sky130A_mr.lydrc:766
-Elapsed: 0.010s
+"width" in: sky130A_mr.lydrc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
 hvntm
-"width_check" in: sky130A_mr.lydrc:792
-Elapsed: 0.010s
-"_output" in: sky130A_mr.lydrc:792
-Elapsed: 0.000s
-"isolated_check" in: sky130A_mr.lydrc:793
-Elapsed: 0.010s
-"_output" in: sky130A_mr.lydrc:793
-Elapsed: 0.010s
+"width" in: sky130A_mr.lydrc:792
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:792
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1073.00M
+"isolated" in: sky130A_mr.lydrc:793
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1073.00M
+"output" in: sky130A_mr.lydrc:793
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1073.00M
 Writing report database: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_klayout_drc.xml ..
-Total run time: 1.450s
+Total elapsed: 1.490s  Memory: 1071.00M

diff --git a/checks/klayout_drc_total.txt b/checks/klayout_drc_total.txt
index bf0d87a..7813681 100644
--- a/checks/klayout_drc_total.txt
+++ b/checks/klayout_drc_total.txt

@@ -1 +1 @@
-4
\ No newline at end of file
+5
\ No newline at end of file

diff --git a/checks/magic_drc.log b/checks/magic_drc.log
index 15a53b6..e1f7b05 100644
--- a/checks/magic_drc.log
+++ b/checks/magic_drc.log

@@ -1,14 +1,14 @@
 
-Magic 8.3 revision 182 - Compiled on Sat Jul 24 11:39:08 UTC 2021.
+Magic 8.3 revision 196 - Compiled on Tue Aug 10 18:40:01 UTC 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
 Using NULL graphics device.
 Processing system .magicrc file
 Sourcing design .magicrc for technology sky130A ...
 2 Magic internal units = 1 Lambda
-Could not find file '/home/bjmuld/work/cells//sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+Could not find file '/home/bjmuld/work/cells/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
          . /build/lib/magic/sys /build/lib/magic/sys/current
-Error parsing ".magicrc": couldn't read file "/home/bjmuld/work/cells//sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Error parsing ".magicrc": couldn't read file "/home/bjmuld/work/cells/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
 Bad local startup file ".magicrc", continuing without.
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading "/usr/local/bin/drc_checks/magic_drc_check.tcl" from command line.

diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index eceed1a..90eab95 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log

@@ -1,63 +1,62 @@
 FULL RUN LOG:
 SPDX NON-COMPLIANT FILES
-/home/bjmuld/work/mpw2/.gitmodules~
 /home/bjmuld/work/mpw2/README.md
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sch
-/home/bjmuld/work/mpw2/xschem/xschemrc
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sym
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sym
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_cellAttempt01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sch
+/home/bjmuld/work/mpw2/xschem/xschemrc
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sym
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_cellAttempt01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_cellAttempt01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sym
 /home/bjmuld/work/mpw2/verilog/rtl/sky130_hilas_sc.v

diff --git a/checks/user_analog_project_wrapper_klayout_drc.xml b/checks/user_analog_project_wrapper_klayout_drc.xml
index 4acb517..400ea2c 100644
--- a/checks/user_analog_project_wrapper_klayout_drc.xml
+++ b/checks/user_analog_project_wrapper_klayout_drc.xml

@@ -216,26 +216,6 @@
    </references>
   </cell>
   <cell>
-   <name>sky130_hilas_drainSelect01</name>
-   <variant/>
-   <references>
-    <ref>
-     <parent>user_analog_project_wrapper</parent>
-     <trans>r180 *1 1535.26,3305.55</trans>
-    </ref>
-   </references>
-  </cell>
-  <cell>
-   <name>sky130_hilas_TgateVinj01</name>
-   <variant/>
-   <references>
-    <ref>
-     <parent>user_analog_project_wrapper</parent>
-     <trans>m90 *1 1522.44,3302.89</trans>
-    </ref>
-   </references>
-  </cell>
-  <cell>
    <name>sky130_hilas_FGcharacterization01</name>
    <variant/>
    <references>
@@ -256,6 +236,26 @@
    </references>
   </cell>
   <cell>
+   <name>sky130_hilas_drainSelect01</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>r180 *1 1535.25,3325.29</trans>
+    </ref>
+   </references>
+  </cell>
+  <cell>
+   <name>sky130_hilas_TgateVinj01</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>m90 *1 1522.43,3322.63</trans>
+    </ref>
+   </references>
+  </cell>
+  <cell>
    <name>sky130_hilas_RightProtection</name>
    <variant/>
    <references>
@@ -300,23 +300,12 @@
   <item>
    <tags/>
    <category>'difftap.3'</category>
-   <cell>sky130_hilas_TgateVinj01</cell>
+   <cell>sky130_hilas_FGcharacterization01</cell>
    <visited>false</visited>
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (-1.77,-0.12;-1.77,0.25)/(-1.89,0.492;-1.89,-0.07)</value>
-   </values>
-  </item>
-  <item>
-   <tags/>
-   <category>'difftap.3'</category>
-   <cell>sky130_hilas_TgateVinj01</cell>
-   <visited>false</visited>
-   <multiplicity>1</multiplicity>
-   <image/>
-   <values>
-    <value>edge-pair: (-1.77,0.55;-1.77,0.91)/(-1.89,0.86;-1.89,0.308)</value>
+    <value>edge-pair: (2.97,6.36;2.97,6.75)|(2.72,6.75;2.72,6.33)</value>
    </values>
   </item>
   <item>
@@ -327,7 +316,29 @@
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (0.73,-0.19;0.73,0.2)/(0.48,0.2;0.48,-0.22)</value>
+    <value>edge-pair: (0.73,-0.19;0.73,0.2)|(0.48,0.2;0.48,-0.22)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'difftap.3'</category>
+   <cell>sky130_hilas_TgateVinj01</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (-1.77,0.55;-1.77,0.91)|(-1.89,0.86;-1.89,0.308)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'difftap.3'</category>
+   <cell>sky130_hilas_TgateVinj01</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (-1.77,-0.12;-1.77,0.25)|(-1.89,0.492;-1.89,-0.07)</value>
    </values>
   </item>
   <item>
@@ -338,7 +349,7 @@
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (8.32,4.72;18.5,4.72)/(18.641,4.95;8.179,4.95)</value>
+    <value>edge-pair: (8.32,4.72;18.5,4.72)|(18.641,4.95;8.179,4.95)</value>
    </values>
   </item>
  </items>

diff --git a/checks/xor.log b/checks/xor.log
index 096a006..b4baf17 100644
--- a/checks/xor.log
+++ b/checks/xor.log

@@ -3,9 +3,9 @@
 Design Name: xor_target
 Output GDS will be: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper.xor.gds
 Reading /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds ..
-ERROR: In /usr/local/bin/xor_checks/xor.drc: Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read
-ERROR: Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read in MacroInterpreter::execute
-  /usr/local/bin/xor_checks/xor.drc:15:in `execute_drc'
-  :/built-in-macros/drc_interpreters.lym:18:in `instance_eval'
-  :/built-in-macros/drc_interpreters.lym:18:in `execute_drc'
-  :/built-in-macros/drc_interpreters.lym:92:in `execute'
+ERROR: In /usr/local/bin/xor_checks/xor.drc: 'source': Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read
+Total elapsed: 0.000s  Memory: 519.00M
+ERROR: 'source': Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read in Executable::execute
+  /usr/local/bin/xor_checks/xor.drc:15:in `execute'
+  :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+  :/built-in-macros/drc_interpreters.lym:27:in `execute'

diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index b2ec0d4..ba31c76 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ

diff --git a/verilog/rtl/sky130_hilas_sc.v b/verilog/rtl/sky130_hilas_sc.v
index 14cb803..bcdc2bc 100644
--- a/verilog/rtl/sky130_hilas_sc.v
+++ b/verilog/rtl/sky130_hilas_sc.v

@@ -36,13 +36,13 @@
 
 `define USE_POWER_PINS 1
 
-`ifndef SKY130_HILAS_VINJDIODEPROTECT01
-`define SKY130_HILAS_VINJDIODEPROTECT01
+`ifndef SKY130_HILAS_PTRANSISTORPAIR
+`define SKY130_HILAS_PTRANSISTORPAIR
 
 /**
- * sky130_hilas_VinjDiodeProtect01: protective ESD diode for VINJ line
+ * sky130_hilas_pTransistorPair: None
  *
- * Verilog wrapper for sky130_hilas_VinjDiodeProtect01.
+ * Verilog wrapper for sky130_hilas_pTransistorPair.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -55,15 +55,91 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjDiodeProtect01 (
-    VINJ,
-    INPUT,
+module sky130_hilas_pTransistorPair (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorPair (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PTRANSISTORPAIR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATE4DOUBLE01
+`define SKY130_HILAS_TGATE4DOUBLE01
+
+/**
+ * sky130_hilas_Tgate4Double01: 4 double-throw transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_Tgate4Double01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Double01 (
+    INPUT1_1,
+    SELECT1,
+    SELECT2,
+    INPUT2_2,
+    INPUT1_2,
+    SELECT3,
+    INPUT2_3,
+    SELECT4,
+    INPUT2_4,
+    INPUT1_4,
+    OUTPUT4,
+    OUTPUT3,
+    OUTPUT2,
+    OUTPUT1,
+    INPUT2_1,
+    INPUT1_3,
     VGND,
     VNB,
     VPB
 );
-        inout VINJ;
-        inout INPUT;
+        inout INPUT1_1;
+        inout SELECT1;
+        inout SELECT2;
+        inout INPUT2_2;
+        inout INPUT1_2;
+        inout SELECT3;
+        inout INPUT2_3;
+        inout SELECT4;
+        inout INPUT2_4;
+        inout INPUT1_4;
+        inout OUTPUT4;
+        inout OUTPUT3;
+        inout OUTPUT2;
+        inout OUTPUT1;
+        inout INPUT2_1;
+        inout INPUT1_3;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -75,12 +151,40 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjDiodeProtect01 (
-    VINJ,
-    INPUT
+module sky130_hilas_Tgate4Double01 (
+    INPUT1_1,
+    SELECT1,
+    SELECT2,
+    INPUT2_2,
+    INPUT1_2,
+    SELECT3,
+    INPUT2_3,
+    SELECT4,
+    INPUT2_4,
+    INPUT1_4,
+    OUTPUT4,
+    OUTPUT3,
+    OUTPUT2,
+    OUTPUT1,
+    INPUT2_1,
+    INPUT1_3
 );
-        inout VINJ;
-        inout INPUT;
+        inout INPUT1_1;
+        inout SELECT1;
+        inout SELECT2;
+        inout INPUT2_2;
+        inout INPUT1_2;
+        inout SELECT3;
+        inout INPUT2_3;
+        inout SELECT4;
+        inout INPUT2_4;
+        inout INPUT1_4;
+        inout OUTPUT4;
+        inout OUTPUT3;
+        inout OUTPUT2;
+        inout OUTPUT1;
+        inout INPUT2_1;
+        inout INPUT1_3;
 endmodule
 `endcelldefine
 
@@ -88,18 +192,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_VINJDIODEPROTECT01
+`endif  // SKY130_HILAS_TGATE4DOUBLE01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_TGATESINGLE01PART2
-`define SKY130_HILAS_TGATESINGLE01PART2
+`ifndef SKY130_HILAS_TGATE4SINGLE01
+`define SKY130_HILAS_TGATE4SINGLE01
 
 /**
- * sky130_hilas_TgateSingle01Part2: None
+ * sky130_hilas_Tgate4Single01: 4 single-throw transmission gates
  *
- * Verilog wrapper for sky130_hilas_TgateSingle01Part2.
+ * Verilog wrapper for sky130_hilas_Tgate4Single01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -112,7 +216,106 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateSingle01Part2 (
+module sky130_hilas_Tgate4Single01 (
+    INPUT1_2,
+    SELECT2,
+    OUTPUT2,
+    OUTPUT4,
+    OUTPUT3,
+    OUTPUT1,
+    INPUT1_4,
+    SELECT4,
+    SELECT3,
+    INPUT1_3,
+    SELECT1,
+    INPUT1_1,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout INPUT1_2;
+        inout SELECT2;
+        inout OUTPUT2;
+        inout OUTPUT4;
+        inout OUTPUT3;
+        inout OUTPUT1;
+        inout INPUT1_4;
+        inout SELECT4;
+        inout SELECT3;
+        inout INPUT1_3;
+        inout SELECT1;
+        inout INPUT1_1;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Single01 (
+    INPUT1_2,
+    SELECT2,
+    OUTPUT2,
+    OUTPUT4,
+    OUTPUT3,
+    OUTPUT1,
+    INPUT1_4,
+    SELECT4,
+    SELECT3,
+    INPUT1_3,
+    SELECT1,
+    INPUT1_1
+);
+        inout INPUT1_2;
+        inout SELECT2;
+        inout OUTPUT2;
+        inout OUTPUT4;
+        inout OUTPUT3;
+        inout OUTPUT1;
+        inout INPUT1_4;
+        inout SELECT4;
+        inout SELECT3;
+        inout INPUT1_3;
+        inout SELECT1;
+        inout INPUT1_1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATE4SINGLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_MCAP2M4
+`define SKY130_HILAS_MCAP2M4
+
+/**
+ * sky130_hilas_mcap2m4: metal capacitor layer contact to m4
+ *
+ * Verilog wrapper for sky130_hilas_mcap2m4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_mcap2m4 (
     VNB,
     VPB
 );
@@ -126,7 +329,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateSingle01Part2 (
+module sky130_hilas_mcap2m4 (
     
 );
 endmodule
@@ -136,7 +339,297 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_TGATESINGLE01PART2
+`endif  // SKY130_HILAS_MCAP2M4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUP_CAP_01
+`define SKY130_HILAS_DECOUP_CAP_01
+
+/**
+ * sky130_hilas_decoup_cap_01: decoupling cap (intended as fill), variant
+ *
+ * Verilog wrapper for sky130_hilas_decoup_cap_01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_01 (
+    VPWR,
+    VNB,
+    VPB
+);
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DECOUP_CAP_01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFET03
+`define SKY130_HILAS_NFET03
+
+/**
+ * sky130_hilas_nFET03: None
+ *
+ * Verilog wrapper for sky130_hilas_nFET03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFET03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_M22M4
+`define SKY130_HILAS_M22M4
+
+/**
+ * sky130_hilas_m22m4: m2 to m4 contact
+ *
+ * Verilog wrapper for sky130_hilas_m22m4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m22m4 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m22m4 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_M22M4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMIRROR02
+`define SKY130_HILAS_PFETMIRROR02
+
+/**
+ * sky130_hilas_pFETmirror02: second pFET current mirror
+ *
+ * Verilog wrapper for sky130_hilas_pFETmirror02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETMIRROR02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01A
+`define SKY130_HILAS_PFETDEVICE01A
+
+/**
+ * sky130_hilas_pFETdevice01a: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMIRROR
+`define SKY130_HILAS_PFETMIRROR
+
+/**
+ * sky130_hilas_pFETmirror: pFET current mirror
+ *
+ * Verilog wrapper for sky130_hilas_pFETmirror.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETMIRROR
 
 
 //--------EOF---------
@@ -189,13 +682,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_NFET03A
-`define SKY130_HILAS_NFET03A
+`ifndef SKY130_HILAS_POLY2M2
+`define SKY130_HILAS_POLY2M2
 
 /**
- * sky130_hilas_nFET03a: None
+ * sky130_hilas_poly2m2: polysilicon layer to m2 contact
  *
- * Verilog wrapper for sky130_hilas_nFET03a.
+ * Verilog wrapper for sky130_hilas_poly2m2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -208,7 +701,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFET03a (
+module sky130_hilas_poly2m2 (
     VNB,
     VPB
 );
@@ -222,7 +715,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFET03a (
+module sky130_hilas_poly2m2 (
     
 );
 endmodule
@@ -232,18 +725,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NFET03A
+`endif  // SKY130_HILAS_POLY2M2
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01
+`ifndef SKY130_HILAS_WELLCONTACT
+`define SKY130_HILAS_WELLCONTACT
 
 /**
- * sky130_hilas_DAC6TransistorStack01: None
+ * sky130_hilas_wellContact: contact to a well block, typically used for contacting tunneling junctions in a well.
  *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01.
+ * Verilog wrapper for sky130_hilas_wellContact.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -256,7 +749,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6TransistorStack01 (
+module sky130_hilas_wellContact (
     VNB,
     VPB
 );
@@ -270,7 +763,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6TransistorStack01 (
+module sky130_hilas_wellContact (
     
 );
 endmodule
@@ -280,7 +773,106 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01
+`endif  // SKY130_HILAS_WELLCONTACT
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2CELL_NOFG
+`define SKY130_HILAS_TA2CELL_NOFG
+
+/**
+ * sky130_hilas_TA2Cell_NoFG: Two transimpedane amplifiers with no floating-gate inputs.
+ *
+ * Verilog wrapper for sky130_hilas_TA2Cell_NoFG.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_NoFG (
+    COLSEL1,
+    VIN12,
+    VIN21,
+    VIN22,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    VTUN,
+    GATE1,
+    VINJ,
+    VIN11,
+    VGND,
+    VPWR,
+    VNB,
+    VPB
+);
+        inout COLSEL1;
+        inout VIN12;
+        inout VIN21;
+        inout VIN22;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout VIN11;
+        inout VGND;
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_NoFG (
+    COLSEL1,
+    VIN12,
+    VIN21,
+    VIN22,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    VTUN,
+    GATE1,
+    VINJ,
+    VIN11
+);
+        inout COLSEL1;
+        inout VIN12;
+        inout VIN21;
+        inout VIN22;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout VIN11;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TA2CELL_NOFG
 
 
 //--------EOF---------
@@ -400,6 +992,573 @@
 
 //--------EOF---------
 
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01C
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01C
+
+/**
+ * sky130_hilas_DAC6TransistorStack01c: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01c.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01c (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01c (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01C
+
+
+//--------EOF---------
+
+`ifndef M12M3
+`define M12M3
+
+/**
+ * m12m3: 
+ *
+ * Verilog wrapper for m12m3.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module m12m3 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module m12m3 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // M12M3
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGCHARACTERIZATION01
+`define SKY130_HILAS_FGCHARACTERIZATION01
+
+/**
+ * sky130_hilas_FGcharacterization01: FG test strucure that uses a capacitor around a transconductance amplifier
+ *
+ * Verilog wrapper for sky130_hilas_FGcharacterization01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGcharacterization01 (
+    VTUN,
+    GATE1,
+    GATE3,
+    VTUNOVERLAP01,
+    GATE2,
+    GATE4,
+    LARGECAPACITOR,
+    VINJ,
+    OUTPUT,
+    VREF,
+    VBIAS,
+    DRAIN1,
+    SOURCE1,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VTUN;
+        inout GATE1;
+        inout GATE3;
+        inout VTUNOVERLAP01;
+        inout GATE2;
+        inout GATE4;
+        inout LARGECAPACITOR;
+        inout VINJ;
+        inout OUTPUT;
+        inout VREF;
+        inout VBIAS;
+        inout DRAIN1;
+        inout SOURCE1;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGcharacterization01 (
+    VTUN,
+    GATE1,
+    GATE3,
+    VTUNOVERLAP01,
+    GATE2,
+    GATE4,
+    LARGECAPACITOR,
+    VINJ,
+    OUTPUT,
+    VREF,
+    VBIAS,
+    DRAIN1,
+    SOURCE1
+);
+        inout VTUN;
+        inout GATE1;
+        inout GATE3;
+        inout VTUNOVERLAP01;
+        inout GATE2;
+        inout GATE4;
+        inout LARGECAPACITOR;
+        inout VINJ;
+        inout OUTPUT;
+        inout VREF;
+        inout VBIAS;
+        inout DRAIN1;
+        inout SOURCE1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGCHARACTERIZATION01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_INVERT01
+`define SKY130_HILAS_INVERT01
+
+/**
+ * sky130_hilas_invert01: None
+ *
+ * Verilog wrapper for sky130_hilas_invert01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_invert01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_invert01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_INVERT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORCAPACITOR02
+`define SKY130_HILAS_FGVARACTORCAPACITOR02
+
+/**
+ * sky130_hilas_FGVaractorCapacitor02: variant 2, varactor cap for floating-gate charge storage
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorCapacitor02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGVARACTORCAPACITOR02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TACOREBLOCK
+`define SKY130_HILAS_TACOREBLOCK
+
+/**
+ * sky130_hilas_TACoreBlock: None
+ *
+ * Verilog wrapper for sky130_hilas_TACoreBlock.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TACOREBLOCK
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP01
+`define SKY130_HILAS_OVERLAPCAP01
+
+/**
+ * sky130_hilas_overlapCap01: overlap capacitor based capacitor
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_OVERLAPCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DRAINSELECT01
+`define SKY130_HILAS_DRAINSELECT01
+
+/**
+ * sky130_hilas_drainSelect01: multiplexor for drain selection for 4 drain lines, pitch matched
+ *
+ * Verilog wrapper for sky130_hilas_drainSelect01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_drainSelect01 (
+    DRAIN3,
+    VINJ,
+    DRAIN_MUX,
+    SELECT2,
+    SELECT1,
+    SELECT3,
+    SELECT4,
+    VGND,
+    VNB,
+    VPB
+);
+        inout DRAIN3;
+        inout VINJ;
+        inout DRAIN_MUX;
+        inout SELECT2;
+        inout SELECT1;
+        inout SELECT3;
+        inout SELECT4;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_drainSelect01 (
+    DRAIN3,
+    VINJ,
+    DRAIN_MUX,
+    SELECT2,
+    SELECT1,
+    SELECT3,
+    SELECT4
+);
+        inout DRAIN3;
+        inout VINJ;
+        inout DRAIN_MUX;
+        inout SELECT2;
+        inout SELECT1;
+        inout SELECT3;
+        inout SELECT4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DRAINSELECT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGTRANS2X1CELL
+`define SKY130_HILAS_FGTRANS2X1CELL
+
+/**
+ * sky130_hilas_FGtrans2x1cell: None
+ *
+ * Verilog wrapper for sky130_hilas_FGtrans2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGtrans2x1cell (
+    COLSEL1,
+    VINJ,
+    DRAIN1,
+    DRAIN2,
+    PROG,
+    RUN,
+    VIN2,
+    VIN1,
+    GATE1,
+    VTUN,
+    COL1,
+    ROW1,
+    ROW2,
+    VGND,
+    VNB,
+    VPB
+);
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout PROG;
+        inout RUN;
+        inout VIN2;
+        inout VIN1;
+        inout GATE1;
+        inout VTUN;
+        inout COL1;
+        inout ROW1;
+        inout ROW2;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGtrans2x1cell (
+    COLSEL1,
+    VINJ,
+    DRAIN1,
+    DRAIN2,
+    PROG,
+    RUN,
+    VIN2,
+    VIN1,
+    GATE1,
+    VTUN,
+    COL1,
+    ROW1,
+    ROW2
+);
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout PROG;
+        inout RUN;
+        inout VIN2;
+        inout VIN1;
+        inout GATE1;
+        inout VTUN;
+        inout COL1;
+        inout ROW1;
+        inout ROW2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGTRANS2X1CELL
+
+
+//--------EOF---------
+
 `ifndef SKY130_HILAS_WTA4STAGE01
 `define SKY130_HILAS_WTA4STAGE01
 
@@ -448,13 +1607,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETMED
-`define SKY130_HILAS_PFETMED
+`ifndef SKY130_HILAS_CAPACITORSIZE01
+`define SKY130_HILAS_CAPACITORSIZE01
 
 /**
- * sky130_hilas_pFETmed: Medium-sized (W/L=10) pFET transistor
+ * sky130_hilas_capacitorSize01: smallest cap
  *
- * Verilog wrapper for sky130_hilas_pFETmed.
+ * Verilog wrapper for sky130_hilas_capacitorSize01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -467,7 +1626,167 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETmed (
+module sky130_hilas_capacitorSize01 (
+    CAPTERM02,
+    CAPTERM01,
+    VNB,
+    VPB
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize01 (
+    CAPTERM02,
+    CAPTERM01
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPACITORSIZE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X2CELL
+`define SKY130_HILAS_SWC4X2CELL
+
+/**
+ * sky130_hilas_swc4x2cell: 4x2 array of FG switch cell, Varactor capacitor cell
+ *
+ * Verilog wrapper for sky130_hilas_swc4x2cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cell (
+    DRAIN1,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4,
+    GATE1,
+    GATE2,
+    GATESELECT1,
+    GATESELECT2,
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
+    VINJ,
+    VTUN,
+    VGND,
+    VNB,
+    VPB
+);
+        inout DRAIN1;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout GATE1;
+        inout GATE2;
+        inout GATESELECT1;
+        inout GATESELECT2;
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
+        inout VINJ;
+        inout VTUN;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cell (
+    DRAIN1,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4,
+    GATE1,
+    GATE2,
+    GATESELECT1,
+    GATESELECT2,
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
+    VINJ,
+    VTUN
+);
+        inout DRAIN1;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout GATE1;
+        inout GATE2;
+        inout GATESELECT1;
+        inout GATESELECT2;
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
+        inout VINJ;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X2CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NMIRROR03
+`define SKY130_HILAS_NMIRROR03
+
+/**
+ * sky130_hilas_nMirror03: None
+ *
+ * Verilog wrapper for sky130_hilas_nMirror03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nMirror03 (
     VNB,
     VPB
 );
@@ -481,7 +1800,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETmed (
+module sky130_hilas_nMirror03 (
     
 );
 endmodule
@@ -491,7 +1810,648 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_PFETMED
+`endif  // SKY130_HILAS_NMIRROR03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01
+
+/**
+ * sky130_hilas_DAC6TransistorStack01: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TACOREBLOCK2
+`define SKY130_HILAS_TACOREBLOCK2
+
+/**
+ * sky130_hilas_TACoreBlock2: None
+ *
+ * Verilog wrapper for sky130_hilas_TACoreBlock2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TACOREBLOCK2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMIRRORPAIRS
+`define SKY130_HILAS_NFETMIRRORPAIRS
+
+/**
+ * sky130_hilas_nFETmirrorPairs: pairs of nFET current mirrors
+ *
+ * Verilog wrapper for sky130_hilas_nFETmirrorPairs.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETMIRRORPAIRS
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZPCELL01
+`define SKY130_HILAS_HORIZPCELL01
+
+/**
+ * sky130_hilas_horizPcell01: None
+ *
+ * Verilog wrapper for sky130_hilas_horizPcell01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizPcell01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizPcell01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_HORIZPCELL01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMED
+`define SKY130_HILAS_NFETMED
+
+/**
+ * sky130_hilas_nFETmed: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETmed.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmed (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmed (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETMED
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TOPPROTECTION
+`define SKY130_HILAS_TOPPROTECTION
+
+/**
+ * sky130_hilas_TopProtection: 
+ *
+ * Verilog wrapper for sky130_hilas_TopProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopProtection (
+    ANALOG00,
+    ANALOG01,
+    ANALOG02,
+    ANALOG03,
+    ANALOG04,
+    ANALOG05,
+    ANALOG06,
+    ANALOG07,
+    ANALOG08,
+    ANALOG09,
+    ANALOG10,
+    PIN1,
+    PIN2,
+    PIN3,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    VTUN,
+    VNB,
+    VPB
+);
+        inout ANALOG00;
+        inout ANALOG01;
+        inout ANALOG02;
+        inout ANALOG03;
+        inout ANALOG04;
+        inout ANALOG05;
+        inout ANALOG06;
+        inout ANALOG07;
+        inout ANALOG08;
+        inout ANALOG09;
+        inout ANALOG10;
+        inout PIN1;
+        inout PIN2;
+        inout PIN3;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout VTUN;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopProtection (
+    ANALOG00,
+    ANALOG01,
+    ANALOG02,
+    ANALOG03,
+    ANALOG04,
+    ANALOG05,
+    ANALOG06,
+    ANALOG07,
+    ANALOG08,
+    ANALOG09,
+    ANALOG10,
+    PIN1,
+    PIN2,
+    PIN3,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    VTUN
+);
+        inout ANALOG00;
+        inout ANALOG01;
+        inout ANALOG02;
+        inout ANALOG03;
+        inout ANALOG04;
+        inout ANALOG05;
+        inout ANALOG06;
+        inout ANALOG07;
+        inout ANALOG08;
+        inout ANALOG09;
+        inout ANALOG10;
+        inout PIN1;
+        inout PIN2;
+        inout PIN3;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TOPPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC2X2VARACTOR
+`define SKY130_HILAS_SWC2X2VARACTOR
+
+/**
+ * sky130_hilas_swc2x2varactor: ??  Is this part of the library?
+ *
+ * Verilog wrapper for sky130_hilas_swc2x2varactor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc2x2varactor (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc2x2varactor (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC2X2VARACTOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LEVELSHIFT4INPUTUP
+`define SKY130_HILAS_LEVELSHIFT4INPUTUP
+
+/**
+ * sky130_hilas_LevelShift4InputUp: 4-channel level shifter
+ *
+ * Verilog wrapper for sky130_hilas_LevelShift4InputUp.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LevelShift4InputUp (
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LevelShift4InputUp (
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4
+);
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_LEVELSHIFT4INPUTUP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01
+`define SKY130_HILAS_PFETDEVICE01
+
+/**
+ * sky130_hilas_pFETdevice01: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2SIGNALBIASCELL
+`define SKY130_HILAS_TA2SIGNALBIASCELL
+
+/**
+ * sky130_hilas_TA2SignalBiasCell: None
+ *
+ * Verilog wrapper for sky130_hilas_TA2SignalBiasCell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2SignalBiasCell (
+    VOUT_AMP2,
+    VOUT_AMP1,
+    VIN22,
+    VIN21,
+    VIN11,
+    VIN12,
+    VBIAS2,
+    VBIAS1,
+    VGND,
+    VPWR,
+    VNB,
+    VPB
+);
+        inout VOUT_AMP2;
+        inout VOUT_AMP1;
+        inout VIN22;
+        inout VIN21;
+        inout VIN11;
+        inout VIN12;
+        inout VBIAS2;
+        inout VBIAS1;
+        inout VGND;
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2SignalBiasCell (
+    VOUT_AMP2,
+    VOUT_AMP1,
+    VIN22,
+    VIN21,
+    VIN11,
+    VIN12,
+    VBIAS2,
+    VBIAS1
+);
+        inout VOUT_AMP2;
+        inout VOUT_AMP1;
+        inout VIN22;
+        inout VIN21;
+        inout VIN11;
+        inout VIN12;
+        inout VBIAS2;
+        inout VBIAS1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TA2SIGNALBIASCELL
 
 
 //--------EOF---------
@@ -551,261 +2511,6 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_SWC4X2CELLOVERLAP
-`define SKY130_HILAS_SWC4X2CELLOVERLAP
-
-/**
- * sky130_hilas_swc4x2cellOverlap: Core switch cell, built with overlap capacitor
- *
- * Verilog wrapper for sky130_hilas_swc4x2cellOverlap.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x2cellOverlap (
-    VERT1,
-    HORIZ1,
-    DRAIN1,
-    HORIZ2,
-    DRAIN2,
-    DRAIN3,
-    HORIZ3,
-    HORIZ4,
-    DRAIN4,
-    VINJ,
-    GATESELECT1,
-    VERT2,
-    GATESELECT2,
-    GATE2,
-    GATE1,
-    VTUN,
-    VNB,
-    VPB
-);
-        inout VERT1;
-        inout HORIZ1;
-        inout DRAIN1;
-        inout HORIZ2;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout HORIZ3;
-        inout HORIZ4;
-        inout DRAIN4;
-        inout VINJ;
-        inout GATESELECT1;
-        inout VERT2;
-        inout GATESELECT2;
-        inout GATE2;
-        inout GATE1;
-        inout VTUN;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x2cellOverlap (
-    VERT1,
-    HORIZ1,
-    DRAIN1,
-    HORIZ2,
-    DRAIN2,
-    DRAIN3,
-    HORIZ3,
-    HORIZ4,
-    DRAIN4,
-    VINJ,
-    GATESELECT1,
-    VERT2,
-    GATESELECT2,
-    GATE2,
-    GATE1,
-    VTUN
-);
-        inout VERT1;
-        inout HORIZ1;
-        inout DRAIN1;
-        inout HORIZ2;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout HORIZ3;
-        inout HORIZ4;
-        inout DRAIN4;
-        inout VINJ;
-        inout GATESELECT1;
-        inout VERT2;
-        inout GATESELECT2;
-        inout GATE2;
-        inout GATE1;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X2CELLOVERLAP
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_POLY2LI
-`define SKY130_HILAS_POLY2LI
-
-/**
- * sky130_hilas_poly2li: polysilicon layer to li contact
- *
- * Verilog wrapper for sky130_hilas_poly2li.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2li (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2li (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_POLY2LI
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DUALTACORE01
-`define SKY130_HILAS_DUALTACORE01
-
-/**
- * sky130_hilas_DualTACore01: None
- *
- * Verilog wrapper for sky130_hilas_DualTACore01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DualTACore01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DualTACore01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DUALTACORE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATEVINJ01
-`define SKY130_HILAS_TGATEVINJ01
-
-/**
- * sky130_hilas_TgateVinj01: None
- *
- * Verilog wrapper for sky130_hilas_TgateVinj01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateVinj01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateVinj01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATEVINJ01
-
-
-//--------EOF---------
-
 `ifndef USER_ANALOG_PROJECT_WRAPPER
 `define USER_ANALOG_PROJECT_WRAPPER
 
@@ -3505,13 +5210,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DAC6BIT01
-`define SKY130_HILAS_DAC6BIT01
+`ifndef SKY130_HILAS_POLY2LI
+`define SKY130_HILAS_POLY2LI
 
 /**
- * sky130_hilas_DAC6bit01: None
+ * sky130_hilas_poly2li: polysilicon layer to li contact
  *
- * Verilog wrapper for sky130_hilas_DAC6bit01.
+ * Verilog wrapper for sky130_hilas_poly2li.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -3524,7 +5229,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6bit01 (
+module sky130_hilas_poly2li (
     VNB,
     VPB
 );
@@ -3538,7 +5243,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6bit01 (
+module sky130_hilas_poly2li (
     
 );
 endmodule
@@ -3548,18 +5253,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DAC6BIT01
+`endif  // SKY130_HILAS_POLY2LI
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_SWC2X2VARACTOR
-`define SKY130_HILAS_SWC2X2VARACTOR
+`ifndef SKY130_HILAS_TGATESINGLE01
+`define SKY130_HILAS_TGATESINGLE01
 
 /**
- * sky130_hilas_swc2x2varactor: ??  Is this part of the library?
+ * sky130_hilas_TgateSingle01: None
  *
- * Verilog wrapper for sky130_hilas_swc2x2varactor.
+ * Verilog wrapper for sky130_hilas_TgateSingle01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -3572,7 +5277,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_swc2x2varactor (
+module sky130_hilas_TgateSingle01 (
     VNB,
     VPB
 );
@@ -3586,7 +5291,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_swc2x2varactor (
+module sky130_hilas_TgateSingle01 (
     
 );
 endmodule
@@ -3596,18 +5301,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_SWC2X2VARACTOR
+`endif  // SKY130_HILAS_TGATESINGLE01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_LI2M2
-`define SKY130_HILAS_LI2M2
+`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP2
+`define SKY130_HILAS_SWC4X1CELLOVERLAP2
 
 /**
- * sky130_hilas_li2m2: local interconnect to m2 contact
+ * sky130_hilas_swc4x1cellOverlap2: 4x1 analog mux with overlap
  *
- * Verilog wrapper for sky130_hilas_li2m2.
+ * Verilog wrapper for sky130_hilas_swc4x1cellOverlap2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -3620,7 +5325,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_li2m2 (
+module sky130_hilas_swc4x1cellOverlap2 (
     VNB,
     VPB
 );
@@ -3634,7 +5339,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_li2m2 (
+module sky130_hilas_swc4x1cellOverlap2 (
     
 );
 endmodule
@@ -3644,7 +5349,660 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_LI2M2
+`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_RESISTOR01
+`define SKY130_HILAS_RESISTOR01
+
+/**
+ * sky130_hilas_resistor01: 
+ *
+ * Verilog wrapper for sky130_hilas_resistor01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_resistor01 (
+    TERM1,
+    TERM2,
+    VGND,
+    VNB,
+    VPB
+);
+        inout TERM1;
+        inout TERM2;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_resistor01 (
+    TERM1,
+    TERM2
+);
+        inout TERM1;
+        inout TERM2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_RESISTOR01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DOUBLETGATE01
+`define SKY130_HILAS_DOUBLETGATE01
+
+/**
+ * sky130_hilas_DoubleTGate01: 2x1 array of transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_DoubleTGate01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DoubleTGate01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DoubleTGate01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DOUBLETGATE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01A
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01A
+
+/**
+ * sky130_hilas_DAC6TransistorStack01a: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLY2M1
+`define SKY130_HILAS_POLY2M1
+
+/**
+ * sky130_hilas_poly2m1: polysilicon layer to m1 contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2m1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_POLY2M1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_STEPUPDIGITALPART1
+`define SKY130_HILAS_STEPUPDIGITALPART1
+
+/**
+ * sky130_hilas_StepUpDigitalPart1: step-up level shifter part
+ *
+ * Verilog wrapper for sky130_hilas_StepUpDigitalPart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigitalPart1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigitalPart1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_STEPUPDIGITALPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1BIASCELL
+`define SKY130_HILAS_SWC4X1BIASCELL
+
+/**
+ * sky130_hilas_swc4x1BiasCell: 4x1 array of FG switch cell configured pFET as current sources
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1BiasCell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1BiasCell (
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
+    VTUN,
+    GATE1,
+    VINJ,
+    DRAIN3,
+    DRAIN4,
+    DRAIN1,
+    DRAIN2,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1BiasCell (
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
+    VTUN,
+    GATE1,
+    VINJ,
+    DRAIN3,
+    DRAIN4,
+    DRAIN1,
+    DRAIN2
+);
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout DRAIN2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X1BIASCELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTASINGLESTAGE01
+`define SKY130_HILAS_WTASINGLESTAGE01
+
+/**
+ * sky130_hilas_WTAsinglestage01: None
+ *
+ * Verilog wrapper for sky130_hilas_WTAsinglestage01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAsinglestage01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAsinglestage01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_WTASINGLESTAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01PART2
+`define SKY130_HILAS_TGATESINGLE01PART2
+
+/**
+ * sky130_hilas_TgateSingle01Part2: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01Part2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATESINGLE01PART2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2CELL_1FG
+`define SKY130_HILAS_TA2CELL_1FG
+
+/**
+ * sky130_hilas_TA2Cell_1FG: Two transimpedance amps with one (of two) amplifiers using floating-gate
+  inputs. FG amplifier with wide linear range.
+ *
+ * Verilog wrapper for sky130_hilas_TA2Cell_1FG.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG (
+    VIN12,
+    VIN11,
+    VIN21,
+    VIN22,
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    COLSEL2,
+    GATE2,
+    GATE1,
+    COLSEL1,
+    VTUN,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VIN12;
+        inout VIN11;
+        inout VIN21;
+        inout VIN22;
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout COLSEL2;
+        inout GATE2;
+        inout GATE1;
+        inout COLSEL1;
+        inout VTUN;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG (
+    VIN12,
+    VIN11,
+    VIN21,
+    VIN22,
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    COLSEL2,
+    GATE2,
+    GATE1,
+    COLSEL1,
+    VTUN
+);
+        inout VIN12;
+        inout VIN11;
+        inout VIN21;
+        inout VIN22;
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout COLSEL2;
+        inout GATE2;
+        inout GATE1;
+        inout COLSEL1;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TA2CELL_1FG
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLYRESISTORGND
+`define SKY130_HILAS_POLYRESISTORGND
+
+/**
+ * sky130_hilas_polyresistorGND: protective current-limiting resistor to ground
+ *
+ * Verilog wrapper for sky130_hilas_polyresistorGND.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_polyresistorGND (
+    INPUT,
+    OUTPUT,
+    VGND,
+    VNB,
+    VPB
+);
+        inout INPUT;
+        inout OUTPUT;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_polyresistorGND (
+    INPUT,
+    OUTPUT
+);
+        inout INPUT;
+        inout OUTPUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_POLYRESISTORGND
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP
+`define SKY130_HILAS_SWC4X1CELLOVERLAP
+
+/**
+ * sky130_hilas_swc4x1cellOverlap: 4x1 array of FG switch cell using overlap capacitors
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1cellOverlap.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP
 
 
 //--------EOF---------
@@ -3908,13 +6266,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_CAPACITORARRAY01
-`define SKY130_HILAS_CAPACITORARRAY01
+`ifndef SKY130_HILAS_DECOUPVINJ01
+`define SKY130_HILAS_DECOUPVINJ01
 
 /**
- * sky130_hilas_capacitorArray01: selectable capacitor array
+ * sky130_hilas_DecoupVinj01: 
  *
- * Verilog wrapper for sky130_hilas_capacitorArray01.
+ * Verilog wrapper for sky130_hilas_DecoupVinj01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -3927,31 +6285,77 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_capacitorArray01 (
-    CAPTERM2,
-    CAPTERM1,
-    VINJ,
-    GATESELECT,
-    VTUN,
-    GATE,
-    DRAIN2,
-    DRAIN1,
-    DRAIN4,
-    DRAIN3,
+module sky130_hilas_DecoupVinj01 (
     VGND,
     VNB,
     VPB
 );
-        inout CAPTERM2;
-        inout CAPTERM1;
-        inout VINJ;
-        inout GATESELECT;
-        inout VTUN;
-        inout GATE;
-        inout DRAIN2;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DecoupVinj01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DECOUPVINJ01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGBIAS2X1CELL
+`define SKY130_HILAS_FGBIAS2X1CELL
+
+/**
+ * sky130_hilas_FGBias2x1cell: None
+ *
+ * Verilog wrapper for sky130_hilas_FGBias2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBias2x1cell (
+    DRAIN1,
+    DRAIN4,
+    GATECOL,
+    GATE_CONTROL,
+    OUTPUT1,
+    OUTPUT2,
+    VINJ,
+    VTUN,
+    VGND,
+    VNB,
+    VPB
+);
         inout DRAIN1;
         inout DRAIN4;
-        inout DRAIN3;
+        inout GATECOL;
+        inout GATE_CONTROL;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout VINJ;
+        inout VTUN;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -3963,1464 +6367,22 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_capacitorArray01 (
-    CAPTERM2,
-    CAPTERM1,
-    VINJ,
-    GATESELECT,
-    VTUN,
-    GATE,
-    DRAIN2,
+module sky130_hilas_FGBias2x1cell (
     DRAIN1,
     DRAIN4,
-    DRAIN3
-);
-        inout CAPTERM2;
-        inout CAPTERM1;
-        inout VINJ;
-        inout GATESELECT;
-        inout VTUN;
-        inout GATE;
-        inout DRAIN2;
-        inout DRAIN1;
-        inout DRAIN4;
-        inout DRAIN3;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPACITORARRAY01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01A
-`define SKY130_HILAS_PFETDEVICE01A
-
-/**
- * sky130_hilas_pFETdevice01a: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TA2CELL_1FG
-`define SKY130_HILAS_TA2CELL_1FG
-
-/**
- * sky130_hilas_TA2Cell_1FG: Two transimpedance amps with one (of two) amplifiers using floating-gate
-  inputs. FG amplifier with wide linear range.
- *
- * Verilog wrapper for sky130_hilas_TA2Cell_1FG.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_1FG (
-    VIN12,
-    VIN11,
-    VIN21,
-    VIN22,
-    VINJ,
+    GATECOL,
+    GATE_CONTROL,
     OUTPUT1,
     OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    COLSEL2,
-    GATE2,
-    GATE1,
-    COLSEL1,
-    VTUN,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VIN12;
-        inout VIN11;
-        inout VIN21;
-        inout VIN22;
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout COLSEL2;
-        inout GATE2;
-        inout GATE1;
-        inout COLSEL1;
-        inout VTUN;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_1FG (
-    VIN12,
-    VIN11,
-    VIN21,
-    VIN22,
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    COLSEL2,
-    GATE2,
-    GATE1,
-    COLSEL1,
-    VTUN
-);
-        inout VIN12;
-        inout VIN11;
-        inout VIN21;
-        inout VIN22;
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout COLSEL2;
-        inout GATE2;
-        inout GATE1;
-        inout COLSEL1;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TA2CELL_1FG
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TUNVARACTORCAPCITOR
-`define SKY130_HILAS_TUNVARACTORCAPCITOR
-
-/**
- * sky130_hilas_TunVaractorCapcitor: Tunneling capacitor using a standard varactor capacitor
- *
- * Verilog wrapper for sky130_hilas_TunVaractorCapcitor.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunVaractorCapcitor (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunVaractorCapcitor (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TUNVARACTORCAPCITOR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGVARACTORCAPACITOR
-`define SKY130_HILAS_FGVARACTORCAPACITOR
-
-/**
- * sky130_hilas_FGVaractorCapacitor: varactor cap for floating-gate charge storage
- *
- * Verilog wrapper for sky130_hilas_FGVaractorCapacitor.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGVARACTORCAPACITOR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TACOREBLOCK2
-`define SKY130_HILAS_TACOREBLOCK2
-
-/**
- * sky130_hilas_TACoreBlock2: None
- *
- * Verilog wrapper for sky130_hilas_TACoreBlock2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TACOREBLOCK2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_LI2M1
-`define SKY130_HILAS_LI2M1
-
-/**
- * sky130_hilas_li2m1: local interconnect to m1 contact
- *
- * Verilog wrapper for sky130_hilas_li2m1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_li2m1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_li2m1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_LI2M1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGBIASWEAKGATE2X1CELL
-`define SKY130_HILAS_FGBIASWEAKGATE2X1CELL
-
-/**
- * sky130_hilas_FGBiasWeakGate2x1cell: 2x1 array of FG switch cells configured as pFET current sources with weak capacitive gate inputs
- *
- * Verilog wrapper for sky130_hilas_FGBiasWeakGate2x1cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGBiasWeakGate2x1cell (
-    DRAIN1,
-    VIN11,
-    ROW1,
-    ROW2,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    VTUN,
-    DRAIN2,
-    VIN12,
-    COMMONSOURCE,
-    VGND,
-    VNB,
-    VPB
-);
-        inout DRAIN1;
-        inout VIN11;
-        inout ROW1;
-        inout ROW2;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout VTUN;
-        inout DRAIN2;
-        inout VIN12;
-        inout COMMONSOURCE;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGBiasWeakGate2x1cell (
-    DRAIN1,
-    VIN11,
-    ROW1,
-    ROW2,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    VTUN,
-    DRAIN2,
-    VIN12,
-    COMMONSOURCE
-);
-        inout DRAIN1;
-        inout VIN11;
-        inout ROW1;
-        inout ROW2;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout VTUN;
-        inout DRAIN2;
-        inout VIN12;
-        inout COMMONSOURCE;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGBIASWEAKGATE2X1CELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETMIRRORPAIRS
-`define SKY130_HILAS_NFETMIRRORPAIRS
-
-/**
- * sky130_hilas_nFETmirrorPairs: pairs of nFET current mirrors
- *
- * Verilog wrapper for sky130_hilas_nFETmirrorPairs.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETMIRRORPAIRS
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DOUBLETGATE01
-`define SKY130_HILAS_DOUBLETGATE01
-
-/**
- * sky130_hilas_DoubleTGate01: 2x1 array of transmission gates
- *
- * Verilog wrapper for sky130_hilas_DoubleTGate01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DoubleTGate01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DoubleTGate01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DOUBLETGATE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01BA
-`define SKY130_HILAS_PFETDEVICE01BA
-
-/**
- * sky130_hilas_pFETdevice01ba: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01ba.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01ba (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01ba (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01BA
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_INVERT01
-`define SKY130_HILAS_INVERT01
-
-/**
- * sky130_hilas_invert01: None
- *
- * Verilog wrapper for sky130_hilas_invert01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_invert01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_invert01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_INVERT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
-`define SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
-
-/**
- * sky130_hilas_FGHugeVaractorCapacitor01: one large varactor cap
- *
- * Verilog wrapper for sky130_hilas_FGHugeVaractorCapacitor01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGHugeVaractorCapacitor01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGHugeVaractorCapacitor01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP
-`define SKY130_HILAS_SWC4X1CELLOVERLAP
-
-/**
- * sky130_hilas_swc4x1cellOverlap: 4x1 array of FG switch cell using overlap capacitors
- *
- * Verilog wrapper for sky130_hilas_swc4x1cellOverlap.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1cellOverlap (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1cellOverlap (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETLARGEPART1
-`define SKY130_HILAS_PFETLARGEPART1
-
-/**
- * sky130_hilas_pFETLargePart1: Part of the W/L=100 pFET transistor
- *
- * Verilog wrapper for sky130_hilas_pFETLargePart1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETLargePart1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETLargePart1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETLARGEPART1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_M22M4
-`define SKY130_HILAS_M22M4
-
-/**
- * sky130_hilas_m22m4: m2 to m4 contact
- *
- * Verilog wrapper for sky130_hilas_m22m4.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_m22m4 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_m22m4 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_M22M4
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGVARACTORTUNNELCAP01
-`define SKY130_HILAS_FGVARACTORTUNNELCAP01
-
-/**
- * sky130_hilas_FGVaractorTunnelCap01: Tunneling cpacitor using a standard varactor capacitor
- *
- * Verilog wrapper for sky130_hilas_FGVaractorTunnelCap01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorTunnelCap01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorTunnelCap01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGVARACTORTUNNELCAP01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETLARGE
-`define SKY130_HILAS_NFETLARGE
-
-/**
- * sky130_hilas_nFETLarge: Single Large (W//L=100) nFET Transistor
- *
- * Verilog wrapper for sky130_hilas_nFETLarge.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN,
-    VGND,
-    VNB,
-    VPB
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETLARGE
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_HORIZPCELL01
-`define SKY130_HILAS_HORIZPCELL01
-
-/**
- * sky130_hilas_horizPcell01: None
- *
- * Verilog wrapper for sky130_hilas_horizPcell01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizPcell01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizPcell01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_HORIZPCELL01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETLARGE
-`define SKY130_HILAS_PFETLARGE
-
-/**
- * sky130_hilas_pFETLarge: Single Large (W/L=100) pFET Transistor
- *
- * Verilog wrapper for sky130_hilas_pFETLarge.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN,
-    WELL,
-    VNB,
-    VPB
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-        inout WELL;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN,
-    WELL
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-        inout WELL;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETLARGE
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_POLYRESISTORGND
-`define SKY130_HILAS_POLYRESISTORGND
-
-/**
- * sky130_hilas_polyresistorGND: protective current-limiting resistor to ground
- *
- * Verilog wrapper for sky130_hilas_polyresistorGND.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_polyresistorGND (
-    INPUT,
-    OUTPUT,
-    VGND,
-    VNB,
-    VPB
-);
-        inout INPUT;
-        inout OUTPUT;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_polyresistorGND (
-    INPUT,
-    OUTPUT
-);
-        inout INPUT;
-        inout OUTPUT;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_POLYRESISTORGND
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_WTASINGLESTAGE01
-`define SKY130_HILAS_WTASINGLESTAGE01
-
-/**
- * sky130_hilas_WTAsinglestage01: None
- *
- * Verilog wrapper for sky130_hilas_WTAsinglestage01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAsinglestage01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAsinglestage01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_WTASINGLESTAGE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_LEVELSHIFT4INPUTUP
-`define SKY130_HILAS_LEVELSHIFT4INPUTUP
-
-/**
- * sky130_hilas_LevelShift4InputUp: 4-channel level shifter
- *
- * Verilog wrapper for sky130_hilas_LevelShift4InputUp.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LevelShift4InputUp (
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
-    OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
-        inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LevelShift4InputUp (
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
-    OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4
-);
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
-        inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_LEVELSHIFT4INPUTUP
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETMED
-`define SKY130_HILAS_NFETMED
-
-/**
- * sky130_hilas_nFETmed: None
- *
- * Verilog wrapper for sky130_hilas_nFETmed.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmed (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmed (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETMED
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TACOREBLOCK
-`define SKY130_HILAS_TACOREBLOCK
-
-/**
- * sky130_hilas_TACoreBlock: None
- *
- * Verilog wrapper for sky130_hilas_TACoreBlock.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TACOREBLOCK
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC4X2CELL
-`define SKY130_HILAS_SWC4X2CELL
-
-/**
- * sky130_hilas_swc4x2cell: 4x2 array of FG switch cell, Varactor capacitor cell
- *
- * Verilog wrapper for sky130_hilas_swc4x2cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x2cell (
-    DRAIN1,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4,
-    GATE1,
-    GATE2,
-    GATESELECT1,
-    GATESELECT2,
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VINJ,
-    VTUN,
-    VGND,
-    VNB,
-    VPB
-);
-        inout DRAIN1;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout GATE1;
-        inout GATE2;
-        inout GATESELECT1;
-        inout GATESELECT2;
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VINJ;
-        inout VTUN;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x2cell (
-    DRAIN1,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4,
-    GATE1,
-    GATE2,
-    GATESELECT1,
-    GATESELECT2,
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
     VINJ,
     VTUN
 );
         inout DRAIN1;
-        inout DRAIN2;
-        inout DRAIN3;
         inout DRAIN4;
-        inout GATE1;
-        inout GATE2;
-        inout GATESELECT1;
-        inout GATESELECT2;
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
+        inout GATECOL;
+        inout GATE_CONTROL;
+        inout OUTPUT1;
+        inout OUTPUT2;
         inout VINJ;
         inout VTUN;
 endmodule
@@ -5430,7 +6392,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_SWC4X2CELL
+`endif  // SKY130_HILAS_FGBIAS2X1CELL
 
 
 //--------EOF---------
@@ -5560,13 +6522,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DRAINSELECT01
-`define SKY130_HILAS_DRAINSELECT01
+`ifndef SKY130_HILAS_PFETDEVICE01B
+`define SKY130_HILAS_PFETDEVICE01B
 
 /**
- * sky130_hilas_drainSelect01: multiplexor for drain selection for 4 drain lines, pitch matched
+ * sky130_hilas_pFETdevice01b: pFET transistor used in DAC block
  *
- * Verilog wrapper for sky130_hilas_drainSelect01.
+ * Verilog wrapper for sky130_hilas_pFETdevice01b.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -5579,25 +6541,532 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_drainSelect01 (
-    DRAIN3,
+module sky130_hilas_pFETdevice01b (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01b (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01B
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMIRRORPAIRS2
+`define SKY130_HILAS_NFETMIRRORPAIRS2
+
+/**
+ * sky130_hilas_nFETmirrorPairs2: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETmirrorPairs2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETMIRRORPAIRS2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NDIFFTHOXCONTACT
+`define SKY130_HILAS_NDIFFTHOXCONTACT
+
+/**
+ * sky130_hilas_nDiffThOxContact: None
+ *
+ * Verilog wrapper for sky130_hilas_nDiffThOxContact.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nDiffThOxContact (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nDiffThOxContact (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NDIFFTHOXCONTACT
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC5BIT01
+`define SKY130_HILAS_DAC5BIT01
+
+/**
+ * sky130_hilas_DAC5bit01: 5-bit digital-to-analog converter (under 6.05um at the moment; thinking through expansion to 6bit and 7bit, and they would use this cell
+ *
+ * Verilog wrapper for sky130_hilas_DAC5bit01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC5bit01 (
+    A0,
+    A1,
+    A2,
+    A3,
+    A4,
+    OUT,
+    VPWR,
+    VNB,
+    VPB
+);
+        inout A0;
+        inout A1;
+        inout A2;
+        inout A3;
+        inout A4;
+        inout OUT;
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC5bit01 (
+    A0,
+    A1,
+    A2,
+    A3,
+    A4,
+    OUT
+);
+        inout A0;
+        inout A1;
+        inout A2;
+        inout A3;
+        inout A4;
+        inout OUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC5BIT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZTRANSCELL01A
+`define SKY130_HILAS_HORIZTRANSCELL01A
+
+/**
+ * sky130_hilas_horizTransCell01a: 
+ *
+ * Verilog wrapper for sky130_hilas_horizTransCell01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_HORIZTRANSCELL01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJINV2
+`define SKY130_HILAS_VINJINV2
+
+/**
+ * sky130_hilas_VinjInv2: logical inverter for VINJ-level voltages
+ *
+ * Verilog wrapper for sky130_hilas_VinjInv2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjInv2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjInv2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_VINJINV2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUP_CAP_00
+`define SKY130_HILAS_DECOUP_CAP_00
+
+/**
+ * sky130_hilas_decoup_cap_00: decoupling cap (intended as fill)
+ *
+ * Verilog wrapper for sky130_hilas_decoup_cap_00.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_00 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_00 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DECOUP_CAP_00
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP02
+`define SKY130_HILAS_OVERLAPCAP02
+
+/**
+ * sky130_hilas_overlapCap02: overlap capacitor based capacitor)
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_OVERLAPCAP02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORCAPACITOR
+`define SKY130_HILAS_FGVARACTORCAPACITOR
+
+/**
+ * sky130_hilas_FGVaractorCapacitor: varactor cap for floating-gate charge storage
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorCapacitor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGVARACTORCAPACITOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01W1
+`define SKY130_HILAS_PFETDEVICE01W1
+
+/**
+ * sky130_hilas_pFETdevice01w1: 
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01w1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01w1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01w1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01W1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJDECODE2TO4
+`define SKY130_HILAS_VINJDECODE2TO4
+
+/**
+ * sky130_hilas_VinjDecode2to4: a 2-to-4 decoder capable of handling VINJ voltage
+ *
+ * Verilog wrapper for sky130_hilas_VinjDecode2to4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDecode2to4 (
+    OUTPUT00,
+    OUTPUT01,
+    OUTPUT10,
+    OUTPUT11,
     VINJ,
-    DRAIN_MUX,
-    SELECT2,
-    SELECT1,
-    SELECT3,
-    SELECT4,
+    IN2,
+    IN1,
+    ENABLE,
     VGND,
     VNB,
     VPB
 );
-        inout DRAIN3;
+        inout OUTPUT00;
+        inout OUTPUT01;
+        inout OUTPUT10;
+        inout OUTPUT11;
         inout VINJ;
-        inout DRAIN_MUX;
-        inout SELECT2;
-        inout SELECT1;
-        inout SELECT3;
-        inout SELECT4;
+        inout IN2;
+        inout IN1;
+        inout ENABLE;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -5609,22 +7078,24 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_drainSelect01 (
-    DRAIN3,
+module sky130_hilas_VinjDecode2to4 (
+    OUTPUT00,
+    OUTPUT01,
+    OUTPUT10,
+    OUTPUT11,
     VINJ,
-    DRAIN_MUX,
-    SELECT2,
-    SELECT1,
-    SELECT3,
-    SELECT4
+    IN2,
+    IN1,
+    ENABLE
 );
-        inout DRAIN3;
+        inout OUTPUT00;
+        inout OUTPUT01;
+        inout OUTPUT10;
+        inout OUTPUT11;
         inout VINJ;
-        inout DRAIN_MUX;
-        inout SELECT2;
-        inout SELECT1;
-        inout SELECT3;
-        inout SELECT4;
+        inout IN2;
+        inout IN1;
+        inout ENABLE;
 endmodule
 `endcelldefine
 
@@ -5632,18 +7103,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DRAINSELECT01
+`endif  // SKY130_HILAS_VINJDECODE2TO4
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_CAPMODULE01
-`define SKY130_HILAS_CAPMODULE01
+`ifndef SKY130_HILAS_PFETDEVICE01BA
+`define SKY130_HILAS_PFETDEVICE01BA
 
 /**
- * sky130_hilas_CapModule01: None
+ * sky130_hilas_pFETdevice01ba: pFET transistor used in DAC block
  *
- * Verilog wrapper for sky130_hilas_CapModule01.
+ * Verilog wrapper for sky130_hilas_pFETdevice01ba.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -5656,7 +7127,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_CapModule01 (
+module sky130_hilas_pFETdevice01ba (
     VNB,
     VPB
 );
@@ -5670,7 +7141,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_CapModule01 (
+module sky130_hilas_pFETdevice01ba (
     
 );
 endmodule
@@ -5680,250 +7151,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_LEFTPROTECTION
-`define SKY130_HILAS_LEFTPROTECTION
-
-/**
- * sky130_hilas_LeftProtection: 
- *
- * Verilog wrapper for sky130_hilas_LeftProtection.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LeftProtection (
-    IO25,
-    IO26,
-    IO27,
-    IO28,
-    IO29,
-    IO30,
-    IO31,
-    IO32,
-    IO33,
-    IO34,
-    IO35,
-    IO36,
-    IO37,
-    PIN1,
-    PIN2,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    PIN11,
-    PIN12,
-    PIN13,
-    VNB,
-    VPB
-);
-        inout IO25;
-        inout IO26;
-        inout IO27;
-        inout IO28;
-        inout IO29;
-        inout IO30;
-        inout IO31;
-        inout IO32;
-        inout IO33;
-        inout IO34;
-        inout IO35;
-        inout IO36;
-        inout IO37;
-        inout PIN1;
-        inout PIN2;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout PIN11;
-        inout PIN12;
-        inout PIN13;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LeftProtection (
-    IO25,
-    IO26,
-    IO27,
-    IO28,
-    IO29,
-    IO30,
-    IO31,
-    IO32,
-    IO33,
-    IO34,
-    IO35,
-    IO36,
-    IO37,
-    PIN1,
-    PIN2,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    PIN11,
-    PIN12,
-    PIN13
-);
-        inout IO25;
-        inout IO26;
-        inout IO27;
-        inout IO28;
-        inout IO29;
-        inout IO30;
-        inout IO31;
-        inout IO32;
-        inout IO33;
-        inout IO34;
-        inout IO35;
-        inout IO36;
-        inout IO37;
-        inout PIN1;
-        inout PIN2;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout PIN11;
-        inout PIN12;
-        inout PIN13;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_LEFTPROTECTION
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGVARACTORCAPACITOR02
-`define SKY130_HILAS_FGVARACTORCAPACITOR02
-
-/**
- * sky130_hilas_FGVaractorCapacitor02: variant 2, varactor cap for floating-gate charge storage
- *
- * Verilog wrapper for sky130_hilas_FGVaractorCapacitor02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGVARACTORCAPACITOR02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATESINGLE01PART1
-`define SKY130_HILAS_TGATESINGLE01PART1
-
-/**
- * sky130_hilas_TgateSingle01Part1: None
- *
- * Verilog wrapper for sky130_hilas_TgateSingle01Part1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateSingle01Part1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateSingle01Part1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATESINGLE01PART1
+`endif  // SKY130_HILAS_PFETDEVICE01BA
 
 
 //--------EOF---------
@@ -6031,13 +7259,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_VINJINV2
-`define SKY130_HILAS_VINJINV2
+`ifndef SKY130_HILAS_PFETLARGE
+`define SKY130_HILAS_PFETLARGE
 
 /**
- * sky130_hilas_VinjInv2: logical inverter for VINJ-level voltages
+ * sky130_hilas_pFETLarge: Single Large (W/L=100) pFET Transistor
  *
- * Verilog wrapper for sky130_hilas_VinjInv2.
+ * Verilog wrapper for sky130_hilas_pFETLarge.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -6050,7 +7278,70 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjInv2 (
+module sky130_hilas_pFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN,
+    WELL,
+    VNB,
+    VPB
+);
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+        inout WELL;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN,
+    WELL
+);
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+        inout WELL;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETLARGE
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFET03A
+`define SKY130_HILAS_NFET03A
+
+/**
+ * sky130_hilas_nFET03a: None
+ *
+ * Verilog wrapper for sky130_hilas_nFET03a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03a (
     VNB,
     VPB
 );
@@ -6064,7 +7355,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjInv2 (
+module sky130_hilas_nFET03a (
     
 );
 endmodule
@@ -6074,18 +7365,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_VINJINV2
+`endif  // SKY130_HILAS_NFET03A
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_CAPMODULE02
-`define SKY130_HILAS_CAPMODULE02
+`ifndef SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+`define SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
 
 /**
- * sky130_hilas_CapModule02: None
+ * sky130_hilas_FGHugeVaractorCapacitor01: one large varactor cap
  *
- * Verilog wrapper for sky130_hilas_CapModule02.
+ * Verilog wrapper for sky130_hilas_FGHugeVaractorCapacitor01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -6098,7 +7389,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_CapModule02 (
+module sky130_hilas_FGHugeVaractorCapacitor01 (
     VNB,
     VPB
 );
@@ -6112,7 +7403,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_CapModule02 (
+module sky130_hilas_FGHugeVaractorCapacitor01 (
     
 );
 endmodule
@@ -6122,18 +7413,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE02
+`endif  // SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01C
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01C
+`ifndef SKY130_HILAS_TGATEVINJ01
+`define SKY130_HILAS_TGATEVINJ01
 
 /**
- * sky130_hilas_DAC6TransistorStack01c: None
+ * sky130_hilas_TgateVinj01: None
  *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01c.
+ * Verilog wrapper for sky130_hilas_TgateVinj01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -6146,7 +7437,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6TransistorStack01c (
+module sky130_hilas_TgateVinj01 (
     VNB,
     VPB
 );
@@ -6160,7 +7451,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6TransistorStack01c (
+module sky130_hilas_TgateVinj01 (
     
 );
 endmodule
@@ -6170,839 +7461,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01C
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGCHARACTERIZATION01
-`define SKY130_HILAS_FGCHARACTERIZATION01
-
-/**
- * sky130_hilas_FGcharacterization01: FG test strucure that uses a capacitor around a transconductance amplifier
- *
- * Verilog wrapper for sky130_hilas_FGcharacterization01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGcharacterization01 (
-    VTUN,
-    GATE1,
-    GATE3,
-    VTUNOVERLAP01,
-    GATE2,
-    GATE4,
-    LARGECAPACITOR,
-    VINJ,
-    OUTPUT,
-    VREF,
-    VBIAS,
-    DRAIN1,
-    SOURCE1,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VTUN;
-        inout GATE1;
-        inout GATE3;
-        inout VTUNOVERLAP01;
-        inout GATE2;
-        inout GATE4;
-        inout LARGECAPACITOR;
-        inout VINJ;
-        inout OUTPUT;
-        inout VREF;
-        inout VBIAS;
-        inout DRAIN1;
-        inout SOURCE1;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGcharacterization01 (
-    VTUN,
-    GATE1,
-    GATE3,
-    VTUNOVERLAP01,
-    GATE2,
-    GATE4,
-    LARGECAPACITOR,
-    VINJ,
-    OUTPUT,
-    VREF,
-    VBIAS,
-    DRAIN1,
-    SOURCE1
-);
-        inout VTUN;
-        inout GATE1;
-        inout GATE3;
-        inout VTUNOVERLAP01;
-        inout GATE2;
-        inout GATE4;
-        inout LARGECAPACITOR;
-        inout VINJ;
-        inout OUTPUT;
-        inout VREF;
-        inout VBIAS;
-        inout DRAIN1;
-        inout SOURCE1;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGCHARACTERIZATION01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_OVERLAPCAP01
-`define SKY130_HILAS_OVERLAPCAP01
-
-/**
- * sky130_hilas_overlapCap01: overlap capacitor based capacitor
- *
- * Verilog wrapper for sky130_hilas_overlapCap01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_OVERLAPCAP01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PTRANSISTORPAIR
-`define SKY130_HILAS_PTRANSISTORPAIR
-
-/**
- * sky130_hilas_pTransistorPair: None
- *
- * Verilog wrapper for sky130_hilas_pTransistorPair.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorPair (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorPair (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PTRANSISTORPAIR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CELLATTEMPT01
-`define SKY130_HILAS_CELLATTEMPT01
-
-/**
- * sky130_hilas_cellAttempt01: 4x1 array of FG switch cell, Varactor capacitor cell
- *
- * Verilog wrapper for sky130_hilas_cellAttempt01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_cellAttempt01 (
-    VTUN,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    ROW4,
-    DRAIN4,
-    DRAIN1,
-    ROW1,
-    ROW3,
-    DRAIN3,
-    DRAIN2,
-    ROW2,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VTUN;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout ROW4;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout ROW1;
-        inout ROW3;
-        inout DRAIN3;
-        inout DRAIN2;
-        inout ROW2;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_cellAttempt01 (
-    VTUN,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    ROW4,
-    DRAIN4,
-    DRAIN1,
-    ROW1,
-    ROW3,
-    DRAIN3,
-    DRAIN2,
-    ROW2
-);
-        inout VTUN;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout ROW4;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout ROW1;
-        inout ROW3;
-        inout DRAIN3;
-        inout DRAIN2;
-        inout ROW2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CELLATTEMPT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_POLY2M1
-`define SKY130_HILAS_POLY2M1
-
-/**
- * sky130_hilas_poly2m1: polysilicon layer to m1 contact
- *
- * Verilog wrapper for sky130_hilas_poly2m1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2m1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2m1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_POLY2M1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01W1
-`define SKY130_HILAS_PFETDEVICE01W1
-
-/**
- * sky130_hilas_pFETdevice01w1: 
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01w1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01w1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01w1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01W1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DAC5BIT01
-`define SKY130_HILAS_DAC5BIT01
-
-/**
- * sky130_hilas_DAC5bit01: 5-bit digital-to-analog converter (under 6.05um at the moment; thinking through expansion to 6bit and 7bit, and they would use this cell
- *
- * Verilog wrapper for sky130_hilas_DAC5bit01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC5bit01 (
-    A0,
-    A1,
-    A2,
-    A3,
-    A4,
-    OUT,
-    VPWR,
-    VNB,
-    VPB
-);
-        inout A0;
-        inout A1;
-        inout A2;
-        inout A3;
-        inout A4;
-        inout OUT;
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC5bit01 (
-    A0,
-    A1,
-    A2,
-    A3,
-    A4,
-    OUT
-);
-        inout A0;
-        inout A1;
-        inout A2;
-        inout A3;
-        inout A4;
-        inout OUT;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC5BIT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_VINJNOR3
-`define SKY130_HILAS_VINJNOR3
-
-/**
- * sky130_hilas_VinjNOR3: 3-input NOR gate capable of VING voltage
- *
- * Verilog wrapper for sky130_hilas_VinjNOR3.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjNOR3 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjNOR3 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_VINJNOR3
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_VINJDECODE2TO4
-`define SKY130_HILAS_VINJDECODE2TO4
-
-/**
- * sky130_hilas_VinjDecode2to4: a 2-to-4 decoder capable of handling VINJ voltage
- *
- * Verilog wrapper for sky130_hilas_VinjDecode2to4.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjDecode2to4 (
-    OUTPUT00,
-    OUTPUT01,
-    OUTPUT10,
-    OUTPUT11,
-    VINJ,
-    IN2,
-    IN1,
-    ENABLE,
-    VGND,
-    VNB,
-    VPB
-);
-        inout OUTPUT00;
-        inout OUTPUT01;
-        inout OUTPUT10;
-        inout OUTPUT11;
-        inout VINJ;
-        inout IN2;
-        inout IN1;
-        inout ENABLE;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjDecode2to4 (
-    OUTPUT00,
-    OUTPUT01,
-    OUTPUT10,
-    OUTPUT11,
-    VINJ,
-    IN2,
-    IN1,
-    ENABLE
-);
-        inout OUTPUT00;
-        inout OUTPUT01;
-        inout OUTPUT10;
-        inout OUTPUT11;
-        inout VINJ;
-        inout IN2;
-        inout IN1;
-        inout ENABLE;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_VINJDECODE2TO4
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01AA
-`define SKY130_HILAS_PFETDEVICE01AA
-
-/**
- * sky130_hilas_pFETdevice01aa: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01aa.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01aa (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01aa (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01AA
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NDIFFTHOXCONTACT
-`define SKY130_HILAS_NDIFFTHOXCONTACT
-
-/**
- * sky130_hilas_nDiffThOxContact: None
- *
- * Verilog wrapper for sky130_hilas_nDiffThOxContact.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nDiffThOxContact (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nDiffThOxContact (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NDIFFTHOXCONTACT
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_WELLCONTACT
-`define SKY130_HILAS_WELLCONTACT
-
-/**
- * sky130_hilas_wellContact: contact to a well block, typically used for contacting tunneling junctions in a well.
- *
- * Verilog wrapper for sky130_hilas_wellContact.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_wellContact (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_wellContact (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_WELLCONTACT
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_OVERLAPCAP02
-`define SKY130_HILAS_OVERLAPCAP02
-
-/**
- * sky130_hilas_overlapCap02: overlap capacitor based capacitor)
- *
- * Verilog wrapper for sky130_hilas_overlapCap02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_OVERLAPCAP02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01C
-`define SKY130_HILAS_PFETDEVICE01C
-
-/**
- * sky130_hilas_pFETdevice01c: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01c.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01c (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01c (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01C
+`endif  // SKY130_HILAS_TGATEVINJ01
 
 
 //--------EOF---------
@@ -7070,1268 +7529,6 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP2
-`define SKY130_HILAS_SWC4X1CELLOVERLAP2
-
-/**
- * sky130_hilas_swc4x1cellOverlap2: 4x1 analog mux with overlap
- *
- * Verilog wrapper for sky130_hilas_swc4x1cellOverlap2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1cellOverlap2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1cellOverlap2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_HORIZTRANSCELL01A
-`define SKY130_HILAS_HORIZTRANSCELL01A
-
-/**
- * sky130_hilas_horizTransCell01a: 
- *
- * Verilog wrapper for sky130_hilas_horizTransCell01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_HORIZTRANSCELL01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TA2CELL_NOFG
-`define SKY130_HILAS_TA2CELL_NOFG
-
-/**
- * sky130_hilas_TA2Cell_NoFG: Two transimpedane amplifiers with no floating-gate inputs.
- *
- * Verilog wrapper for sky130_hilas_TA2Cell_NoFG.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_NoFG (
-    COLSEL1,
-    VIN12,
-    VIN21,
-    VIN22,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    VTUN,
-    GATE1,
-    VINJ,
-    VIN11,
-    VGND,
-    VPWR,
-    VNB,
-    VPB
-);
-        inout COLSEL1;
-        inout VIN12;
-        inout VIN21;
-        inout VIN22;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout VIN11;
-        inout VGND;
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_NoFG (
-    COLSEL1,
-    VIN12,
-    VIN21,
-    VIN22,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    VTUN,
-    GATE1,
-    VINJ,
-    VIN11
-);
-        inout COLSEL1;
-        inout VIN12;
-        inout VIN21;
-        inout VIN22;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout VIN11;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TA2CELL_NOFG
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGBIAS2X1CELL
-`define SKY130_HILAS_FGBIAS2X1CELL
-
-/**
- * sky130_hilas_FGBias2x1cell: None
- *
- * Verilog wrapper for sky130_hilas_FGBias2x1cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGBias2x1cell (
-    DRAIN1,
-    DRAIN4,
-    GATECOL,
-    GATE_CONTROL,
-    OUTPUT1,
-    OUTPUT2,
-    VINJ,
-    VTUN,
-    VGND,
-    VNB,
-    VPB
-);
-        inout DRAIN1;
-        inout DRAIN4;
-        inout GATECOL;
-        inout GATE_CONTROL;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout VINJ;
-        inout VTUN;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGBias2x1cell (
-    DRAIN1,
-    DRAIN4,
-    GATECOL,
-    GATE_CONTROL,
-    OUTPUT1,
-    OUTPUT2,
-    VINJ,
-    VTUN
-);
-        inout DRAIN1;
-        inout DRAIN4;
-        inout GATECOL;
-        inout GATE_CONTROL;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout VINJ;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGBIAS2X1CELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPMODULE03
-`define SKY130_HILAS_CAPMODULE03
-
-/**
- * sky130_hilas_CapModule03: None
- *
- * Verilog wrapper for sky130_hilas_CapModule03.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule03 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule03 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE03
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETMIRROR02
-`define SKY130_HILAS_PFETMIRROR02
-
-/**
- * sky130_hilas_pFETmirror02: second pFET current mirror
- *
- * Verilog wrapper for sky130_hilas_pFETmirror02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmirror02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmirror02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETMIRROR02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETMIRRORPAIRS2
-`define SKY130_HILAS_NFETMIRRORPAIRS2
-
-/**
- * sky130_hilas_nFETmirrorPairs2: None
- *
- * Verilog wrapper for sky130_hilas_nFETmirrorPairs2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETMIRRORPAIRS2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TOPPROTECTION
-`define SKY130_HILAS_TOPPROTECTION
-
-/**
- * sky130_hilas_TopProtection: 
- *
- * Verilog wrapper for sky130_hilas_TopProtection.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TopProtection (
-    ANALOG00,
-    ANALOG01,
-    ANALOG02,
-    ANALOG03,
-    ANALOG04,
-    ANALOG05,
-    ANALOG06,
-    ANALOG07,
-    ANALOG08,
-    ANALOG09,
-    ANALOG10,
-    PIN1,
-    PIN2,
-    PIN3,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    VTUN,
-    VNB,
-    VPB
-);
-        inout ANALOG00;
-        inout ANALOG01;
-        inout ANALOG02;
-        inout ANALOG03;
-        inout ANALOG04;
-        inout ANALOG05;
-        inout ANALOG06;
-        inout ANALOG07;
-        inout ANALOG08;
-        inout ANALOG09;
-        inout ANALOG10;
-        inout PIN1;
-        inout PIN2;
-        inout PIN3;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout VTUN;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TopProtection (
-    ANALOG00,
-    ANALOG01,
-    ANALOG02,
-    ANALOG03,
-    ANALOG04,
-    ANALOG05,
-    ANALOG06,
-    ANALOG07,
-    ANALOG08,
-    ANALOG09,
-    ANALOG10,
-    PIN1,
-    PIN2,
-    PIN3,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    VTUN
-);
-        inout ANALOG00;
-        inout ANALOG01;
-        inout ANALOG02;
-        inout ANALOG03;
-        inout ANALOG04;
-        inout ANALOG05;
-        inout ANALOG06;
-        inout ANALOG07;
-        inout ANALOG08;
-        inout ANALOG09;
-        inout ANALOG10;
-        inout PIN1;
-        inout PIN2;
-        inout PIN3;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TOPPROTECTION
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATE4SINGLE01
-`define SKY130_HILAS_TGATE4SINGLE01
-
-/**
- * sky130_hilas_Tgate4Single01: 4 single-throw transmission gates
- *
- * Verilog wrapper for sky130_hilas_Tgate4Single01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_Tgate4Single01 (
-    INPUT1_2,
-    SELECT2,
-    OUTPUT2,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT1,
-    INPUT1_4,
-    SELECT4,
-    SELECT3,
-    INPUT1_3,
-    SELECT1,
-    INPUT1_1,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout INPUT1_2;
-        inout SELECT2;
-        inout OUTPUT2;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT1;
-        inout INPUT1_4;
-        inout SELECT4;
-        inout SELECT3;
-        inout INPUT1_3;
-        inout SELECT1;
-        inout INPUT1_1;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_Tgate4Single01 (
-    INPUT1_2,
-    SELECT2,
-    OUTPUT2,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT1,
-    INPUT1_4,
-    SELECT4,
-    SELECT3,
-    INPUT1_3,
-    SELECT1,
-    INPUT1_1
-);
-        inout INPUT1_2;
-        inout SELECT2;
-        inout OUTPUT2;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT1;
-        inout INPUT1_4;
-        inout SELECT4;
-        inout SELECT3;
-        inout INPUT1_3;
-        inout SELECT1;
-        inout INPUT1_1;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATE4SINGLE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_OVERLAPCAP02A
-`define SKY130_HILAS_OVERLAPCAP02A
-
-/**
- * sky130_hilas_overlapCap02a: overlap capacitor based capacitor
- *
- * Verilog wrapper for sky130_hilas_overlapCap02a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_OVERLAPCAP02A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC4X1BIASCELL
-`define SKY130_HILAS_SWC4X1BIASCELL
-
-/**
- * sky130_hilas_swc4x1BiasCell: 4x1 array of FG switch cell configured pFET as current sources
- *
- * Verilog wrapper for sky130_hilas_swc4x1BiasCell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1BiasCell (
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VTUN,
-    GATE1,
-    VINJ,
-    DRAIN3,
-    DRAIN4,
-    DRAIN1,
-    DRAIN2,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1BiasCell (
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VTUN,
-    GATE1,
-    VINJ,
-    DRAIN3,
-    DRAIN4,
-    DRAIN1,
-    DRAIN2
-);
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout DRAIN2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X1BIASCELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPACITORSIZE03
-`define SKY130_HILAS_CAPACITORSIZE03
-
-/**
- * sky130_hilas_capacitorSize03: mid-large cap
- *
- * Verilog wrapper for sky130_hilas_capacitorSize03.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorSize03 (
-    CAPTERM02,
-    CAPTERM01,
-    VNB,
-    VPB
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorSize03 (
-    CAPTERM02,
-    CAPTERM01
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPACITORSIZE03
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGTRANS2X1CELL
-`define SKY130_HILAS_FGTRANS2X1CELL
-
-/**
- * sky130_hilas_FGtrans2x1cell: None
- *
- * Verilog wrapper for sky130_hilas_FGtrans2x1cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGtrans2x1cell (
-    COLSEL1,
-    VINJ,
-    DRAIN1,
-    DRAIN2,
-    PROG,
-    RUN,
-    VIN2,
-    VIN1,
-    GATE1,
-    VTUN,
-    COL1,
-    ROW1,
-    ROW2,
-    VGND,
-    VNB,
-    VPB
-);
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout PROG;
-        inout RUN;
-        inout VIN2;
-        inout VIN1;
-        inout GATE1;
-        inout VTUN;
-        inout COL1;
-        inout ROW1;
-        inout ROW2;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGtrans2x1cell (
-    COLSEL1,
-    VINJ,
-    DRAIN1,
-    DRAIN2,
-    PROG,
-    RUN,
-    VIN2,
-    VIN1,
-    GATE1,
-    VTUN,
-    COL1,
-    ROW1,
-    ROW2
-);
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout PROG;
-        inout RUN;
-        inout VIN2;
-        inout VIN1;
-        inout GATE1;
-        inout VTUN;
-        inout COL1;
-        inout ROW1;
-        inout ROW2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGTRANS2X1CELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_POLY2M2
-`define SKY130_HILAS_POLY2M2
-
-/**
- * sky130_hilas_poly2m2: polysilicon layer to m2 contact
- *
- * Verilog wrapper for sky130_hilas_poly2m2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2m2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2m2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_POLY2M2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPMODULE01A
-`define SKY130_HILAS_CAPMODULE01A
-
-/**
- * sky130_hilas_CapModule01a: primitive cap, variant 01a
- *
- * Verilog wrapper for sky130_hilas_CapModule01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01D
-`define SKY130_HILAS_PFETDEVICE01D
-
-/**
- * sky130_hilas_pFETdevice01d: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01d.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01d (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01d (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01D
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_WTA4STAGE01
-`define SKY130_HILAS_WTA4STAGE01
-
-/**
- * sky130_hilas_WTA4Stage01: 4-input winner-take-all circuit. Connects directly to array of swc4x2cell. Can array vertically. Needs one nFET transistor current source.
- *
- * Verilog wrapper for sky130_hilas_WTA4Stage01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTA4Stage01 (
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
-    OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4,
-    DRAIN1,
-    GATE1,
-    VTUN,
-    WTAMIDDLENODE,
-    COLSEL1,
-    VINJ,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4,
-    VGND,
-    VNB,
-    VPB
-);
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
-        inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-        inout DRAIN1;
-        inout GATE1;
-        inout VTUN;
-        inout WTAMIDDLENODE;
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTA4Stage01 (
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
-    OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4,
-    DRAIN1,
-    GATE1,
-    VTUN,
-    WTAMIDDLENODE,
-    COLSEL1,
-    VINJ,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4
-);
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
-        inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-        inout DRAIN1;
-        inout GATE1;
-        inout VTUN;
-        inout WTAMIDDLENODE;
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_WTA4STAGE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_WTABLOCKSAMPLE01
-`define SKY130_HILAS_WTABLOCKSAMPLE01
-
-/**
- * sky130_hilas_WTAblockSample01: None
- *
- * Verilog wrapper for sky130_hilas_WTAblockSample01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAblockSample01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAblockSample01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_WTABLOCKSAMPLE01
-
-
-//--------EOF---------
-
 `ifndef SKY130_HILAS_TOPPROTECTSTRUCTURE
 `define SKY130_HILAS_TOPPROTECTSTRUCTURE
 
@@ -8631,6 +7828,1206 @@
 
 //--------EOF---------
 
+`ifndef SKY130_HILAS_M12M2
+`define SKY130_HILAS_M12M2
+
+/**
+ * sky130_hilas_m12m2: m1 to m2 contact
+ *
+ * Verilog wrapper for sky130_hilas_m12m2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m12m2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m12m2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_M12M2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01AA
+`define SKY130_HILAS_PFETDEVICE01AA
+
+/**
+ * sky130_hilas_pFETdevice01aa: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01aa.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01aa (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01aa (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01AA
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORTUNNELCAP01
+`define SKY130_HILAS_FGVARACTORTUNNELCAP01
+
+/**
+ * sky130_hilas_FGVaractorTunnelCap01: Tunneling cpacitor using a standard varactor capacitor
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorTunnelCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorTunnelCap01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorTunnelCap01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGVARACTORTUNNELCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TUNCAP01
+`define SKY130_HILAS_TUNCAP01
+
+/**
+ * sky130_hilas_TunCap01: None
+ *
+ * Verilog wrapper for sky130_hilas_TunCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunCap01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunCap01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TUNCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMED
+`define SKY130_HILAS_PFETMED
+
+/**
+ * sky130_hilas_pFETmed: Medium-sized (W/L=10) pFET transistor
+ *
+ * Verilog wrapper for sky130_hilas_pFETmed.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmed (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmed (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETMED
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE03
+`define SKY130_HILAS_CAPACITORSIZE03
+
+/**
+ * sky130_hilas_capacitorSize03: mid-large cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize03 (
+    CAPTERM02,
+    CAPTERM01,
+    VNB,
+    VPB
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize03 (
+    CAPTERM02,
+    CAPTERM01
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPACITORSIZE03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE02
+`define SKY130_HILAS_CAPMODULE02
+
+/**
+ * sky130_hilas_CapModule02: None
+ *
+ * Verilog wrapper for sky130_hilas_CapModule02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPMODULE02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01PART1
+`define SKY130_HILAS_TGATESINGLE01PART1
+
+/**
+ * sky130_hilas_TgateSingle01Part1: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01Part1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATESINGLE01PART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TUNVARACTORCAPCITOR
+`define SKY130_HILAS_TUNVARACTORCAPCITOR
+
+/**
+ * sky130_hilas_TunVaractorCapcitor: Tunneling capacitor using a standard varactor capacitor
+ *
+ * Verilog wrapper for sky130_hilas_TunVaractorCapcitor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunVaractorCapcitor (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunVaractorCapcitor (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TUNVARACTORCAPCITOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+`define SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+
+/**
+ * sky130_hilas_FGBiasWeakGate2x1cell: 2x1 array of FG switch cells configured as pFET current sources with weak capacitive gate inputs
+ *
+ * Verilog wrapper for sky130_hilas_FGBiasWeakGate2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBiasWeakGate2x1cell (
+    DRAIN1,
+    VIN11,
+    ROW1,
+    ROW2,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    VTUN,
+    DRAIN2,
+    VIN12,
+    COMMONSOURCE,
+    VGND,
+    VNB,
+    VPB
+);
+        inout DRAIN1;
+        inout VIN11;
+        inout ROW1;
+        inout ROW2;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout VTUN;
+        inout DRAIN2;
+        inout VIN12;
+        inout COMMONSOURCE;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBiasWeakGate2x1cell (
+    DRAIN1,
+    VIN11,
+    ROW1,
+    ROW2,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    VTUN,
+    DRAIN2,
+    VIN12,
+    COMMONSOURCE
+);
+        inout DRAIN1;
+        inout VIN11;
+        inout ROW1;
+        inout ROW2;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout VTUN;
+        inout DRAIN2;
+        inout VIN12;
+        inout COMMONSOURCE;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LI2M1
+`define SKY130_HILAS_LI2M1
+
+/**
+ * sky130_hilas_li2m1: local interconnect to m1 contact
+ *
+ * Verilog wrapper for sky130_hilas_li2m1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_LI2M1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DUALTACORE01
+`define SKY130_HILAS_DUALTACORE01
+
+/**
+ * sky130_hilas_DualTACore01: None
+ *
+ * Verilog wrapper for sky130_hilas_DualTACore01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DualTACore01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DualTACore01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DUALTACORE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_STEPUPDIGITAL
+`define SKY130_HILAS_STEPUPDIGITAL
+
+/**
+ * sky130_hilas_StepUpDigital: a single level shifter
+ *
+ * Verilog wrapper for sky130_hilas_StepUpDigital.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigital (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigital (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_STEPUPDIGITAL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PTRANSISTORVERT01
+`define SKY130_HILAS_PTRANSISTORVERT01
+
+/**
+ * sky130_hilas_pTransistorVert01: None
+ *
+ * Verilog wrapper for sky130_hilas_pTransistorVert01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorVert01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorVert01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PTRANSISTORVERT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE01A
+`define SKY130_HILAS_CAPMODULE01A
+
+/**
+ * sky130_hilas_CapModule01a: primitive cap, variant 01a
+ *
+ * Verilog wrapper for sky130_hilas_CapModule01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPMODULE01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01C
+`define SKY130_HILAS_PFETDEVICE01C
+
+/**
+ * sky130_hilas_pFETdevice01c: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01c.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01c (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01c (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01C
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORARRAY01
+`define SKY130_HILAS_CAPACITORARRAY01
+
+/**
+ * sky130_hilas_capacitorArray01: selectable capacitor array
+ *
+ * Verilog wrapper for sky130_hilas_capacitorArray01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorArray01 (
+    CAPTERM2,
+    CAPTERM1,
+    VINJ,
+    GATESELECT,
+    VTUN,
+    GATE,
+    DRAIN2,
+    DRAIN1,
+    DRAIN4,
+    DRAIN3,
+    VGND,
+    VNB,
+    VPB
+);
+        inout CAPTERM2;
+        inout CAPTERM1;
+        inout VINJ;
+        inout GATESELECT;
+        inout VTUN;
+        inout GATE;
+        inout DRAIN2;
+        inout DRAIN1;
+        inout DRAIN4;
+        inout DRAIN3;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorArray01 (
+    CAPTERM2,
+    CAPTERM1,
+    VINJ,
+    GATESELECT,
+    VTUN,
+    GATE,
+    DRAIN2,
+    DRAIN1,
+    DRAIN4,
+    DRAIN3
+);
+        inout CAPTERM2;
+        inout CAPTERM1;
+        inout VINJ;
+        inout GATESELECT;
+        inout VTUN;
+        inout GATE;
+        inout DRAIN2;
+        inout DRAIN1;
+        inout DRAIN4;
+        inout DRAIN3;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPACITORARRAY01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01E
+`define SKY130_HILAS_PFETDEVICE01E
+
+/**
+ * sky130_hilas_pFETdevice01e: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01e.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01e (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01e (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01E
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZTRANSCELL01
+`define SKY130_HILAS_HORIZTRANSCELL01
+
+/**
+ * sky130_hilas_horizTransCell01: None
+ *
+ * Verilog wrapper for sky130_hilas_horizTransCell01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_HORIZTRANSCELL01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LEFTPROTECTION
+`define SKY130_HILAS_LEFTPROTECTION
+
+/**
+ * sky130_hilas_LeftProtection: 
+ *
+ * Verilog wrapper for sky130_hilas_LeftProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LeftProtection (
+    IO25,
+    IO26,
+    IO27,
+    IO28,
+    IO29,
+    IO30,
+    IO31,
+    IO32,
+    IO33,
+    IO34,
+    IO35,
+    IO36,
+    IO37,
+    PIN1,
+    PIN2,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    PIN11,
+    PIN12,
+    PIN13,
+    VNB,
+    VPB
+);
+        inout IO25;
+        inout IO26;
+        inout IO27;
+        inout IO28;
+        inout IO29;
+        inout IO30;
+        inout IO31;
+        inout IO32;
+        inout IO33;
+        inout IO34;
+        inout IO35;
+        inout IO36;
+        inout IO37;
+        inout PIN1;
+        inout PIN2;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout PIN11;
+        inout PIN12;
+        inout PIN13;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LeftProtection (
+    IO25,
+    IO26,
+    IO27,
+    IO28,
+    IO29,
+    IO30,
+    IO31,
+    IO32,
+    IO33,
+    IO34,
+    IO35,
+    IO36,
+    IO37,
+    PIN1,
+    PIN2,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    PIN11,
+    PIN12,
+    PIN13
+);
+        inout IO25;
+        inout IO26;
+        inout IO27;
+        inout IO28;
+        inout IO29;
+        inout IO30;
+        inout IO31;
+        inout IO32;
+        inout IO33;
+        inout IO34;
+        inout IO35;
+        inout IO36;
+        inout IO37;
+        inout PIN1;
+        inout PIN2;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout PIN11;
+        inout PIN12;
+        inout PIN13;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_LEFTPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01B
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01B
+
+/**
+ * sky130_hilas_DAC6TransistorStack01b: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01b.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01b (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01b (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01B
+
+
+//--------EOF---------
+
 `ifndef SKY130_HILAS_TRANS2MED
 `define SKY130_HILAS_TRANS2MED
 
@@ -8732,13 +9129,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETDEVICE01
-`define SKY130_HILAS_PFETDEVICE01
+`ifndef SKY130_HILAS_LI2M2
+`define SKY130_HILAS_LI2M2
 
 /**
- * sky130_hilas_pFETdevice01: pFET transistor used in DAC block
+ * sky130_hilas_li2m2: local interconnect to m2 contact
  *
- * Verilog wrapper for sky130_hilas_pFETdevice01.
+ * Verilog wrapper for sky130_hilas_li2m2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -8751,7 +9148,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETdevice01 (
+module sky130_hilas_li2m2 (
     VNB,
     VPB
 );
@@ -8765,7 +9162,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETdevice01 (
+module sky130_hilas_li2m2 (
     
 );
 endmodule
@@ -8775,18 +9172,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01
+`endif  // SKY130_HILAS_LI2M2
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DECOUPVINJ00
-`define SKY130_HILAS_DECOUPVINJ00
+`ifndef SKY130_HILAS_CELLATTEMPT01
+`define SKY130_HILAS_CELLATTEMPT01
 
 /**
- * sky130_hilas_DecoupVinj00: 
+ * sky130_hilas_cellAttempt01: 4x1 array of FG switch cell, Varactor capacitor cell
  *
- * Verilog wrapper for sky130_hilas_DecoupVinj00.
+ * Verilog wrapper for sky130_hilas_cellAttempt01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -8799,10 +9196,36 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DecoupVinj00 (
+module sky130_hilas_cellAttempt01 (
+    VTUN,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    ROW4,
+    DRAIN4,
+    DRAIN1,
+    ROW1,
+    ROW3,
+    DRAIN3,
+    DRAIN2,
+    ROW2,
+    VGND,
     VNB,
     VPB
 );
+        inout VTUN;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout ROW4;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout ROW1;
+        inout ROW3;
+        inout DRAIN3;
+        inout DRAIN2;
+        inout ROW2;
+        inout VGND;
         inout VNB;
         inout VPB;
 endmodule
@@ -8813,9 +9236,32 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DecoupVinj00 (
-    
+module sky130_hilas_cellAttempt01 (
+    VTUN,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    ROW4,
+    DRAIN4,
+    DRAIN1,
+    ROW1,
+    ROW3,
+    DRAIN3,
+    DRAIN2,
+    ROW2
 );
+        inout VTUN;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout ROW4;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout ROW1;
+        inout ROW3;
+        inout DRAIN3;
+        inout DRAIN2;
+        inout ROW2;
 endmodule
 `endcelldefine
 
@@ -8823,18 +9269,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DECOUPVINJ00
+`endif  // SKY130_HILAS_CELLATTEMPT01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETMIRROR
-`define SKY130_HILAS_PFETMIRROR
+`ifndef SKY130_HILAS_OVERLAPCAP02A
+`define SKY130_HILAS_OVERLAPCAP02A
 
 /**
- * sky130_hilas_pFETmirror: pFET current mirror
+ * sky130_hilas_overlapCap02a: overlap capacitor based capacitor
  *
- * Verilog wrapper for sky130_hilas_pFETmirror.
+ * Verilog wrapper for sky130_hilas_overlapCap02a.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -8847,7 +9293,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETmirror (
+module sky130_hilas_overlapCap02a (
     VNB,
     VPB
 );
@@ -8861,7 +9307,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETmirror (
+module sky130_hilas_overlapCap02a (
     
 );
 endmodule
@@ -8871,18 +9317,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_PFETMIRROR
+`endif  // SKY130_HILAS_OVERLAPCAP02A
 
 
 //--------EOF---------
 
-`ifndef M12M3
-`define M12M3
+`ifndef SKY130_HILAS_WTABLOCKSAMPLE01
+`define SKY130_HILAS_WTABLOCKSAMPLE01
 
 /**
- * m12m3: 
+ * sky130_hilas_WTAblockSample01: None
  *
- * Verilog wrapper for m12m3.
+ * Verilog wrapper for sky130_hilas_WTAblockSample01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -8895,7 +9341,7 @@
 /*********************************************************/
 
 `celldefine
-module m12m3 (
+module sky130_hilas_WTAblockSample01 (
     VNB,
     VPB
 );
@@ -8909,7 +9355,7 @@
 /*********************************************************/
 
 `celldefine
-module m12m3 (
+module sky130_hilas_WTAblockSample01 (
     
 );
 endmodule
@@ -8919,18 +9365,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // M12M3
+`endif  // SKY130_HILAS_WTABLOCKSAMPLE01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01A
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01A
+`ifndef SKY130_HILAS_PFETDEVICE01D
+`define SKY130_HILAS_PFETDEVICE01D
 
 /**
- * sky130_hilas_DAC6TransistorStack01a: None
+ * sky130_hilas_pFETdevice01d: pFET transistor used in DAC block
  *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01a.
+ * Verilog wrapper for sky130_hilas_pFETdevice01d.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -8943,7 +9389,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6TransistorStack01a (
+module sky130_hilas_pFETdevice01d (
     VNB,
     VPB
 );
@@ -8957,7 +9403,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6TransistorStack01a (
+module sky130_hilas_pFETdevice01d (
     
 );
 endmodule
@@ -8967,18 +9413,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01A
+`endif  // SKY130_HILAS_PFETDEVICE01D
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DECOUP_CAP_00
-`define SKY130_HILAS_DECOUP_CAP_00
+`ifndef SKY130_HILAS_CAPMODULE01
+`define SKY130_HILAS_CAPMODULE01
 
 /**
- * sky130_hilas_decoup_cap_00: decoupling cap (intended as fill)
+ * sky130_hilas_CapModule01: None
  *
- * Verilog wrapper for sky130_hilas_decoup_cap_00.
+ * Verilog wrapper for sky130_hilas_CapModule01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -8991,7 +9437,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_decoup_cap_00 (
+module sky130_hilas_CapModule01 (
     VNB,
     VPB
 );
@@ -9005,7 +9451,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_decoup_cap_00 (
+module sky130_hilas_CapModule01 (
     
 );
 endmodule
@@ -9015,18 +9461,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DECOUP_CAP_00
+`endif  // SKY130_HILAS_CAPMODULE01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_M12M2
-`define SKY130_HILAS_M12M2
+`ifndef SKY130_HILAS_NFETLARGE
+`define SKY130_HILAS_NFETLARGE
 
 /**
- * sky130_hilas_m12m2: m1 to m2 contact
+ * sky130_hilas_nFETLarge: Single Large (W//L=100) nFET Transistor
  *
- * Verilog wrapper for sky130_hilas_m12m2.
+ * Verilog wrapper for sky130_hilas_nFETLarge.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9039,10 +9485,18 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_m12m2 (
+module sky130_hilas_nFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN,
+    VGND,
     VNB,
     VPB
 );
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+        inout VGND;
         inout VNB;
         inout VPB;
 endmodule
@@ -9053,9 +9507,14 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_m12m2 (
-    
+module sky130_hilas_nFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN
 );
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
 endmodule
 `endcelldefine
 
@@ -9063,55 +9522,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_M12M2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01E
-`define SKY130_HILAS_PFETDEVICE01E
-
-/**
- * sky130_hilas_pFETdevice01e: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01e.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01e (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01e (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01E
+`endif  // SKY130_HILAS_NFETLARGE
 
 
 //--------EOF---------
@@ -9164,13 +9575,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_NOVERLAPCAP01
-`define SKY130_HILAS_NOVERLAPCAP01
+`ifndef SKY130_HILAS_DECOUPVINJ00
+`define SKY130_HILAS_DECOUPVINJ00
 
 /**
- * sky130_hilas_nOverlapCap01: overlap capacitor based capacitor (nFET)
+ * sky130_hilas_DecoupVinj00: 
  *
- * Verilog wrapper for sky130_hilas_nOverlapCap01.
+ * Verilog wrapper for sky130_hilas_DecoupVinj00.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9183,7 +9594,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nOverlapCap01 (
+module sky130_hilas_DecoupVinj00 (
     VNB,
     VPB
 );
@@ -9197,7 +9608,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nOverlapCap01 (
+module sky130_hilas_DecoupVinj00 (
     
 );
 endmodule
@@ -9207,18 +9618,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NOVERLAPCAP01
+`endif  // SKY130_HILAS_DECOUPVINJ00
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DECOUP_CAP_01
-`define SKY130_HILAS_DECOUP_CAP_01
+`ifndef SKY130_HILAS_CAPMODULE03
+`define SKY130_HILAS_CAPMODULE03
 
 /**
- * sky130_hilas_decoup_cap_01: decoupling cap (intended as fill), variant
+ * sky130_hilas_CapModule03: None
  *
- * Verilog wrapper for sky130_hilas_decoup_cap_01.
+ * Verilog wrapper for sky130_hilas_CapModule03.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9231,12 +9642,10 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_decoup_cap_01 (
-    VPWR,
+module sky130_hilas_CapModule03 (
     VNB,
     VPB
 );
-        inout VPWR;
         inout VNB;
         inout VPB;
 endmodule
@@ -9247,7 +9656,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_decoup_cap_01 (
+module sky130_hilas_CapModule03 (
     
 );
 endmodule
@@ -9257,18 +9666,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DECOUP_CAP_01
+`endif  // SKY130_HILAS_CAPMODULE03
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_MCAP2M4
-`define SKY130_HILAS_MCAP2M4
+`ifndef SKY130_HILAS_PFETLARGEPART1
+`define SKY130_HILAS_PFETLARGEPART1
 
 /**
- * sky130_hilas_mcap2m4: metal capacitor layer contact to m4
+ * sky130_hilas_pFETLargePart1: Part of the W/L=100 pFET transistor
  *
- * Verilog wrapper for sky130_hilas_mcap2m4.
+ * Verilog wrapper for sky130_hilas_pFETLargePart1.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9281,7 +9690,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_mcap2m4 (
+module sky130_hilas_pFETLargePart1 (
     VNB,
     VPB
 );
@@ -9295,7 +9704,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_mcap2m4 (
+module sky130_hilas_pFETLargePart1 (
     
 );
 endmodule
@@ -9305,18 +9714,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_MCAP2M4
+`endif  // SKY130_HILAS_PFETLARGEPART1
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_NMIRROR03
-`define SKY130_HILAS_NMIRROR03
+`ifndef SKY130_HILAS_VINJNOR3
+`define SKY130_HILAS_VINJNOR3
 
 /**
- * sky130_hilas_nMirror03: None
+ * sky130_hilas_VinjNOR3: 3-input NOR gate capable of VING voltage
  *
- * Verilog wrapper for sky130_hilas_nMirror03.
+ * Verilog wrapper for sky130_hilas_VinjNOR3.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9329,7 +9738,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nMirror03 (
+module sky130_hilas_VinjNOR3 (
     VNB,
     VPB
 );
@@ -9343,7 +9752,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nMirror03 (
+module sky130_hilas_VinjNOR3 (
     
 );
 endmodule
@@ -9353,55 +9762,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NMIRROR03
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TUNCAP01
-`define SKY130_HILAS_TUNCAP01
-
-/**
- * sky130_hilas_TunCap01: None
- *
- * Verilog wrapper for sky130_hilas_TunCap01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunCap01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunCap01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TUNCAP01
+`endif  // SKY130_HILAS_VINJNOR3
 
 
 //--------EOF---------
@@ -9454,13 +9815,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_TGATESINGLE01
-`define SKY130_HILAS_TGATESINGLE01
+`ifndef SKY130_HILAS_DAC6BIT01
+`define SKY130_HILAS_DAC6BIT01
 
 /**
- * sky130_hilas_TgateSingle01: None
+ * sky130_hilas_DAC6bit01: None
  *
- * Verilog wrapper for sky130_hilas_TgateSingle01.
+ * Verilog wrapper for sky130_hilas_DAC6bit01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9473,7 +9834,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateSingle01 (
+module sky130_hilas_DAC6bit01 (
     VNB,
     VPB
 );
@@ -9487,7 +9848,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateSingle01 (
+module sky130_hilas_DAC6bit01 (
     
 );
 endmodule
@@ -9497,18 +9858,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_TGATESINGLE01
+`endif  // SKY130_HILAS_DAC6BIT01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_NFET03
-`define SKY130_HILAS_NFET03
+`ifndef SKY130_HILAS_NOVERLAPCAP01
+`define SKY130_HILAS_NOVERLAPCAP01
 
 /**
- * sky130_hilas_nFET03: None
+ * sky130_hilas_nOverlapCap01: overlap capacitor based capacitor (nFET)
  *
- * Verilog wrapper for sky130_hilas_nFET03.
+ * Verilog wrapper for sky130_hilas_nOverlapCap01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9521,7 +9882,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFET03 (
+module sky130_hilas_nOverlapCap01 (
     VNB,
     VPB
 );
@@ -9535,7 +9896,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFET03 (
+module sky130_hilas_nOverlapCap01 (
     
 );
 endmodule
@@ -9545,18 +9906,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NFET03
+`endif  // SKY130_HILAS_NOVERLAPCAP01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_CAPACITORSIZE01
-`define SKY130_HILAS_CAPACITORSIZE01
+`ifndef SKY130_HILAS_VINJDIODEPROTECT01
+`define SKY130_HILAS_VINJDIODEPROTECT01
 
 /**
- * sky130_hilas_capacitorSize01: smallest cap
+ * sky130_hilas_VinjDiodeProtect01: protective ESD diode for VINJ line
  *
- * Verilog wrapper for sky130_hilas_capacitorSize01.
+ * Verilog wrapper for sky130_hilas_VinjDiodeProtect01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9569,114 +9930,15 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_capacitorSize01 (
-    CAPTERM02,
-    CAPTERM01,
-    VNB,
-    VPB
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorSize01 (
-    CAPTERM02,
-    CAPTERM01
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPACITORSIZE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01B
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01B
-
-/**
- * sky130_hilas_DAC6TransistorStack01b: None
- *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01b.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01b (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01b (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01B
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DECOUPVINJ01
-`define SKY130_HILAS_DECOUPVINJ01
-
-/**
- * sky130_hilas_DecoupVinj01: 
- *
- * Verilog wrapper for sky130_hilas_DecoupVinj01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DecoupVinj01 (
+module sky130_hilas_VinjDiodeProtect01 (
+    VINJ,
+    INPUT,
     VGND,
     VNB,
     VPB
 );
+        inout VINJ;
+        inout INPUT;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -9688,9 +9950,12 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DecoupVinj01 (
-    
+module sky130_hilas_VinjDiodeProtect01 (
+    VINJ,
+    INPUT
 );
+        inout VINJ;
+        inout INPUT;
 endmodule
 `endcelldefine
 
@@ -9698,18 +9963,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DECOUPVINJ01
+`endif  // SKY130_HILAS_VINJDIODEPROTECT01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETDEVICE01B
-`define SKY130_HILAS_PFETDEVICE01B
+`ifndef SKY130_HILAS_WTA4STAGE01
+`define SKY130_HILAS_WTA4STAGE01
 
 /**
- * sky130_hilas_pFETdevice01b: pFET transistor used in DAC block
+ * sky130_hilas_WTA4Stage01: 4-input winner-take-all circuit. Connects directly to array of swc4x2cell. Can array vertically. Needs one nFET transistor current source.
  *
- * Verilog wrapper for sky130_hilas_pFETdevice01b.
+ * Verilog wrapper for sky130_hilas_WTA4Stage01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9722,451 +9987,45 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETdevice01b (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01b (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01B
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PTRANSISTORVERT01
-`define SKY130_HILAS_PTRANSISTORVERT01
-
-/**
- * sky130_hilas_pTransistorVert01: None
- *
- * Verilog wrapper for sky130_hilas_pTransistorVert01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorVert01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorVert01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PTRANSISTORVERT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TA2SIGNALBIASCELL
-`define SKY130_HILAS_TA2SIGNALBIASCELL
-
-/**
- * sky130_hilas_TA2SignalBiasCell: None
- *
- * Verilog wrapper for sky130_hilas_TA2SignalBiasCell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2SignalBiasCell (
-    VOUT_AMP2,
-    VOUT_AMP1,
-    VIN22,
-    VIN21,
-    VIN11,
-    VIN12,
-    VBIAS2,
-    VBIAS1,
-    VGND,
-    VPWR,
-    VNB,
-    VPB
-);
-        inout VOUT_AMP2;
-        inout VOUT_AMP1;
-        inout VIN22;
-        inout VIN21;
-        inout VIN11;
-        inout VIN12;
-        inout VBIAS2;
-        inout VBIAS1;
-        inout VGND;
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2SignalBiasCell (
-    VOUT_AMP2,
-    VOUT_AMP1,
-    VIN22,
-    VIN21,
-    VIN11,
-    VIN12,
-    VBIAS2,
-    VBIAS1
-);
-        inout VOUT_AMP2;
-        inout VOUT_AMP1;
-        inout VIN22;
-        inout VIN21;
-        inout VIN11;
-        inout VIN12;
-        inout VBIAS2;
-        inout VBIAS1;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TA2SIGNALBIASCELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_STEPUPDIGITALPART1
-`define SKY130_HILAS_STEPUPDIGITALPART1
-
-/**
- * sky130_hilas_StepUpDigitalPart1: step-up level shifter part
- *
- * Verilog wrapper for sky130_hilas_StepUpDigitalPart1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigitalPart1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigitalPart1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_STEPUPDIGITALPART1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_STEPUPDIGITAL
-`define SKY130_HILAS_STEPUPDIGITAL
-
-/**
- * sky130_hilas_StepUpDigital: a single level shifter
- *
- * Verilog wrapper for sky130_hilas_StepUpDigital.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigital (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigital (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_STEPUPDIGITAL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATE4DOUBLE01
-`define SKY130_HILAS_TGATE4DOUBLE01
-
-/**
- * sky130_hilas_Tgate4Double01: 4 double-throw transmission gates
- *
- * Verilog wrapper for sky130_hilas_Tgate4Double01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_Tgate4Double01 (
-    INPUT1_1,
-    SELECT1,
-    SELECT2,
-    INPUT2_2,
-    INPUT1_2,
-    SELECT3,
-    INPUT2_3,
-    SELECT4,
-    INPUT2_4,
-    INPUT1_4,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT2,
+module sky130_hilas_WTA4Stage01 (
     OUTPUT1,
-    INPUT2_1,
-    INPUT1_3,
-    VGND,
-    VNB,
-    VPB
-);
-        inout INPUT1_1;
-        inout SELECT1;
-        inout SELECT2;
-        inout INPUT2_2;
-        inout INPUT1_2;
-        inout SELECT3;
-        inout INPUT2_3;
-        inout SELECT4;
-        inout INPUT2_4;
-        inout INPUT1_4;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT2;
-        inout OUTPUT1;
-        inout INPUT2_1;
-        inout INPUT1_3;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_Tgate4Double01 (
-    INPUT1_1,
-    SELECT1,
-    SELECT2,
-    INPUT2_2,
-    INPUT1_2,
-    SELECT3,
-    INPUT2_3,
-    SELECT4,
-    INPUT2_4,
-    INPUT1_4,
-    OUTPUT4,
-    OUTPUT3,
     OUTPUT2,
-    OUTPUT1,
-    INPUT2_1,
-    INPUT1_3
-);
-        inout INPUT1_1;
-        inout SELECT1;
-        inout SELECT2;
-        inout INPUT2_2;
-        inout INPUT1_2;
-        inout SELECT3;
-        inout INPUT2_3;
-        inout SELECT4;
-        inout INPUT2_4;
-        inout INPUT1_4;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT2;
-        inout OUTPUT1;
-        inout INPUT2_1;
-        inout INPUT1_3;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATE4DOUBLE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_HORIZTRANSCELL01
-`define SKY130_HILAS_HORIZTRANSCELL01
-
-/**
- * sky130_hilas_horizTransCell01: None
- *
- * Verilog wrapper for sky130_hilas_horizTransCell01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_HORIZTRANSCELL01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_RESISTOR01
-`define SKY130_HILAS_RESISTOR01
-
-/**
- * sky130_hilas_resistor01: 
- *
- * Verilog wrapper for sky130_hilas_resistor01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_resistor01 (
-    TERM1,
-    TERM2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4,
+    DRAIN1,
+    GATE1,
+    VTUN,
+    WTAMIDDLENODE,
+    COLSEL1,
+    VINJ,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4,
     VGND,
     VNB,
     VPB
 );
-        inout TERM1;
-        inout TERM2;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+        inout DRAIN1;
+        inout GATE1;
+        inout VTUN;
+        inout WTAMIDDLENODE;
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout DRAIN4;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -10178,12 +10037,42 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_resistor01 (
-    TERM1,
-    TERM2
+module sky130_hilas_WTA4Stage01 (
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4,
+    DRAIN1,
+    GATE1,
+    VTUN,
+    WTAMIDDLENODE,
+    COLSEL1,
+    VINJ,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4
 );
-        inout TERM1;
-        inout TERM2;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+        inout DRAIN1;
+        inout GATE1;
+        inout VTUN;
+        inout WTAMIDDLENODE;
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout DRAIN4;
 endmodule
 `endcelldefine
 
@@ -10191,7 +10080,118 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_RESISTOR01
+`endif  // SKY130_HILAS_WTA4STAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X2CELLOVERLAP
+`define SKY130_HILAS_SWC4X2CELLOVERLAP
+
+/**
+ * sky130_hilas_swc4x2cellOverlap: Core switch cell, built with overlap capacitor
+ *
+ * Verilog wrapper for sky130_hilas_swc4x2cellOverlap.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cellOverlap (
+    VERT1,
+    HORIZ1,
+    DRAIN1,
+    HORIZ2,
+    DRAIN2,
+    DRAIN3,
+    HORIZ3,
+    HORIZ4,
+    DRAIN4,
+    VINJ,
+    GATESELECT1,
+    VERT2,
+    GATESELECT2,
+    GATE2,
+    GATE1,
+    VTUN,
+    VNB,
+    VPB
+);
+        inout VERT1;
+        inout HORIZ1;
+        inout DRAIN1;
+        inout HORIZ2;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout HORIZ3;
+        inout HORIZ4;
+        inout DRAIN4;
+        inout VINJ;
+        inout GATESELECT1;
+        inout VERT2;
+        inout GATESELECT2;
+        inout GATE2;
+        inout GATE1;
+        inout VTUN;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cellOverlap (
+    VERT1,
+    HORIZ1,
+    DRAIN1,
+    HORIZ2,
+    DRAIN2,
+    DRAIN3,
+    HORIZ3,
+    HORIZ4,
+    DRAIN4,
+    VINJ,
+    GATESELECT1,
+    VERT2,
+    GATESELECT2,
+    GATE2,
+    GATE1,
+    VTUN
+);
+        inout VERT1;
+        inout HORIZ1;
+        inout DRAIN1;
+        inout HORIZ2;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout HORIZ3;
+        inout HORIZ4;
+        inout DRAIN4;
+        inout VINJ;
+        inout GATESELECT1;
+        inout VERT2;
+        inout GATESELECT2;
+        inout GATE2;
+        inout GATE1;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X2CELLOVERLAP
 
 
 //--------EOF---------
\ No newline at end of file
commit	9ec92fea442f25877ace30ebac0e6a9a1e004aa5	[log] [tgz]
author	Barry Muldrey <Barry Muldrey>	Thu Aug 19 11:17:32 2021 -0500
committer	Barry Muldrey <Barry Muldrey>	Thu Aug 19 11:17:32 2021 -0500
tree	b0ff80bcfbef7ed6c19a28d9b113921375a8f499
parent	dcc9b3419b1bb01239059501f3f8d89f9ac4e1f7 [diff]