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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-037/9e82528c1aca9a2fe6ba63b25027df93f0e06cfb^!/.
commit
9e82528c1aca9a2fe6ba63b25027df93f0e06cfb
[log]
author
Barry Muldrey <barry@muldrey.net>
Thu Aug 19 20:31:30 2021 -0500
committer
Barry Muldrey <barry@muldrey.net>
Thu Aug 19 20:31:30 2021 -0500
tree
017710a559ce9d473f90a4989085c5f7fbe9401b
parent
9ec92fea442f25877ace30ebac0e6a9a1e004aa5 [diff]
DRC work

diff --git a/checks/erase_box_user_analog_project_wrapper.gds.log b/checks/erase_box_user_analog_project_wrapper.gds.log
index 1408d61..a86b905 100644
--- a/checks/erase_box_user_analog_project_wrapper.gds.log
+++ b/checks/erase_box_user_analog_project_wrapper.gds.log

@@ -1,6 +1,6 @@
 /home/bjmuld/work/mpw2/gds//user_analog_project_wrapper.gds /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_erased.gds user_analog_project_wrapper
 
-Magic 8.3 revision 196 - Compiled on Tue Aug 10 18:40:01 UTC 2021.
+Magic 8.3 revision 182 - Compiled on Sat Jul 24 11:39:08 UTC 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
 Using NULL graphics device.
@@ -34,6 +34,7 @@
 
 microns:  3006.00 x 37.00   (-43.00,  3520.00), ( 2963.00,  3557.00)  111222.00 
 lambda:     3006 x 37      (   -43,  3520 ), (  2963,  3557 )  111222    
+can't read "errorCode": no such variable
 Unrecognized layer: metal5
 Layer names are:
     mag or magnet

diff --git a/checks/erase_box_user_analog_project_wrapper_empty.gds.log b/checks/erase_box_user_analog_project_wrapper_empty.gds.log
index 0c83074..45cabd9 100644
--- a/checks/erase_box_user_analog_project_wrapper_empty.gds.log
+++ b/checks/erase_box_user_analog_project_wrapper_empty.gds.log

@@ -1,6 +1,6 @@
 /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty.gds /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds user_analog_project_wrapper
 
-Magic 8.3 revision 196 - Compiled on Tue Aug 10 18:40:01 UTC 2021.
+Magic 8.3 revision 182 - Compiled on Sat Jul 24 11:39:08 UTC 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
 Using NULL graphics device.
@@ -34,6 +34,7 @@
 
 microns:  3006.00 x 37.00   (-43.00,  3520.00), ( 2963.00,  3557.00)  111222.00 
 lambda:     3006 x 37      (   -43,  3520 ), (  2963,  3557 )  111222    
+can't read "errorCode": no such variable
 Unrecognized layer: metal5
 Layer names are:
     mag or magnet

diff --git a/checks/full_log.log b/checks/full_log.log
index 0e9320d..1e9c325 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log

@@ -3,8 +3,8 @@
 Step 0 done without fatal errors.
  Executing Step 1 of 9: Project License Check
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- SPDX COMPLIANCE Found 60 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/bjmuld/work/mpw2/README.md', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch']
+ SPDX COMPLIANCE Found 61 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/bjmuld/work/mpw2/.gitmodules~', '/home/bjmuld/work/mpw2/README.md', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sch', '/home/bjmuld/work/mpw2/xschem/xschemrc', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sym', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch', '/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sym']
  Executing Step 2 of 9: YAML File Check
  YAML file valid!
 Step 2 done without fatal errors.

diff --git a/checks/klayout_drc.log b/checks/klayout_drc.log
index eaa31ae..cf8b456 100644
--- a/checks/klayout_drc.log
+++ b/checks/klayout_drc.log

@@ -1,528 +1,359 @@
-"input" in: sky130A_mr.lydrc:88
-    Polygons (raw): 1454 (flat)  90 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:89
-    Polygons (raw): 840 (flat)  118 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:90
-    Polygons (raw): 477 (flat)  127 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:91
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:92
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:93
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:94
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:95
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:96
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:97
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:98
-    Polygons (raw): 530 (flat)  108 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:99
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:100
-    Polygons (raw): 47 (flat)  7 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:101
-    Polygons (raw): 1727 (flat)  334 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:102
-    Polygons (raw): 180 (flat)  51 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:103
-    Polygons (raw): 602 (flat)  103 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:104
-    Polygons (raw): 1105 (flat)  154 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:105
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:106
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:107
-    Polygons (raw): 284 (flat)  37 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:108
-    Polygons (raw): 34332 (flat)  1716 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:110
-    Polygons (raw): 3713 (flat)  380 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:111
-    Polygons (raw): 15344 (flat)  817 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:113
-    Polygons (raw): 3578 (flat)  1481 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:114
-    Polygons (raw): 39371 (flat)  3288 (hierarchical)
-    Elapsed: 0.010s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:116
-    Polygons (raw): 4168 (flat)  2913 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:117
-    Polygons (raw): 26788 (flat)  6052 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:119
-    Polygons (raw): 586 (flat)  554 (hierarchical)
-    Elapsed: 0.000s  Memory: 523.00M
-"polygons" in: sky130A_mr.lydrc:120
-    Polygons (raw): 122210 (flat)  122210 (hierarchical)
-    Elapsed: 0.060s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:122
-    Polygons (raw): 45 (flat)  45 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:123
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:125
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:127
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:128
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:129
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:130
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:131
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:132
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:133
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:134
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:135
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:136
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:137
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:138
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:139
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:140
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:141
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:142
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:143
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:144
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:145
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:146
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:147
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:148
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:149
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:150
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:151
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:152
-    Polygons (raw): 1 (flat)  1 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:153
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:154
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:155
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:156
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:157
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:158
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:159
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:160
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:161
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:162
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:163
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:164
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:165
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:166
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:167
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:168
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:169
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:170
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:171
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:172
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:173
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:174
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:175
-    Polygons (raw): 31 (flat)  2 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:176
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:177
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:178
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 525.00M
-"polygons" in: sky130A_mr.lydrc:179
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 525.00M
+"_input" in: sky130A_mr.lydrc:88
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:89
+Elapsed: 0.020s
+"_input" in: sky130A_mr.lydrc:90
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:91
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:92
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:93
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:94
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:95
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:96
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:97
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:98
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:99
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:100
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:101
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:102
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:103
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:104
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:105
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:106
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:107
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:108
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:110
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:111
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:113
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:114
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:116
+Elapsed: 0.020s
+"_input" in: sky130A_mr.lydrc:117
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:119
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:120
+Elapsed: 0.140s
+"_input" in: sky130A_mr.lydrc:122
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:123
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:125
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:127
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:128
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:129
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:130
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:131
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:132
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:133
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:134
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:135
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:136
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:137
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:138
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:139
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:140
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:141
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:142
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:143
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:144
+Elapsed: 0.020s
+"_input" in: sky130A_mr.lydrc:145
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:146
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:147
+Elapsed: 0.020s
+"_input" in: sky130A_mr.lydrc:148
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:149
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:150
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:151
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:152
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:153
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:154
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:155
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:156
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:157
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:158
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:159
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:160
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:161
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:162
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:163
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:164
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:165
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:166
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:167
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:168
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:169
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:170
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:171
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:172
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:173
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:174
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:175
+Elapsed: 0.020s
+"_input" in: sky130A_mr.lydrc:176
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:177
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:178
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:179
+Elapsed: 0.010s
 DRC section
 FEOL section
 "&" in: sky130A_mr.lydrc:203
-    Polygons (raw): 484 (flat)  61 (hierarchical)
-    Elapsed: 0.020s  Memory: 1069.00M
+Elapsed: 0.040s
 dnwell
-"width" in: sky130A_mr.lydrc:207
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1069.00M
-"output" in: sky130A_mr.lydrc:207
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1069.00M
+"width_check" in: sky130A_mr.lydrc:207
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:207
+Elapsed: 0.010s
 nwell
-"width" in: sky130A_mr.lydrc:215
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:215
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:216
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:216
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:215
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:215
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:216
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:216
+Elapsed: 0.010s
 hvtp
-"width" in: sky130A_mr.lydrc:235
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:235
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:236
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:236
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:235
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:235
+Elapsed: 0.020s
+"isolated_check" in: sky130A_mr.lydrc:236
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:236
+Elapsed: 0.010s
 htvr
-"width" in: sky130A_mr.lydrc:243
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:243
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:244
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:244
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:243
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:243
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:244
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:244
+Elapsed: 0.010s
 lvtn
-"isolated" in: sky130A_mr.lydrc:249
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:249
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+"isolated_check" in: sky130A_mr.lydrc:249
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:249
+Elapsed: 0.010s
 ncm
-"width" in: sky130A_mr.lydrc:261
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:261
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:261
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:261
+Elapsed: 0.010s
 diff-tap
 "+" in: sky130A_mr.lydrc:270
-    Polygons (raw): 2294 (flat)  208 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:280
-    Edge pairs: 56 (flat)  5 (hierarchical)
-    Elapsed: 0.020s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:280
-    Edge pairs: 56 (flat)  5 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:280
+Elapsed: 0.030s
+"_output" in: sky130A_mr.lydrc:280
+Elapsed: 0.010s
 tunm
-"width" in: sky130A_mr.lydrc:293
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:293
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:294
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:294
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:293
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:293
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:294
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:294
+Elapsed: 0.010s
 poly
-"width" in: sky130A_mr.lydrc:303
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:303
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"not" in: sky130A_mr.lydrc:308
-    Polygons (raw): 1727 (flat)  334 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:308
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.030s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:308
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:303
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:303
+Elapsed: 0.010s
+"-" in: sky130A_mr.lydrc:308
+Elapsed: 0.020s
+"isolated_check" in: sky130A_mr.lydrc:308
+Elapsed: 0.030s
+"_output" in: sky130A_mr.lydrc:308
+Elapsed: 0.010s
 rpm
-"width" in: sky130A_mr.lydrc:326
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:326
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:327
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:327
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:326
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:326
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:327
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:327
+Elapsed: 0.010s
 npc
-"width" in: sky130A_mr.lydrc:360
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:360
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"isolated" in: sky130A_mr.lydrc:361
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"output" in: sky130A_mr.lydrc:361
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+"width_check" in: sky130A_mr.lydrc:360
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:360
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:361
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:361
+Elapsed: 0.010s
 licon
 "interacting" in: sky130A_mr.lydrc:382
-    Polygons (raw): 31 (flat)  2 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
-"and" in: sky130A_mr.lydrc:382
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1070.00M
-"not" in: sky130A_mr.lydrc:382
-    Polygons (raw): 34332 (flat)  1716 (hierarchical)
-    Elapsed: 0.010s  Memory: 1070.00M
+Elapsed: 0.020s
+"&" in: sky130A_mr.lydrc:382
+Elapsed: 0.010s
+"-" in: sky130A_mr.lydrc:382
+Elapsed: 0.010s
 "edges" in: sky130A_mr.lydrc:382
-    Edges: 137328 (flat)  6864 (hierarchical)
-    Elapsed: 0.030s  Memory: 1070.00M
-"without_length" in: sky130A_mr.lydrc:382
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.020s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:382
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
+Elapsed: 0.040s
+"with_length" in: sky130A_mr.lydrc:382
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:382
+Elapsed: 0.010s
 "interacting" in: sky130A_mr.lydrc:383
-    Polygons (raw): 31 (flat)  2 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+Elapsed: 0.020s
+"&" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
 "interacting" in: sky130A_mr.lydrc:383
-    Polygons (raw): 31 (flat)  2 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
+Elapsed: 0.020s
+"&" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
 "edges" in: sky130A_mr.lydrc:383
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+Elapsed: 0.010s
 "with_length" in: sky130A_mr.lydrc:383
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+Elapsed: 0.010s
 "interacting" in: sky130A_mr.lydrc:383
-    Polygons (raw): 31 (flat)  2 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
 "edges" in: sky130A_mr.lydrc:383
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+Elapsed: 0.010s
 "with_length" in: sky130A_mr.lydrc:383
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"or" in: sky130A_mr.lydrc:383
-    Edges: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+Elapsed: 0.010s
+"|" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
 "not_interacting" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:383
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"or" in: sky130A_mr.lydrc:411
-    Polygons (raw): 590 (flat)  107 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"and" in: sky130A_mr.lydrc:411
-    Polygons (raw): 33901 (flat)  1665 (hierarchical)
-    Elapsed: 0.040s  Memory: 1073.00M
-"separation" in: sky130A_mr.lydrc:411
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.020s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:411
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:383
+Elapsed: 0.010s
+"|" in: sky130A_mr.lydrc:411
+Elapsed: 0.020s
+"&" in: sky130A_mr.lydrc:411
+Elapsed: 0.290s
+"separation_check" in: sky130A_mr.lydrc:411
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:411
+Elapsed: 0.010s
 vpp
 capm
-"width" in: sky130A_mr.lydrc:445
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:445
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"isolated" in: sky130A_mr.lydrc:446
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:446
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
+"width_check" in: sky130A_mr.lydrc:445
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:445
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:446
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:446
+Elapsed: 0.010s
 "interacting" in: sky130A_mr.lydrc:447
-    Polygons (raw): 0 (flat)  0 (hierarchical)
-    Elapsed: 0.030s  Memory: 1073.00M
-"isolated" in: sky130A_mr.lydrc:447
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.020s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:447
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
-"enclosing" in: sky130A_mr.lydrc:448
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:448
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"enclosing" in: sky130A_mr.lydrc:449
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:449
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
-"separation" in: sky130A_mr.lydrc:450
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:450
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+Elapsed: 0.060s
+"isolated_check" in: sky130A_mr.lydrc:447
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:447
+Elapsed: 0.010s
+"enclosing_check" in: sky130A_mr.lydrc:448
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:448
+Elapsed: 0.010s
+"enclosing_check" in: sky130A_mr.lydrc:449
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:449
+Elapsed: 0.010s
+"separation_check" in: sky130A_mr.lydrc:450
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:450
+Elapsed: 0.010s
 FEOL section
 hvi
-"width" in: sky130A_mr.lydrc:766
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:766
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
+"width_check" in: sky130A_mr.lydrc:766
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:766
+Elapsed: 0.010s
 hvntm
-"width" in: sky130A_mr.lydrc:792
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:792
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
-"isolated" in: sky130A_mr.lydrc:793
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.010s  Memory: 1073.00M
-"output" in: sky130A_mr.lydrc:793
-    Edge pairs: 0 (flat)  0 (hierarchical)
-    Elapsed: 0.000s  Memory: 1073.00M
+"width_check" in: sky130A_mr.lydrc:792
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:792
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:793
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:793
+Elapsed: 0.020s
 Writing report database: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_klayout_drc.xml ..
-Total elapsed: 1.490s  Memory: 1071.00M
+Total run time: 2.550s

diff --git a/checks/magic_drc.log b/checks/magic_drc.log
index e1f7b05..fb8d8bd 100644
--- a/checks/magic_drc.log
+++ b/checks/magic_drc.log

@@ -1,5 +1,5 @@
 
-Magic 8.3 revision 196 - Compiled on Tue Aug 10 18:40:01 UTC 2021.
+Magic 8.3 revision 182 - Compiled on Sat Jul 24 11:39:08 UTC 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
 Using NULL graphics device.

diff --git a/checks/met_min_ca_density_check.log b/checks/met_min_ca_density_check.log
index 6e2415e..9644ae5 100644
--- a/checks/met_min_ca_density_check.log
+++ b/checks/met_min_ca_density_check.log

@@ -1,5 +1,5 @@
-li1_ca_density is 0.9995210723848069
-m1_ca_density is 0.998528255672089
+li1_ca_density is 0.9995210740776774
+m1_ca_density is 0.9985282514691003
 m2_ca_density is 0.9749639026015722
 m3_ca_density is 0.9263081444096357
 m4_ca_density is 0.9274977941508407

diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index 90eab95..eceed1a 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log

@@ -1,62 +1,63 @@
 FULL RUN LOG:
 SPDX NON-COMPLIANT FILES
+/home/bjmuld/work/mpw2/.gitmodules~
 /home/bjmuld/work/mpw2/README.md
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_cellAttempt01.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelProtectStructure.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sch
 /home/bjmuld/work/mpw2/xschem/xschemrc
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LeftProtection.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGcharacterization01.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG.sch
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_cellAttempt01.sym
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_RightProtection.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x2cell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_1FG_Strong.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_nFETLarge.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_VinjDiodeProtect01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_DAC5bit01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_WTA4Stage01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans2med.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_FGtrans2x1cell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_swc4x1BiasCell.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sym
 /home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sch
-/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Single01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Tgate4Double01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_Trans4small.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_capacitorArray01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_cellAttempt01.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_drainSelect01.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_polyresistorGND.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TA2Cell_NoFG.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sch
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_pFETLarge.sym
+/home/bjmuld/work/mpw2/xschem/sky130_hilas_TopProtection.sym
 /home/bjmuld/work/mpw2/verilog/rtl/sky130_hilas_sc.v

diff --git a/checks/user_analog_project_wrapper_klayout_drc.xml b/checks/user_analog_project_wrapper_klayout_drc.xml
index 400ea2c..d7ba85d 100644
--- a/checks/user_analog_project_wrapper_klayout_drc.xml
+++ b/checks/user_analog_project_wrapper_klayout_drc.xml

@@ -216,52 +216,12 @@
    </references>
   </cell>
   <cell>
-   <name>sky130_hilas_FGcharacterization01</name>
+   <name>sky130_hilas_TopProtection</name>
    <variant/>
    <references>
     <ref>
      <parent>user_analog_project_wrapper</parent>
-     <trans>m90 *1 1496.06,3334.92</trans>
-    </ref>
-   </references>
-  </cell>
-  <cell>
-   <name>sky130_hilas_pFETdevice01w1</name>
-   <variant/>
-   <references>
-    <ref>
-     <parent>user_analog_project_wrapper</parent>
-     <trans>m90 *1 1493.82,3341.47</trans>
-    </ref>
-   </references>
-  </cell>
-  <cell>
-   <name>sky130_hilas_drainSelect01</name>
-   <variant/>
-   <references>
-    <ref>
-     <parent>user_analog_project_wrapper</parent>
-     <trans>r180 *1 1535.25,3325.29</trans>
-    </ref>
-   </references>
-  </cell>
-  <cell>
-   <name>sky130_hilas_TgateVinj01</name>
-   <variant/>
-   <references>
-    <ref>
-     <parent>user_analog_project_wrapper</parent>
-     <trans>m90 *1 1522.43,3322.63</trans>
-    </ref>
-   </references>
-  </cell>
-  <cell>
-   <name>sky130_hilas_RightProtection</name>
-   <variant/>
-   <references>
-    <ref>
-     <parent>user_analog_project_wrapper</parent>
-     <trans>r0 *1 1724.32,3058.16</trans>
+     <trans>r0 *1 1360.39,3348.46</trans>
     </ref>
    </references>
   </cell>
@@ -271,7 +231,7 @@
    <references>
     <ref>
      <parent>user_analog_project_wrapper</parent>
-     <trans>m45 *1 1706.77,3152.76</trans>
+     <trans>r0 *1 1680.56,3350.76</trans>
     </ref>
    </references>
   </cell>
@@ -286,12 +246,22 @@
    </references>
   </cell>
   <cell>
-   <name>sky130_hilas_TopProtection</name>
+   <name>sky130_hilas_RightProtection</name>
    <variant/>
    <references>
     <ref>
      <parent>user_analog_project_wrapper</parent>
-     <trans>r0 *1 1360.39,3348.46</trans>
+     <trans>r0 *1 1724.32,3058.16</trans>
+    </ref>
+   </references>
+  </cell>
+  <cell>
+   <name>sky130_hilas_FGcharacterization01</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>m90 *1 1496.06,3334.92</trans>
     </ref>
    </references>
   </cell>
@@ -299,46 +269,35 @@
  <items>
   <item>
    <tags/>
-   <category>'difftap.3'</category>
-   <cell>sky130_hilas_FGcharacterization01</cell>
+   <category>'nwell.1'</category>
+   <cell>sky130_hilas_TopLevelTextStructure</cell>
    <visited>false</visited>
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (2.97,6.36;2.97,6.75)|(2.72,6.75;2.72,6.33)</value>
+    <value>edge-pair: (75.86,40.77;75.85,40.77)/(75.85,40.78;75.86,40.78)</value>
    </values>
   </item>
   <item>
    <tags/>
-   <category>'difftap.3'</category>
-   <cell>sky130_hilas_pFETdevice01w1</cell>
+   <category>'nwell.1'</category>
+   <cell>sky130_hilas_TopLevelTextStructure</cell>
    <visited>false</visited>
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (0.73,-0.19;0.73,0.2)|(0.48,0.2;0.48,-0.22)</value>
+    <value>edge-pair: (75.86,46.8;75.85,46.8)/(75.85,46.81;75.86,46.81)</value>
    </values>
   </item>
   <item>
    <tags/>
-   <category>'difftap.3'</category>
-   <cell>sky130_hilas_TgateVinj01</cell>
+   <category>'nwell.1'</category>
+   <cell>sky130_hilas_TopLevelTextStructure</cell>
    <visited>false</visited>
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (-1.77,0.55;-1.77,0.91)|(-1.89,0.86;-1.89,0.308)</value>
-   </values>
-  </item>
-  <item>
-   <tags/>
-   <category>'difftap.3'</category>
-   <cell>sky130_hilas_TgateVinj01</cell>
-   <visited>false</visited>
-   <multiplicity>1</multiplicity>
-   <image/>
-   <values>
-    <value>edge-pair: (-1.77,-0.12;-1.77,0.25)|(-1.89,0.492;-1.89,-0.07)</value>
+    <value>edge-pair: (75.86,46.8;75.85,46.8)/(75.86,46.86;76.698,46.86)</value>
    </values>
   </item>
   <item>
@@ -349,7 +308,18 @@
    <multiplicity>1</multiplicity>
    <image/>
    <values>
-    <value>edge-pair: (8.32,4.72;18.5,4.72)|(18.641,4.95;8.179,4.95)</value>
+    <value>edge-pair: (8.34,4.69;18.5,4.69)/(18.573,4.95;8.267,4.95)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'hvntm.1'</category>
+   <cell>sky130_hilas_FGcharacterization01</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (16.695,6.192;16.695,7.378)/(17.365,7.175;17.365,6.395)</value>
    </values>
   </item>
  </items>

diff --git a/checks/xor.log b/checks/xor.log
index b4baf17..096a006 100644
--- a/checks/xor.log
+++ b/checks/xor.log

@@ -3,9 +3,9 @@
 Design Name: xor_target
 Output GDS will be: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper.xor.gds
 Reading /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds ..
-ERROR: In /usr/local/bin/xor_checks/xor.drc: 'source': Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read
-Total elapsed: 0.000s  Memory: 519.00M
-ERROR: 'source': Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read in Executable::execute
-  /usr/local/bin/xor_checks/xor.drc:15:in `execute'
-  :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
-  :/built-in-macros/drc_interpreters.lym:27:in `execute'
+ERROR: In /usr/local/bin/xor_checks/xor.drc: Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read
+ERROR: Stream has unknown format: /home/bjmuld/work/mpw2/checks/user_analog_project_wrapper_empty_erased.gds in Layout::read in MacroInterpreter::execute
+  /usr/local/bin/xor_checks/xor.drc:15:in `execute_drc'
+  :/built-in-macros/drc_interpreters.lym:18:in `instance_eval'
+  :/built-in-macros/drc_interpreters.lym:18:in `execute_drc'
+  :/built-in-macros/drc_interpreters.lym:92:in `execute'

diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index ba31c76..d88b60d 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ

diff --git a/mag/sky130_hilas_DAC5bit01.mag b/mag/sky130_hilas_DAC5bit01.mag
index d0a9f57..d0085fb 100644
--- a/mag/sky130_hilas_DAC5bit01.mag
+++ b/mag/sky130_hilas_DAC5bit01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 481 1069 520 1072
 rect 642 1069 681 1072
@@ -176,118 +176,118 @@
 rect 382 715 1569 735
 rect 382 714 396 715
 rect 382 603 1236 623
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_9
-timestamp 1628285143
-transform 1 0 413 0 1 1089
-box -9 -26 24 29
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_11
-timestamp 1628285143
-transform 1 0 413 0 1 863
-box -9 -26 24 29
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_12
-timestamp 1628285143
-transform 1 0 413 0 1 769
-box -9 -26 24 29
-use sky130_hilas_DAC6TransistorStack01a  sky130_hilas_DAC6TransistorStack01a_0
-timestamp 1628285143
-transform 1 0 391 0 1 701
-box 28 -174 200 391
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_10
-timestamp 1628285143
-transform 1 0 411 0 1 958
-box -9 -26 24 29
 use sky130_hilas_poly2m2  sky130_hilas_poly2m2_8
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 584 0 1 1093
 box -9 -26 24 29
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_7
-timestamp 1628285143
-transform 0 1 734 -1 0 1073
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_10
+timestamp 1629420194
+transform 1 0 411 0 1 958
 box -9 -26 24 29
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_6
-timestamp 1628285143
-transform 1 0 904 0 1 1093
+use sky130_hilas_DAC6TransistorStack01a  sky130_hilas_DAC6TransistorStack01a_0
+timestamp 1629420194
+transform 1 0 391 0 1 701
+box 28 -174 200 391
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_12
+timestamp 1629420194
+transform 1 0 413 0 1 769
 box -9 -26 24 29
-use sky130_hilas_li2m1  sky130_hilas_li2m1_6
-timestamp 1628285143
-transform 1 0 855 0 1 532
-box -10 -8 13 21
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_11
+timestamp 1629420194
+transform 1 0 413 0 1 863
+box -9 -26 24 29
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_9
+timestamp 1629420194
+transform 1 0 413 0 1 1089
+box -9 -26 24 29
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 693 0 1 532
 box -10 -8 13 21
+use sky130_hilas_li2m1  sky130_hilas_li2m1_6
+timestamp 1629420194
+transform 1 0 855 0 1 532
+box -10 -8 13 21
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_6
+timestamp 1629420194
+transform 1 0 904 0 1 1093
+box -9 -26 24 29
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_7
+timestamp 1629420194
+transform 0 1 734 -1 0 1073
+box -9 -26 24 29
 use sky130_hilas_DAC6TransistorStack01  sky130_hilas_DAC6TransistorStack01_0
 array 0 2 161 0 0 566
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 552 0 1 701
 box 28 -174 200 391
-use sky130_hilas_DAC6TransistorStack01b  sky130_hilas_DAC6TransistorStack01b_0
-timestamp 1628285143
-transform 1 0 1035 0 1 701
-box 13 -174 204 391
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_5
-timestamp 1628285143
-transform 1 0 1065 0 1 1094
-box -9 -26 24 29
 use sky130_hilas_li2m1  sky130_hilas_li2m1_7
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1015 0 1 532
 box -10 -8 13 21
-use sky130_hilas_DAC6TransistorStack01c  sky130_hilas_DAC6TransistorStack01c_0
-timestamp 1628285143
-transform 1 0 1196 0 1 701
-box 28 -174 215 391
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_3
-timestamp 1628285143
-transform 1 0 1388 0 1 1094
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_5
+timestamp 1629420194
+transform 1 0 1065 0 1 1094
 box -9 -26 24 29
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_4
-timestamp 1628285143
-transform 1 0 1227 0 1 1093
-box -9 -26 24 29
-use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
-transform 1 0 1217 0 1 607
-box -9 -10 23 22
-use sky130_hilas_li2m1  sky130_hilas_li2m1_1
-timestamp 1628285143
-transform 1 0 1177 0 1 532
-box -10 -8 13 21
+use sky130_hilas_DAC6TransistorStack01b  sky130_hilas_DAC6TransistorStack01b_0
+timestamp 1629420194
+transform 1 0 1035 0 1 701
+box 13 -174 204 391
 use sky130_hilas_li2m1  sky130_hilas_li2m1_5
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1337 0 1 532
 box -10 -8 13 21
+use sky130_hilas_li2m1  sky130_hilas_li2m1_1
+timestamp 1629420194
+transform 1 0 1177 0 1 532
+box -10 -8 13 21
+use sky130_hilas_m12m2  sky130_hilas_m12m2_0
+timestamp 1629420194
+transform 1 0 1217 0 1 607
+box -9 -10 23 22
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_4
+timestamp 1629420194
+transform 1 0 1227 0 1 1093
+box -9 -26 24 29
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_3
+timestamp 1629420194
+transform 1 0 1388 0 1 1094
+box -9 -26 24 29
+use sky130_hilas_DAC6TransistorStack01c  sky130_hilas_DAC6TransistorStack01c_0
+timestamp 1629420194
+transform 1 0 1196 0 1 701
+box 28 -174 215 391
 use sky130_hilas_DAC6TransistorStack01  sky130_hilas_DAC6TransistorStack01_2
 array 0 2 161 0 0 566
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1357 0 1 701
 box 28 -174 200 391
 use sky130_hilas_poly2m2  sky130_hilas_poly2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1549 0 1 1094
 box -9 -26 24 29
 use sky130_hilas_DAC6TransistorStack01a  sky130_hilas_DAC6TransistorStack01a_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1840 0 1 701
 box 28 -174 200 391
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1679 0 1 1090
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1746 0 1 1090
 box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1659 0 1 532
 box -10 -8 13 21
 use sky130_hilas_li2m1  sky130_hilas_li2m1_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1820 0 1 532
 box -10 -8 13 21
 use sky130_hilas_li2m1  sky130_hilas_li2m1_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1499 0 1 532
 box -10 -8 13 21
 << labels >>

diff --git a/mag/sky130_hilas_DAC6TransistorStack01.mag b/mag/sky130_hilas_DAC6TransistorStack01.mag
index 3308673..8f1bf1c 100644
--- a/mag/sky130_hilas_DAC6TransistorStack01.mag
+++ b/mag/sky130_hilas_DAC6TransistorStack01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 90 368 129 371
 rect 90 326 129 329
@@ -14,28 +14,28 @@
 rect 89 -58 128 -55
 rect 90 -112 129 -109
 rect 90 -154 129 -151
-use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
-timestamp 1628285143
-transform 1 0 108 0 1 -132
-box -80 -42 81 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
-timestamp 1628285143
-transform 1 0 108 0 1 348
-box -80 -78 92 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_0
-timestamp 1628285143
-transform 1 0 107 0 1 -36
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_4
-timestamp 1628285143
-transform 1 0 107 0 1 60
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_3
-timestamp 1628285143
-transform 1 0 107 0 1 156
-box -79 -78 82 43
 use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_6
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 107 0 1 252
 box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_3
+timestamp 1629420194
+transform 1 0 107 0 1 156
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_4
+timestamp 1629420194
+transform 1 0 107 0 1 60
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_0
+timestamp 1629420194
+transform 1 0 107 0 1 -36
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
+timestamp 1629420194
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
+timestamp 1629420194
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
 << end >>

diff --git a/mag/sky130_hilas_DAC6TransistorStack01a.mag b/mag/sky130_hilas_DAC6TransistorStack01a.mag
index cab584c..55ab651 100644
--- a/mag/sky130_hilas_DAC6TransistorStack01a.mag
+++ b/mag/sky130_hilas_DAC6TransistorStack01a.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 90 368 129 371
 rect 90 326 129 329
@@ -14,28 +14,28 @@
 rect 90 -58 129 -55
 rect 90 -112 129 -109
 rect 90 -154 129 -151
-use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
-timestamp 1628285143
-transform 1 0 108 0 1 -132
-box -80 -42 81 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_3
-timestamp 1628285143
-transform 1 0 108 0 1 348
-box -80 -78 92 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_2
-timestamp 1628285143
-transform 1 0 108 0 1 252
-box -80 -78 92 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_4
-timestamp 1628285143
-transform 1 0 108 0 1 156
-box -80 -78 92 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_1
-timestamp 1628285143
-transform 1 0 108 0 1 60
-box -80 -78 92 43
 use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 108 0 1 -36
 box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_1
+timestamp 1629420194
+transform 1 0 108 0 1 60
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_4
+timestamp 1629420194
+transform 1 0 108 0 1 156
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_2
+timestamp 1629420194
+transform 1 0 108 0 1 252
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_3
+timestamp 1629420194
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
+timestamp 1629420194
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
 << end >>

diff --git a/mag/sky130_hilas_DAC6TransistorStack01b.mag b/mag/sky130_hilas_DAC6TransistorStack01b.mag
index 19dcc23..0cf9065 100644
--- a/mag/sky130_hilas_DAC6TransistorStack01b.mag
+++ b/mag/sky130_hilas_DAC6TransistorStack01b.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 90 368 129 371
 rect 90 326 129 329
@@ -14,28 +14,28 @@
 rect 89 -58 128 -55
 rect 90 -112 129 -109
 rect 90 -154 129 -151
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_0
-timestamp 1628285143
-transform 1 0 107 0 1 -36
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_4
-timestamp 1628285143
-transform 1 0 107 0 1 60
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_6
-timestamp 1628285143
-transform 1 0 107 0 1 252
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
-timestamp 1628285143
-transform 1 0 108 0 1 348
-box -80 -78 92 43
-use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
-timestamp 1628285143
-transform 1 0 108 0 1 -132
-box -80 -42 81 43
 use sky130_hilas_pFETdevice01d  sky130_hilas_pFETdevice01d_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 107 0 1 156
 box -94 -102 97 43
+use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
+timestamp 1629420194
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
+timestamp 1629420194
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_6
+timestamp 1629420194
+transform 1 0 107 0 1 252
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_4
+timestamp 1629420194
+transform 1 0 107 0 1 60
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_0
+timestamp 1629420194
+transform 1 0 107 0 1 -36
+box -79 -78 82 43
 << end >>

diff --git a/mag/sky130_hilas_DAC6TransistorStack01c.mag b/mag/sky130_hilas_DAC6TransistorStack01c.mag
index fd33e34..a392136 100644
--- a/mag/sky130_hilas_DAC6TransistorStack01c.mag
+++ b/mag/sky130_hilas_DAC6TransistorStack01c.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 90 368 129 371
 rect 90 326 129 329
@@ -14,28 +14,28 @@
 rect 89 -58 128 -55
 rect 90 -112 129 -109
 rect 90 -154 129 -151
-use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
-timestamp 1628285143
-transform 1 0 108 0 1 -132
-box -80 -42 81 43
-use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
-timestamp 1628285143
-transform 1 0 108 0 1 348
-box -80 -78 92 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_6
-timestamp 1628285143
-transform 1 0 107 0 1 252
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_3
-timestamp 1628285143
-transform 1 0 107 0 1 156
-box -79 -78 82 43
-use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_0
-timestamp 1628285143
-transform 1 0 107 0 1 -36
-box -79 -78 82 43
 use sky130_hilas_pFETdevice01b  sky130_hilas_pFETdevice01b_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 107 0 1 60
 box -79 -114 108 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_0
+timestamp 1629420194
+transform 1 0 107 0 1 -36
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_3
+timestamp 1629420194
+transform 1 0 107 0 1 156
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01  sky130_hilas_pFETdevice01_6
+timestamp 1629420194
+transform 1 0 107 0 1 252
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01aa  sky130_hilas_pFETdevice01aa_0
+timestamp 1629420194
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01a  sky130_hilas_pFETdevice01a_0
+timestamp 1629420194
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
 << end >>

diff --git a/mag/sky130_hilas_DualTACore01.mag b/mag/sky130_hilas_DualTACore01.mag
index f5cc025..2bf4108 100644
--- a/mag/sky130_hilas_DualTACore01.mag
+++ b/mag/sky130_hilas_DualTACore01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -87 540 -60 546
 rect -87 498 -60 504
@@ -27,51 +27,51 @@
 rect -136 211 155 233
 rect -137 -6 134 17
 use sky130_hilas_pFETmirror02  sky130_hilas_pFETmirror02_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 88 0 1 -111
 box -61 89 67 373
 use sky130_hilas_nMirror03  sky130_hilas_nMirror03_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -113 0 1 130
 box -59 -6 125 123
 use sky130_hilas_nMirror03  sky130_hilas_nMirror03_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -113 0 -1 97
 box -59 -6 125 123
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 106 0 1 228
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 98 0 1 3
 box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 41 0 1 126
 box -10 -8 13 21
 use sky130_hilas_pFETmirror02  sky130_hilas_pFETmirror02_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 88 0 -1 635
 box -61 89 67 373
 use sky130_hilas_nMirror03  sky130_hilas_nMirror03_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -113 0 -1 397
 box -59 -6 125 123
 use sky130_hilas_nMirror03  sky130_hilas_nMirror03_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -113 0 1 430
 box -59 -6 125 123
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 107 0 1 300
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 102 0 1 522
 box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 41 0 1 385
 box -10 -8 13 21
 << labels >>

diff --git a/mag/sky130_hilas_FGBias2x1cell.mag b/mag/sky130_hilas_FGBias2x1cell.mag
index 04c884f..50334f2 100644
--- a/mag/sky130_hilas_FGBias2x1cell.mag
+++ b/mag/sky130_hilas_FGBias2x1cell.mag

@@ -1,7 +1,9 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
+rect 426 228 511 306
+rect 426 223 427 228
 rect 568 195 618 201
 rect 640 195 690 201
 rect 568 153 618 159
@@ -92,59 +94,59 @@
 rect -396 -320 526 -315
 rect -396 -330 514 -320
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 986 0 1 62
 box -1005 -380 -733 -211
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 986 0 -1 -231
 box -1005 -380 -733 -211
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1056 0 1 19
 box -1451 -400 -1278 -210
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1056 0 1 433
 box -1451 -400 -1278 -210
 use sky130_hilas_wellContact  sky130_hilas_wellContact_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1054 0 1 231
 box -1448 -441 -1275 -255
 use sky130_hilas_wellContact  sky130_hilas_wellContact_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1054 0 1 404
 box -1448 -441 -1275 -255
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -103 0 1 -92
 box -10 -8 13 21
 use sky130_hilas_horizTransCell01  sky130_hilas_horizTransCell01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 790 0 1 -429
 box -476 42 -33 359
 use sky130_hilas_horizTransCell01  sky130_hilas_horizTransCell01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 790 0 -1 270
 box -476 42 -33 359
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 627 0 1 -116
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 627 0 1 -56
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 721 0 1 -84
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 538 0 1 -216
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 538 0 1 60
 box -14 -15 20 18
 << labels >>

diff --git a/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag b/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag
index d50bdf2..e8f1bfa 100644
--- a/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag
+++ b/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 568 195 618 201
 rect 640 195 690 201
@@ -108,63 +108,63 @@
 rect -396 -320 526 -315
 rect -396 -330 514 -320
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 986 0 1 62
 box -1005 -380 -733 -211
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 986 0 -1 -231
 box -1005 -380 -733 -211
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1056 0 1 433
 box -1451 -400 -1278 -210
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1056 0 1 19
 box -1451 -400 -1278 -210
 use sky130_hilas_wellContact  sky130_hilas_wellContact_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1054 0 1 404
 box -1448 -441 -1275 -255
 use sky130_hilas_wellContact  sky130_hilas_wellContact_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1054 0 1 231
 box -1448 -441 -1275 -255
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -191 0 1 -268
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -188 0 1 101
 box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -103 0 1 -92
 box -10 -8 13 21
 use sky130_hilas_horizTransCell01  sky130_hilas_horizTransCell01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 790 0 1 -429
 box -476 42 -33 359
 use sky130_hilas_horizTransCell01  sky130_hilas_horizTransCell01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 790 0 -1 270
 box -476 42 -33 359
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 627 0 1 -116
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 627 0 1 -56
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 538 0 1 -216
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 538 0 1 60
 box -14 -15 20 18
 << labels >>

diff --git a/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag b/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag
index 178d037..897ea1f 100644
--- a/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag
+++ b/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -556 -677 413 -217
 rect -556 -816 473 -677

diff --git a/mag/sky130_hilas_FGVaractorCapacitor.mag b/mag/sky130_hilas_FGVaractorCapacitor.mag
index 48c327f..1796487 100644
--- a/mag/sky130_hilas_FGVaractorCapacitor.mag
+++ b/mag/sky130_hilas_FGVaractorCapacitor.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -957 -395 -734 -210
 << mvvaractor >>

diff --git a/mag/sky130_hilas_FGVaractorCapacitor02.mag b/mag/sky130_hilas_FGVaractorCapacitor02.mag
index e6055bf..9273ba7 100644
--- a/mag/sky130_hilas_FGVaractorCapacitor02.mag
+++ b/mag/sky130_hilas_FGVaractorCapacitor02.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -1005 -215 -734 -211
 rect -1005 -380 -733 -215

diff --git a/mag/sky130_hilas_FGVaractorTunnelCap01.mag b/mag/sky130_hilas_FGVaractorTunnelCap01.mag
index 45bb6a4..f314992 100644
--- a/mag/sky130_hilas_FGVaractorTunnelCap01.mag
+++ b/mag/sky130_hilas_FGVaractorTunnelCap01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -1005 -380 -783 -211
 << mvvaractor >>

diff --git a/mag/sky130_hilas_FGcharacterization01.mag b/mag/sky130_hilas_FGcharacterization01.mag
index 3fcd3a8..66ed039 100644
--- a/mag/sky130_hilas_FGcharacterization01.mag
+++ b/mag/sky130_hilas_FGcharacterization01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 52 825 81 841
 rect 131 825 160 841
@@ -177,6 +177,8 @@
 rect 1745 820 1751 837
 rect 1688 814 1751 820
 rect 1688 751 1751 764
+rect 1689 736 1718 737
+rect 1688 621 1718 736
 rect 1688 592 1751 597
 rect 1688 536 1751 542
 rect 1688 519 1693 536
@@ -375,14 +377,12 @@
 rect 1689 278 2043 284
 << mvnsubdiff >>
 rect 311 688 352 696
-rect 311 675 323 688
-rect 297 671 323 675
+rect 311 671 323 688
 rect 340 671 352 688
-rect 297 654 352 671
-rect 297 637 323 654
+rect 311 654 352 671
+rect 311 637 323 654
 rect 340 637 352 654
-rect 297 636 352 637
-rect 311 620 352 636
+rect 311 620 352 637
 rect 311 603 323 620
 rect 340 603 352 620
 rect 311 598 352 603
@@ -688,171 +688,171 @@
 rect 1719 287 1763 305
 rect -531 266 1792 287
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 563 0 1 1073
 box -1005 -380 -733 -211
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 563 0 1 774
 box -1005 -380 -733 -211
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 563 0 1 673
 box -1005 -380 -733 -211
 use sky130_hilas_nOverlapCap01  sky130_hilas_nOverlapCap01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -795 0 1 395
 box -62 -43 67 86
 use sky130_hilas_FGVaractorTunnelCap01  sky130_hilas_FGVaractorTunnelCap01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 93 0 1 1068
 box -1005 -380 -783 -211
 use sky130_hilas_overlapCap02a  sky130_hilas_overlapCap02a_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 506 0 1 748
 box -521 -54 -121 110
 use sky130_hilas_overlapCap02a  sky130_hilas_overlapCap02a_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 506 0 1 313
 box -521 -54 -121 110
 use sky130_hilas_overlapCap02a  sky130_hilas_overlapCap02a_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 506 0 1 468
 box -521 -54 -121 110
 use sky130_hilas_li2m2  sky130_hilas_li2m2_14
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -520 0 1 283
 box -14 -15 20 18
 use sky130_hilas_FGHugeVaractorCapacitor01  sky130_hilas_FGHugeVaractorCapacitor01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1099 0 1 1077
 box -556 -816 473 -217
 use sky130_hilas_pFETdevice01w1  sky130_hilas_pFETdevice01w1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 224 0 1 655
 box -79 -78 82 43
 use sky130_hilas_li2m2  sky130_hilas_li2m2_11
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 394 0 1 647
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_12
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 258 0 1 655
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_13
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 189 0 1 654
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 466 0 1 281
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_9
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1706 0 1 298
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_6
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1851 0 1 299
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_5
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1777 0 1 299
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1792 0 1 359
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_8
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2014 0 1 299
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_7
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1921 0 1 299
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1935 0 1 357
 box -14 -15 20 18
 use sky130_hilas_poly2li  sky130_hilas_poly2li_5
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 1805 0 -1 480
 box -9 -14 18 19
 use sky130_hilas_li2m2  sky130_hilas_li2m2_10
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 1795 0 -1 479
 box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1791 0 1 524
 box -10 -8 13 21
 use sky130_hilas_poly2li  sky130_hilas_poly2li_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1921 0 1 440
 box -9 -14 18 19
 use sky130_hilas_m12m2  sky130_hilas_m12m2_9
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2000 0 1 497
 box -9 -10 23 22
 use sky130_hilas_poly2m2  sky130_hilas_poly2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1743 0 1 666
 box -9 -26 24 29
 use sky130_hilas_nDiffThOxContact  sky130_hilas_nDiffThOxContact_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1712 0 1 580
 box -26 13 41 42
 use sky130_hilas_m12m2  sky130_hilas_m12m2_6
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1859 0 1 720
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1857 0 1 634
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1859 0 1 676
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2000 0 1 632
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2000 0 1 719
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2000 0 1 674
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1933 0 1 721
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1933 0 1 637
 box -14 -15 20 18
 use sky130_hilas_nDiffThOxContact  sky130_hilas_nDiffThOxContact_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1712 0 1 723
 box -26 13 41 42
 use sky130_hilas_m12m2  sky130_hilas_m12m2_10
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1713 0 1 827
 box -9 -10 23 22
 use sky130_hilas_poly2li  sky130_hilas_poly2li_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1924 0 1 828
 box -9 -14 18 19
 use sky130_hilas_m12m2  sky130_hilas_m12m2_7
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1999 0 1 822
 box -9 -10 23 22
 use sky130_hilas_poly2li  sky130_hilas_poly2li_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2064 0 1 828
 box -9 -14 18 19
 << labels >>

diff --git a/mag/sky130_hilas_FGtrans2x1cell.mag b/mag/sky130_hilas_FGtrans2x1cell.mag
index bec6ad3..25a37c8 100644
--- a/mag/sky130_hilas_FGtrans2x1cell.mag
+++ b/mag/sky130_hilas_FGtrans2x1cell.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 568 195 618 201
 rect 640 195 690 201
@@ -167,83 +167,83 @@
 rect -395 -330 514 -320
 rect 749 -332 757 -314
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_0
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 -752 0 1 62
 box -1005 -380 -733 -211
 use sky130_hilas_FGVaractorCapacitor02  sky130_hilas_FGVaractorCapacitor02_2
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 -752 0 -1 -231
 box -1005 -380 -733 -211
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1056 0 1 433
 box -1451 -400 -1278 -210
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1056 0 1 19
 box -1451 -400 -1278 -210
 use sky130_hilas_wellContact  sky130_hilas_wellContact_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1054 0 1 231
 box -1448 -441 -1275 -255
 use sky130_hilas_wellContact  sky130_hilas_wellContact_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1054 0 1 404
 box -1448 -441 -1275 -255
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -103 0 1 -92
 box -10 -8 13 21
-use sky130_hilas_li2m1  sky130_hilas_li2m1_5
-timestamp 1628285143
-transform 1 0 478 0 1 -332
-box -10 -8 13 21
-use sky130_hilas_li2m1  sky130_hilas_li2m1_2
-timestamp 1628285143
-transform 1 0 435 0 1 -281
-box -10 -8 13 21
-use sky130_hilas_li2m1  sky130_hilas_li2m1_3
-timestamp 1628285143
-transform 1 0 480 0 1 -141
-box -10 -8 13 21
-use sky130_hilas_li2m1  sky130_hilas_li2m1_1
-timestamp 1628285143
-transform 1 0 434 0 1 -123
-box -10 -8 13 21
 use sky130_hilas_poly2m1  sky130_hilas_poly2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 389 0 1 -74
 box -9 -26 24 25
-use sky130_hilas_li2m1  sky130_hilas_li2m1_7
-timestamp 1628285143
-transform 1 0 481 0 1 -34
+use sky130_hilas_li2m1  sky130_hilas_li2m1_1
+timestamp 1629420194
+transform 1 0 434 0 1 -123
 box -10 -8 13 21
-use sky130_hilas_li2m1  sky130_hilas_li2m1_4
-timestamp 1628285143
-transform 1 0 434 0 1 109
+use sky130_hilas_li2m1  sky130_hilas_li2m1_3
+timestamp 1629420194
+transform 1 0 480 0 1 -141
+box -10 -8 13 21
+use sky130_hilas_li2m1  sky130_hilas_li2m1_2
+timestamp 1629420194
+transform 1 0 435 0 1 -281
+box -10 -8 13 21
+use sky130_hilas_li2m1  sky130_hilas_li2m1_5
+timestamp 1629420194
+transform 1 0 478 0 1 -332
 box -10 -8 13 21
 use sky130_hilas_li2m1  sky130_hilas_li2m1_6
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 481 0 1 165
 box -10 -8 13 21
-use sky130_hilas_horizTransCell01a  sky130_hilas_horizTransCell01a_1
-timestamp 1628285143
-transform 1 0 790 0 -1 270
-box -476 42 -33 359
+use sky130_hilas_li2m1  sky130_hilas_li2m1_4
+timestamp 1629420194
+transform 1 0 434 0 1 109
+box -10 -8 13 21
+use sky130_hilas_li2m1  sky130_hilas_li2m1_7
+timestamp 1629420194
+transform 1 0 481 0 1 -34
+box -10 -8 13 21
 use sky130_hilas_horizTransCell01a  sky130_hilas_horizTransCell01a_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 790 0 1 -429
 box -476 42 -33 359
+use sky130_hilas_horizTransCell01a  sky130_hilas_horizTransCell01a_1
+timestamp 1629420194
+transform 1 0 790 0 -1 270
+box -476 42 -33 359
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 628 0 1 -85
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 563 0 1 -166
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 562 0 1 3
 box -14 -15 20 18
 << labels >>

diff --git a/mag/sky130_hilas_LeftProtection.mag b/mag/sky130_hilas_LeftProtection.mag
index e455c59..0d4f200 100644
--- a/mag/sky130_hilas_LeftProtection.mag
+++ b/mag/sky130_hilas_LeftProtection.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1627737364
+timestamp 1629421669
 << metal1 >>
 rect -898 27122 -834 27516
 rect -2065 26640 -1984 27030
@@ -29,55 +29,55 @@
 rect -897 -7184 -833 -6790
 rect -2065 -7668 -1984 -7278
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_0
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 -7694
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_1
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 -4835
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_2
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 -1976
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_3
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 883
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_4
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 3742
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_6
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 6601
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_9
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 9460
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_7
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 12319
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_8
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 15178
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_5
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 18037
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_10
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 20896
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_11
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 23755
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_12
-timestamp 1627735001
+timestamp 1629421669
 transform 0 -1 -1126 1 0 26614
 box -745 -229 2114 858
 << labels >>

diff --git a/mag/sky130_hilas_LevelShift4InputUp.mag b/mag/sky130_hilas_LevelShift4InputUp.mag
index 5e31473..3d10c99 100644
--- a/mag/sky130_hilas_LevelShift4InputUp.mag
+++ b/mag/sky130_hilas_LevelShift4InputUp.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628420416
+timestamp 1629420194
 << error_s >>
 rect 35 554 85 560
 rect 358 555 408 561
@@ -84,21 +84,21 @@
 rect 830 87 840 119
 rect -30 5 -14 25
 rect 830 -88 840 -56
-use sky130_hilas_StepUpDigital  StepUpDigital_0
-timestamp 1628285143
-transform 1 0 -49 0 1 113
-box 19 -44 889 131
-use sky130_hilas_StepUpDigital  StepUpDigital_3
-timestamp 1628285143
-transform 1 0 -49 0 1 -62
+use sky130_hilas_StepUpDigital  StepUpDigital_2
+timestamp 1629420194
+transform 1 0 -49 0 1 463
 box 19 -44 889 131
 use sky130_hilas_StepUpDigital  StepUpDigital_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -49 0 1 288
 box 19 -44 889 131
-use sky130_hilas_StepUpDigital  StepUpDigital_2
-timestamp 1628285143
-transform 1 0 -49 0 1 463
+use sky130_hilas_StepUpDigital  StepUpDigital_3
+timestamp 1629420194
+transform 1 0 -49 0 1 -62
+box 19 -44 889 131
+use sky130_hilas_StepUpDigital  StepUpDigital_0
+timestamp 1629420194
+transform 1 0 -49 0 1 113
 box 19 -44 889 131
 << labels >>
 rlabel metal1 4 -102 33 -97 0 VINJ

diff --git a/mag/sky130_hilas_RightProtection.mag b/mag/sky130_hilas_RightProtection.mag
index a53089c..ab7fb45 100644
--- a/mag/sky130_hilas_RightProtection.mag
+++ b/mag/sky130_hilas_RightProtection.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1627737364
+timestamp 1629421669
 << metal1 >>
 rect -2053 27123 -1982 27519
 rect -898 26641 -826 27030
@@ -16,33 +16,33 @@
 rect -898 12346 -826 12735
 rect -2053 9967 -1983 10363
 rect -898 9486 -826 9875
-use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_12
-timestamp 1627735001
-transform 0 1 -1755 1 0 26614
-box -745 -229 2114 858
-use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_11
-timestamp 1627735001
-transform 0 1 -1755 1 0 23755
-box -745 -229 2114 858
-use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_10
-timestamp 1627735001
-transform 0 1 -1755 1 0 20896
-box -745 -229 2114 858
-use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_5
-timestamp 1627735001
-transform 0 1 -1755 1 0 18037
-box -745 -229 2114 858
-use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_8
-timestamp 1627735001
-transform 0 1 -1755 1 0 15178
+use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_9
+timestamp 1629421669
+transform 0 1 -1755 1 0 9460
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_7
-timestamp 1627735001
+timestamp 1629421669
 transform 0 1 -1755 1 0 12319
 box -745 -229 2114 858
-use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_9
-timestamp 1627735001
-transform 0 1 -1755 1 0 9460
+use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_8
+timestamp 1629421669
+transform 0 1 -1755 1 0 15178
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_5
+timestamp 1629421669
+transform 0 1 -1755 1 0 18037
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_10
+timestamp 1629421669
+transform 0 1 -1755 1 0 20896
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_11
+timestamp 1629421669
+transform 0 1 -1755 1 0 23755
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_12
+timestamp 1629421669
+transform 0 1 -1755 1 0 26614
 box -745 -229 2114 858
 << labels >>
 rlabel metal1 -898 9486 -826 9875 0 IO7

diff --git a/mag/sky130_hilas_StepUpDigital.mag b/mag/sky130_hilas_StepUpDigital.mag
index d8099a7..04b092f 100644
--- a/mag/sky130_hilas_StepUpDigital.mag
+++ b/mag/sky130_hilas_StepUpDigital.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 84 91 134 97
 rect 407 92 457 98
@@ -157,7 +157,7 @@
 rect 290 62 293 88
 rect 260 60 292 62
 use sky130_hilas_StepUpDigitalPart1  StepUpDigitalPart1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -3 0 1 5
 box 278 -49 892 120
 << labels >>

diff --git a/mag/sky130_hilas_StepUpDigitalPart1.mag b/mag/sky130_hilas_StepUpDigitalPart1.mag
index 707eac3..4f72e30 100644
--- a/mag/sky130_hilas_StepUpDigitalPart1.mag
+++ b/mag/sky130_hilas_StepUpDigitalPart1.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect 410 87 460 93
 rect 567 86 595 93

diff --git a/mag/sky130_hilas_TA2Cell_1FG.mag b/mag/sky130_hilas_TA2Cell_1FG.mag
index 6afa7ce..fa40f02 100644
--- a/mag/sky130_hilas_TA2Cell_1FG.mag
+++ b/mag/sky130_hilas_TA2Cell_1FG.mag

@@ -1,7 +1,9 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
+rect -651 750 -566 828
+rect -651 745 -650 750
 rect -2549 717 -2499 723
 rect -2477 717 -2427 723
 rect -509 717 -459 723
@@ -183,22 +185,22 @@
 rect -1169 158 -1129 159
 rect -1169 148 -1166 158
 rect -1198 146 -1166 148
-use sky130_hilas_DualTACore01  sky130_hilas_DualTACore01_0
-timestamp 1628285143
-transform 1 0 38 0 1 181
-box -172 -26 155 553
-use sky130_hilas_pTransistorPair  sky130_hilas_pTransistorPair_1
-timestamp 1628285143
-transform 1 0 -454 0 -1 305
-box 133 -440 320 165
+use sky130_hilas_FGBias2x1cell  sky130_hilas_FGBias2x1cell_0
+timestamp 1629420194
+transform 1 0 -1077 0 1 522
+box -396 -387 757 306
 use sky130_hilas_FGBiasWeakGate2x1cell  sky130_hilas_FGBiasWeakGate2x1cell_0
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 -1859 0 1 522
 box -396 -387 757 228
-use sky130_hilas_FGBias2x1cell  sky130_hilas_FGBias2x1cell_0
-timestamp 1628285143
-transform 1 0 -1077 0 1 522
-box -396 -387 757 228
+use sky130_hilas_pTransistorPair  sky130_hilas_pTransistorPair_1
+timestamp 1629420194
+transform 1 0 -454 0 -1 305
+box 133 -440 320 165
+use sky130_hilas_DualTACore01  sky130_hilas_DualTACore01_0
+timestamp 1629420194
+transform 1 0 38 0 1 181
+box -172 -26 155 553
 << labels >>
 rlabel metal2 -1726 617 -1690 636 0 VIN11
 port 2 nsew analog default

diff --git a/mag/sky130_hilas_TA2Cell_1FG_Strong.mag b/mag/sky130_hilas_TA2Cell_1FG_Strong.mag
index 774b51f..982dcbb 100644
--- a/mag/sky130_hilas_TA2Cell_1FG_Strong.mag
+++ b/mag/sky130_hilas_TA2Cell_1FG_Strong.mag

@@ -1,7 +1,9 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
+rect -651 750 -566 828
+rect -651 745 -650 750
 rect -2550 717 -2500 723
 rect -2478 717 -2428 723
 rect -509 717 -459 723
@@ -165,22 +167,22 @@
 rect -1166 160 -124 162
 rect -1166 147 -1163 160
 rect -1195 145 -1163 147
-use sky130_hilas_FGtrans2x1cell  sky130_hilas_FGtrans2x1cell_0
-timestamp 1628285143
-transform -1 0 -1860 0 1 522
-box -395 -387 757 228
 use sky130_hilas_FGBias2x1cell  sky130_hilas_FGBias2x1cell_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -1077 0 1 522
-box -396 -387 757 228
-use sky130_hilas_pTransistorPair  sky130_hilas_pTransistorPair_1
-timestamp 1628285143
-transform 1 0 -454 0 -1 305
-box 133 -440 320 165
+box -396 -387 757 306
 use sky130_hilas_DualTACore01  sky130_hilas_DualTACore01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 38 0 1 181
 box -172 -26 155 553
+use sky130_hilas_pTransistorPair  sky130_hilas_pTransistorPair_1
+timestamp 1629420194
+transform 1 0 -454 0 -1 305
+box 133 -440 320 165
+use sky130_hilas_FGtrans2x1cell  sky130_hilas_FGtrans2x1cell_0
+timestamp 1629420194
+transform -1 0 -1860 0 1 522
+box -395 -387 757 228
 << labels >>
 rlabel metal1 -3 739 31 745 0 VGND
 port 11 nsew

diff --git a/mag/sky130_hilas_Tgate4Single01.mag b/mag/sky130_hilas_Tgate4Single01.mag
index 36f6d2b..8cb2b9a 100644
--- a/mag/sky130_hilas_Tgate4Single01.mag
+++ b/mag/sky130_hilas_Tgate4Single01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 165 453 205 459
 rect 315 453 355 459
@@ -54,21 +54,21 @@
 rect -36 -50 -30 -30
 rect 433 -50 440 -30
 rect -36 -148 -31 -128
-use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_1
-timestamp 1628285143
-transform 1 0 227 0 1 22
-box -263 -186 213 -25
-use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_2
-timestamp 1628285143
-transform 1 0 227 0 -1 -29
+use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_3
+timestamp 1629420194
+transform 1 0 227 0 1 342
 box -263 -186 213 -25
 use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 227 0 -1 291
 box -263 -186 213 -25
-use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_3
-timestamp 1628285143
-transform 1 0 227 0 1 342
+use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_2
+timestamp 1629420194
+transform 1 0 227 0 -1 -29
+box -263 -186 213 -25
+use sky130_hilas_TgateSingle01  sky130_hilas_TgateSingle01_1
+timestamp 1629420194
+transform 1 0 227 0 1 22
 box -263 -186 213 -25
 << labels >>
 rlabel metal2 -36 270 -30 290 0 SELECT2

diff --git a/mag/sky130_hilas_TgateSingle01.mag b/mag/sky130_hilas_TgateSingle01.mag
index 4558628..de518a5 100644
--- a/mag/sky130_hilas_TgateSingle01.mag
+++ b/mag/sky130_hilas_TgateSingle01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -138 -59 -98 -54
 rect 88 -59 128 -52
@@ -79,26 +79,26 @@
 rect -176 -150 -64 -149
 rect -263 -170 -64 -150
 rect -176 -171 -64 -170
-use sky130_hilas_TgateSingle01Part2  sky130_hilas_TgateSingle01Part2_0
-timestamp 1628285143
-transform 1 0 -71 0 1 0
-box -67 -181 96 -38
-use sky130_hilas_TgateSingle01Part1  sky130_hilas_TgateSingle01Part1_0
-timestamp 1628285143
-transform 1 0 -232 0 1 0
-box 257 -181 445 -29
-use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
-transform 1 0 -225 0 1 -62
-box -9 -10 23 22
-use sky130_hilas_li2m1  sky130_hilas_li2m1_2
-timestamp 1628285143
-transform 1 0 -180 0 1 -86
-box -10 -8 13 21
 use sky130_hilas_poly2m1  sky130_hilas_poly2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -236 0 1 -65
 box -9 -26 24 25
+use sky130_hilas_li2m1  sky130_hilas_li2m1_2
+timestamp 1629420194
+transform 1 0 -180 0 1 -86
+box -10 -8 13 21
+use sky130_hilas_m12m2  sky130_hilas_m12m2_0
+timestamp 1629420194
+transform 1 0 -225 0 1 -62
+box -9 -10 23 22
+use sky130_hilas_TgateSingle01Part1  sky130_hilas_TgateSingle01Part1_0
+timestamp 1629420194
+transform 1 0 -232 0 1 0
+box 257 -181 445 -29
+use sky130_hilas_TgateSingle01Part2  sky130_hilas_TgateSingle01Part2_0
+timestamp 1629420194
+transform 1 0 -71 0 1 0
+box -67 -181 96 -38
 << labels >>
 rlabel metal2 -263 -72 -254 -52 0 Select
 rlabel metal2 -263 -170 -254 -150 0 Input

diff --git a/mag/sky130_hilas_TgateSingle01Part1.mag b/mag/sky130_hilas_TgateSingle01Part1.mag
index b548938..7362b59 100644
--- a/mag/sky130_hilas_TgateSingle01Part1.mag
+++ b/mag/sky130_hilas_TgateSingle01Part1.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 320 -59 360 -52
 rect 320 -101 360 -94
@@ -64,22 +64,22 @@
 << metal2 >>
 rect 257 -72 445 -52
 rect 257 -170 314 -150
-use sky130_hilas_m12m2  sky130_hilas_m12m2_3
-timestamp 1628285143
-transform 1 0 335 0 1 -68
-box -9 -10 23 22
-use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
-transform 1 0 304 0 1 -155
-box -14 -15 20 18
-use sky130_hilas_li2m1  sky130_hilas_li2m1_1
-timestamp 1628285143
-transform 1 0 402 0 1 -86
-box -10 -8 13 21
 use sky130_hilas_li2m1  sky130_hilas_li2m1_5
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 356 0 1 -148
 box -10 -8 13 21
+use sky130_hilas_li2m1  sky130_hilas_li2m1_1
+timestamp 1629420194
+transform 1 0 402 0 1 -86
+box -10 -8 13 21
+use sky130_hilas_li2m2  sky130_hilas_li2m2_3
+timestamp 1629420194
+transform 1 0 304 0 1 -155
+box -14 -15 20 18
+use sky130_hilas_m12m2  sky130_hilas_m12m2_3
+timestamp 1629420194
+transform 1 0 335 0 1 -68
+box -9 -10 23 22
 << labels >>
 rlabel metal2 439 -72 445 -52 0 output
 << end >>

diff --git a/mag/sky130_hilas_TgateSingle01Part2.mag b/mag/sky130_hilas_TgateSingle01Part2.mag
index bd7b039..34b1583 100644
--- a/mag/sky130_hilas_TgateSingle01Part2.mag
+++ b/mag/sky130_hilas_TgateSingle01Part2.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 9 -126 49 -120
 rect 9 -168 49 -162
@@ -38,16 +38,16 @@
 rect -67 -150 -45 -149
 rect -67 -170 96 -150
 rect -67 -171 -45 -170
-use sky130_hilas_m12m2  sky130_hilas_m12m2_2
-timestamp 1628285143
-transform 1 0 73 0 1 -69
-box -9 -10 23 22
-use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
-transform 1 0 -14 0 1 -155
-box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 82 0 1 -147
 box -10 -8 13 21
+use sky130_hilas_li2m2  sky130_hilas_li2m2_2
+timestamp 1629420194
+transform 1 0 -14 0 1 -155
+box -14 -15 20 18
+use sky130_hilas_m12m2  sky130_hilas_m12m2_2
+timestamp 1629420194
+transform 1 0 73 0 1 -69
+box -9 -10 23 22
 << end >>

diff --git a/mag/sky130_hilas_TgateVinj01.mag b/mag/sky130_hilas_TgateVinj01.mag
index 41c2e89..d3236ff 100644
--- a/mag/sky130_hilas_TgateVinj01.mag
+++ b/mag/sky130_hilas_TgateVinj01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -147 91 -97 97
 rect 173 91 223 97
@@ -81,17 +81,19 @@
 rect 304 5 314 22
 rect 283 -7 314 5
 << nsubdiff >>
-rect -214 56 -189 86
-rect -214 39 -210 56
-rect -193 39 -189 56
-rect -214 22 -189 39
+rect -214 78 -177 91
+rect -214 61 -210 78
+rect -192 61 -177 78
+rect -214 55 -177 61
+rect -214 25 -188 55
+rect -214 22 -177 25
 rect -214 5 -210 22
-rect -193 5 -189 22
-rect -214 -7 -189 5
+rect -193 5 -177 22
+rect -214 -12 -177 5
 << psubdiffcont >>
 rect 287 5 304 22
 << nsubdiffcont >>
-rect -210 39 -193 56
+rect -210 61 -192 78
 rect -210 5 -193 22
 << poly >>
 rect -147 99 319 114
@@ -117,13 +119,14 @@
 rect 294 79 311 96
 << locali >>
 rect 294 96 311 104
+rect -210 78 -192 86
+rect -210 41 -192 61
 rect -170 78 -153 86
-rect -210 56 -193 60
-rect -210 22 -193 24
 rect -100 62 -91 79
 rect -74 65 150 79
 rect -74 62 -43 65
 rect -170 50 -153 61
+rect -210 22 -193 24
 rect -52 48 -43 62
 rect -26 62 150 65
 rect 167 62 175 79
@@ -152,9 +155,7 @@
 rect 246 0 256 17
 rect 199 -3 223 0
 << viali >>
-rect -210 60 -193 77
-rect -210 39 -193 41
-rect -210 24 -193 39
+rect -210 24 -193 41
 rect -210 -12 -193 5
 rect -170 33 -153 50
 rect 300 52 317 69
@@ -164,19 +165,18 @@
 rect 287 -12 304 5
 << metal1 >>
 rect -174 89 -149 124
-rect -213 77 -149 89
-rect -213 60 -210 77
-rect -193 60 -149 77
-rect -213 50 -149 60
+rect -213 50 -149 89
 rect -213 41 -170 50
-rect -213 24 -210 41
+rect -213 25 -210 41
+rect -214 24 -210 25
 rect -193 33 -170 41
 rect -153 33 -149 50
 rect -193 24 -149 33
-rect -213 5 -149 24
+rect -214 5 -149 24
 rect -59 22 -25 25
 rect -59 21 -54 22
-rect -213 -12 -210 5
+rect -214 -11 -210 5
+rect -213 -12 -210 -11
 rect -193 -12 -149 5
 rect -81 18 -54 21
 rect -81 1 -72 18
@@ -236,7 +236,7 @@
 rect 213 -4 216 22
 rect 184 -7 216 -4
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 266 0 1 65
 box -10 -8 13 21
 << end >>

diff --git a/mag/sky130_hilas_TopLevelTextStructure.mag b/mag/sky130_hilas_TopLevelTextStructure.mag
index dc07513..cc73fee 100644
--- a/mag/sky130_hilas_TopLevelTextStructure.mag
+++ b/mag/sky130_hilas_TopLevelTextStructure.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1629332956
+timestamp 1629420194
 << error_s >>
 rect 2364 6133 2393 6149
 rect 2443 6133 2472 6149
@@ -183,7 +183,9 @@
 rect 4242 4681 4270 4687
 rect 4384 4680 4412 4687
 rect 4519 4681 4569 4687
+rect 7585 4686 7670 4764
 rect 4842 4680 4892 4686
+rect 7585 4681 7586 4686
 rect 5686 4653 5736 4659
 rect 5758 4653 5808 4659
 rect 7727 4653 7777 4659
@@ -298,13 +300,8 @@
 rect 4771 4151 4821 4157
 rect 5686 4140 5736 4146
 rect 5758 4140 5808 4146
-rect 7727 4140 7777 4146
-rect 7799 4140 7849 4146
-rect 8187 4140 8214 4146
 rect 5096 4128 5146 4134
 rect 5416 4128 5466 4134
-rect 10945 4121 10985 4127
-rect 11095 4121 11135 4127
 rect 4193 4114 4221 4120
 rect 4433 4114 4461 4120
 rect 4590 4114 4641 4120
@@ -314,13 +311,19 @@
 rect 5416 4104 5466 4109
 rect 5686 4098 5736 4104
 rect 5758 4098 5808 4104
-rect 7727 4098 7777 4104
-rect 7799 4098 7849 4104
-rect 8187 4098 8214 4104
 rect 4242 4084 4270 4090
 rect 4384 4084 4412 4091
 rect 4519 4084 4569 4090
 rect 4842 4085 4892 4091
+rect 7585 4078 7586 4161
+rect 7727 4140 7777 4146
+rect 7799 4140 7849 4146
+rect 8187 4140 8214 4146
+rect 10945 4121 10985 4127
+rect 11095 4121 11135 4127
+rect 7727 4098 7777 4104
+rect 7799 4098 7849 4104
+rect 8187 4098 8214 4104
 rect 10945 4080 10985 4086
 rect 11095 4080 11135 4086
 rect 5096 4062 5146 4067
@@ -3647,95 +3650,95 @@
 rect 8095 3777 8099 3813
 rect 8052 3771 8099 3777
 use sky130_hilas_pFETLarge  sky130_hilas_pFETLarge_0
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 2012 0 -1 1081
 box 64 419 528 1018
 use sky130_hilas_nFETLarge  sky130_hilas_nFETLarge_0
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 2008 0 -1 1836
 box 64 420 501 1003
 use sky130_hilas_DAC5bit01  sky130_hilas_DAC5bit01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 0 1 9912 1 0 -1031
 box 382 524 2040 1123
 use sky130_hilas_Trans2med  sky130_hilas_Trans2med_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 2073 0 -1 2311
 box -380 -143 -27 452
-use sky130_hilas_LevelShift4InputUp  sky130_hilas_LevelShift4InputUp_3
-timestamp 1628420416
-transform -1 0 4923 0 -1 2334
-box -30 -106 840 594
-use sky130_hilas_LevelShift4InputUp  sky130_hilas_LevelShift4InputUp_2
-timestamp 1628420416
-transform -1 0 4927 0 -1 3240
-box -30 -106 840 594
-use sky130_hilas_WTA4Stage01  sky130_hilas_WTA4Stage01_0
-timestamp 1628285143
-transform 1 0 6825 0 1 1804
-box -1121 -61 296 589
 use sky130_hilas_drainSelect01  sky130_hilas_drainSelect01_3
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 6602 0 -1 2371
 box 1050 -28 1622 631
 use sky130_hilas_drainSelect01  sky130_hilas_drainSelect01_2
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 6599 0 -1 3298
 box 1050 -28 1622 631
+use sky130_hilas_LevelShift4InputUp  sky130_hilas_LevelShift4InputUp_3
+timestamp 1629420194
+transform -1 0 4923 0 -1 2334
+box -30 -106 840 594
+use sky130_hilas_LevelShift4InputUp  sky130_hilas_LevelShift4InputUp_2
+timestamp 1629420194
+transform -1 0 4927 0 -1 3240
+box -30 -106 840 594
+use sky130_hilas_WTA4Stage01  sky130_hilas_WTA4Stage01_0
+timestamp 1629420194
+transform 1 0 6825 0 1 1804
+box -1121 -61 296 589
 use sky130_hilas_pFETLarge  sky130_hilas_pFETLarge_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 4824 0 1 606
 box 64 419 528 1018
 use sky130_hilas_pFETLarge  sky130_hilas_pFETLarge_2
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 5880 0 1 606
 box 64 419 528 1018
 use sky130_hilas_pFETLarge  sky130_hilas_pFETLarge_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 5805 0 1 609
 box 64 419 528 1018
 use sky130_hilas_pFETLarge  sky130_hilas_pFETLarge_4
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 6861 0 1 609
 box 64 419 528 1018
 use sky130_hilas_nFETLarge  sky130_hilas_nFETLarge_1
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 7435 0 1 608
 box 64 420 501 1003
 use sky130_hilas_Trans4small  sky130_hilas_Trans4small_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1738 0 1 4259
 box 191 -150 471 455
+use sky130_hilas_TA2Cell_1FG_Strong  sky130_hilas_TA2Cell_1FG_Strong_0
+timestamp 1629420194
+transform 1 0 8236 0 1 3936
+box -2617 135 193 828
+use sky130_hilas_TA2Cell_1FG  sky130_hilas_TA2Cell_1FG_0
+timestamp 1629420194
+transform 1 0 8236 0 1 3333
+box -2616 135 193 828
+use sky130_hilas_drainSelect01  sky130_hilas_drainSelect01_1
+timestamp 1629420194
+transform -1 0 6601 0 -1 4345
+box 1050 -28 1622 631
 use sky130_hilas_LevelShift4InputUp  sky130_hilas_LevelShift4InputUp_1
-timestamp 1628420416
+timestamp 1629420194
 transform -1 0 4927 0 -1 4253
 box -30 -106 840 594
 use sky130_hilas_swc4x2cell  sky130_hilas_swc4x2cell_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 6765 0 1 2702
 box -1004 -26 1008 624
-use sky130_hilas_TA2Cell_1FG  sky130_hilas_TA2Cell_1FG_0
-timestamp 1628285143
-transform 1 0 8236 0 1 3333
-box -2616 135 193 750
-use sky130_hilas_TA2Cell_1FG_Strong  sky130_hilas_TA2Cell_1FG_Strong_0
-timestamp 1628285143
-transform 1 0 8236 0 1 3936
-box -2617 135 193 750
-use sky130_hilas_drainSelect01  sky130_hilas_drainSelect01_1
-timestamp 1628285143
-transform -1 0 6601 0 -1 4345
-box 1050 -28 1622 631
 use sky130_hilas_Tgate4Single01  sky130_hilas_Tgate4Single01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 10780 0 1 3947
 box -36 -164 440 477
 use sky130_hilas_FGcharacterization01  sky130_hilas_FGcharacterization01_0
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 2682 0 1 5308
 box -912 259 2083 864
 use sky130_hilas_LevelShift4InputUp  sky130_hilas_LevelShift4InputUp_0
-timestamp 1628420416
+timestamp 1629420194
 transform -1 0 4927 0 1 4476
 box -30 -106 840 594
 << labels >>

diff --git a/mag/sky130_hilas_TopProtectStructure.mag b/mag/sky130_hilas_TopProtectStructure.mag
index e056770..45ab04b 100644
--- a/mag/sky130_hilas_TopProtectStructure.mag
+++ b/mag/sky130_hilas_TopProtectStructure.mag

@@ -1,12 +1,11 @@
 magic
 tech sky130A
-timestamp 1627744303
+timestamp 1629421669
 << error_s >>
 rect -626 12757 -597 12773
 rect -547 12757 -518 12773
 rect -468 12757 -439 12773
 rect -389 12757 -360 12773
-rect -502 12734 -485 12735
 rect -626 12723 -625 12724
 rect -598 12723 -597 12724
 rect -547 12723 -546 12724
@@ -22,14 +21,12 @@
 rect -390 12722 -359 12723
 rect -626 12715 -597 12722
 rect -547 12715 -518 12722
-rect -502 12715 -485 12716
 rect -468 12715 -439 12722
 rect -389 12715 -360 12722
 rect -626 12701 -617 12715
 rect -370 12701 -360 12715
 rect -626 12695 -597 12701
 rect -547 12695 -518 12701
-rect -502 12699 -485 12701
 rect -468 12695 -439 12701
 rect -389 12695 -360 12701
 rect -627 12694 -596 12695
@@ -45,18 +42,14 @@
 rect -440 12693 -439 12694
 rect -389 12693 -388 12694
 rect -361 12693 -360 12694
-rect -502 12680 -485 12682
 rect -626 12644 -597 12659
 rect -547 12644 -518 12659
 rect -468 12644 -439 12659
 rect -389 12644 -360 12659
-rect -553 12607 -514 12610
-rect -553 12565 -514 12568
 rect -626 12477 -597 12493
 rect -547 12477 -518 12493
 rect -468 12477 -439 12493
 rect -389 12477 -360 12493
-rect -502 12454 -485 12455
 rect -626 12443 -625 12444
 rect -598 12443 -597 12444
 rect -547 12443 -546 12444
@@ -72,14 +65,12 @@
 rect -390 12442 -359 12443
 rect -626 12435 -597 12442
 rect -547 12435 -518 12442
-rect -502 12435 -485 12436
 rect -468 12435 -439 12442
 rect -389 12435 -360 12442
 rect -626 12421 -617 12435
 rect -370 12421 -360 12435
 rect -626 12415 -597 12421
 rect -547 12415 -518 12421
-rect -502 12419 -485 12421
 rect -468 12415 -439 12421
 rect -389 12415 -360 12421
 rect -627 12414 -596 12415
@@ -95,7 +86,6 @@
 rect -440 12413 -439 12414
 rect -389 12413 -388 12414
 rect -361 12413 -360 12414
-rect -502 12400 -485 12402
 rect 470 12395 499 12413
 rect -626 12364 -597 12379
 rect -547 12364 -518 12379
@@ -117,7 +107,6 @@
 rect 531 12334 549 12363
 rect 470 12333 471 12334
 rect 498 12333 499 12334
-rect -502 12299 -485 12300
 rect -626 12288 -625 12289
 rect -598 12288 -597 12289
 rect -547 12288 -546 12289
@@ -133,14 +122,12 @@
 rect -390 12287 -359 12288
 rect -626 12280 -597 12287
 rect -547 12280 -518 12287
-rect -502 12280 -485 12281
 rect -468 12280 -439 12287
 rect -389 12280 -360 12287
 rect -626 12266 -617 12280
 rect -370 12266 -360 12280
 rect -626 12260 -597 12266
 rect -547 12260 -518 12266
-rect -502 12264 -485 12266
 rect -468 12260 -439 12266
 rect -389 12260 -360 12266
 rect -627 12259 -596 12260
@@ -157,1051 +144,573 @@
 rect -440 12258 -439 12259
 rect -389 12258 -388 12259
 rect -361 12258 -360 12259
-rect -502 12245 -485 12247
 rect -626 12209 -597 12224
 rect -547 12209 -518 12224
 rect -468 12209 -439 12224
 rect -389 12209 -360 12224
-rect 1242 11570 1270 11586
-rect 1384 11570 1412 11586
-rect 1519 11576 1569 11585
-rect 1852 11579 1902 11590
-rect 1488 11570 1519 11576
-rect 1818 11573 1852 11579
-rect 1296 11544 1301 11549
-rect 1242 11528 1270 11544
-rect 1384 11528 1412 11544
-rect 1519 11534 1569 11543
-rect 1736 11536 1753 11541
-rect 1852 11537 1902 11548
-rect 1909 11528 1926 11529
-rect 1193 11507 1221 11524
-rect 1433 11507 1461 11524
-rect 1590 11508 1641 11518
-rect 1781 11517 1831 11528
-rect 1909 11509 1926 11510
-rect 1654 11503 1673 11508
-rect 1193 11465 1221 11482
-rect 1433 11465 1461 11482
-rect 1559 11476 1590 11482
-rect 1668 11476 1673 11503
-rect 1749 11486 1781 11491
-rect 1590 11466 1641 11476
-rect 1781 11475 1831 11486
-rect 1242 11415 1270 11431
-rect 1384 11415 1412 11431
-rect 1519 11421 1569 11430
-rect 1852 11424 1902 11435
-rect 1488 11415 1519 11421
-rect 1818 11418 1852 11424
-rect 1296 11389 1301 11394
-rect 1242 11373 1270 11389
-rect 1384 11373 1412 11389
-rect 1519 11379 1569 11388
-rect 1736 11381 1753 11386
-rect 1852 11382 1902 11393
-rect 1909 11373 1926 11374
-rect 1193 11352 1221 11369
-rect 1433 11352 1461 11369
-rect 1590 11353 1641 11363
-rect 1781 11362 1831 11373
-rect 1909 11354 1926 11355
-rect 1654 11348 1673 11353
-rect -943 11308 -916 11315
-rect 1193 11310 1221 11327
-rect 1433 11310 1461 11327
-rect 1559 11321 1590 11327
-rect 1668 11321 1673 11348
-rect 1749 11331 1781 11336
-rect 1590 11311 1641 11321
-rect 1781 11320 1831 11331
-rect -943 11266 -916 11273
-rect 1242 11260 1270 11276
-rect 1384 11260 1412 11276
-rect 1519 11266 1569 11275
-rect 1852 11269 1902 11280
-rect 2696 11271 2746 11282
-rect 2768 11271 2818 11282
-rect 4737 11271 4787 11282
-rect 4809 11271 4859 11282
-rect 5197 11277 5224 11284
-rect 1488 11260 1519 11266
-rect 1818 11263 1852 11269
-rect 5400 11264 5417 11269
-rect 2818 11240 2852 11241
-rect 4703 11240 4737 11241
-rect 1296 11234 1301 11239
-rect -943 11216 -916 11223
-rect 1242 11218 1270 11234
-rect 1384 11218 1412 11234
-rect 1519 11224 1569 11233
-rect 1736 11226 1753 11231
-rect 1852 11227 1902 11238
-rect 2696 11229 2746 11240
-rect 2768 11229 2818 11240
-rect 4737 11229 4787 11240
-rect 4809 11229 4859 11240
-rect 5197 11235 5224 11242
-rect 1909 11218 1926 11219
-rect 1193 11197 1221 11214
-rect 1433 11197 1461 11214
-rect 1590 11198 1641 11208
-rect 1781 11207 1831 11218
-rect 5197 11211 5224 11218
-rect 2760 11208 2769 11210
-rect 2820 11208 2852 11210
-rect 2884 11208 2923 11210
-rect 3019 11208 3059 11210
-rect 4496 11208 4536 11210
-rect 4632 11208 4671 11210
-rect 4703 11208 4735 11210
-rect 4786 11208 4795 11210
-rect 1909 11199 1926 11200
-rect 1654 11193 1673 11198
-rect -943 11174 -916 11181
-rect 1193 11155 1221 11172
-rect 1433 11155 1461 11172
-rect 1559 11166 1590 11172
-rect 1668 11166 1673 11193
-rect 1749 11176 1781 11181
-rect 1590 11156 1641 11166
-rect 1781 11165 1831 11176
-rect -943 11124 -916 11131
-rect 1242 11105 1270 11121
-rect 1384 11105 1412 11121
-rect 1519 11111 1569 11120
-rect 1852 11114 1902 11125
-rect 1488 11105 1519 11111
-rect 1818 11108 1852 11114
-rect 2741 11104 2746 11145
+rect 1252 11655 1280 11661
+rect 1394 11654 1422 11661
+rect 1529 11655 1579 11661
+rect 1852 11654 1902 11660
+rect 1252 11613 1280 11619
+rect 1394 11612 1422 11619
+rect 1529 11613 1579 11619
+rect 1852 11612 1902 11618
+rect 1203 11583 1231 11589
+rect 1443 11583 1471 11589
+rect 1600 11583 1651 11589
+rect 1781 11588 1831 11594
+rect 1203 11541 1231 11547
+rect 1443 11541 1471 11547
+rect 1600 11541 1651 11547
+rect 1781 11546 1831 11552
+rect 1252 11480 1280 11486
+rect 1394 11479 1422 11486
+rect 1529 11480 1579 11486
+rect 1852 11479 1902 11485
+rect 1252 11438 1280 11444
+rect 1394 11437 1422 11444
+rect 1529 11438 1579 11444
+rect 1852 11437 1902 11443
+rect 1203 11408 1231 11414
+rect 1443 11408 1471 11414
+rect 1600 11408 1651 11414
+rect 1781 11413 1831 11419
+rect 1203 11366 1231 11372
+rect 1443 11366 1471 11372
+rect 1600 11366 1651 11372
+rect 1781 11371 1831 11377
+rect 1252 11305 1280 11311
+rect 1394 11304 1422 11311
+rect 1529 11305 1579 11311
+rect 4595 11310 4680 11388
+rect 1852 11304 1902 11310
+rect 4595 11305 4596 11310
+rect 2696 11277 2746 11283
+rect 2768 11277 2818 11283
+rect 4737 11277 4787 11283
+rect 4809 11277 4859 11283
+rect 5197 11281 5224 11287
+rect 1252 11263 1280 11269
+rect 1394 11262 1422 11269
+rect 1529 11263 1579 11269
+rect 1852 11262 1902 11268
+rect 1203 11233 1231 11239
+rect 1443 11233 1471 11239
+rect 1600 11233 1651 11239
+rect 1781 11238 1831 11244
+rect 2696 11235 2746 11241
+rect 2768 11235 2818 11241
+rect 4737 11235 4787 11241
+rect 4809 11235 4859 11241
+rect 5197 11239 5224 11245
+rect 5197 11214 5224 11220
+rect 1203 11191 1231 11197
+rect 1443 11191 1471 11197
+rect 1600 11191 1651 11197
+rect 1781 11196 1831 11202
+rect 1252 11130 1280 11136
+rect 1394 11129 1422 11136
+rect 1529 11130 1579 11136
+rect 1852 11129 1902 11135
 rect 2881 11133 2884 11183
 rect 2923 11133 2926 11183
 rect 3017 11133 3019 11183
 rect 3059 11133 3061 11183
-rect 4494 11133 4496 11183
-rect 4536 11133 4538 11183
-rect 4629 11133 4632 11183
-rect 4671 11133 4674 11183
-rect 5197 11169 5224 11176
-rect 4809 11121 4814 11145
-rect 5197 11129 5224 11136
-rect 4833 11104 4838 11121
-rect -943 11082 -916 11089
-rect 1296 11079 1301 11084
-rect 1242 11063 1270 11079
-rect 1384 11063 1412 11079
-rect 1519 11069 1569 11078
-rect 1736 11071 1753 11076
-rect 1852 11072 1902 11083
-rect 1909 11063 1926 11064
-rect 1193 11042 1221 11059
-rect 1433 11042 1461 11059
-rect 1590 11043 1641 11053
-rect 1781 11052 1831 11063
+rect 5197 11172 5224 11178
+rect 5197 11131 5224 11137
+rect 1252 11088 1280 11094
+rect 1394 11087 1422 11094
+rect 1529 11088 1579 11094
+rect 1852 11087 1902 11093
+rect 1203 11058 1231 11064
+rect 1443 11058 1471 11064
+rect 1600 11058 1651 11064
+rect 1781 11063 1831 11069
 rect 2881 11054 2884 11104
 rect 2923 11054 2926 11104
 rect 3017 11054 3019 11104
 rect 3059 11054 3061 11104
-rect 4494 11054 4496 11104
-rect 4536 11054 4538 11104
-rect 4629 11054 4632 11104
-rect 4671 11054 4674 11104
-rect 5197 11087 5224 11094
-rect 5197 11063 5224 11070
-rect 1909 11044 1926 11045
-rect 1654 11038 1673 11043
-rect -951 11018 -912 11021
-rect 1193 11000 1221 11017
-rect 1433 11000 1461 11017
-rect 1559 11011 1590 11017
-rect 1668 11011 1673 11038
-rect 1749 11021 1781 11026
-rect 5197 11021 5224 11028
-rect 1590 11001 1641 11011
-rect 1781 11010 1831 11021
-rect 7955 11011 7995 11022
-rect 8105 11011 8145 11022
-rect 5197 10981 5224 10988
-rect -951 10976 -912 10979
-rect 7955 10969 7995 10980
-rect 8105 10969 8145 10980
-rect 1193 10950 1221 10967
-rect 1433 10950 1461 10967
-rect 1590 10956 1641 10966
-rect 1559 10950 1590 10956
-rect 1668 10929 1673 10956
-rect 1781 10946 1831 10957
-rect 1749 10941 1781 10946
-rect 2106 10931 2156 10942
-rect 2286 10931 2336 10942
-rect 2426 10931 2476 10941
-rect -951 10922 -912 10925
-rect 1193 10908 1221 10925
-rect 1320 10907 1325 10912
-rect 1433 10908 1461 10925
-rect 1654 10924 1673 10929
-rect 1590 10914 1641 10924
-rect 1909 10922 1926 10923
-rect 1749 10915 1777 10920
-rect 2522 10919 2539 10921
-rect 1781 10904 1831 10915
-rect 1242 10888 1270 10904
-rect 1384 10888 1412 10904
-rect 1909 10903 1926 10904
-rect 2336 10900 2366 10904
-rect 1519 10889 1569 10898
-rect 1852 10884 1902 10895
-rect 2106 10889 2156 10900
-rect 2286 10889 2336 10900
-rect 2396 10899 2401 10904
-rect 2522 10900 2539 10902
-rect 2426 10889 2476 10899
-rect 2522 10885 2539 10887
-rect 2741 10884 2746 10925
+rect 5197 11089 5224 11095
+rect 5197 11064 5224 11070
+rect 1203 11016 1231 11022
+rect 1443 11016 1471 11022
+rect 1600 11016 1651 11022
+rect 1781 11021 1831 11027
+rect 5197 11022 5224 11028
+rect 7955 11024 7995 11030
+rect 8105 11024 8145 11030
+rect 5197 10981 5224 10987
+rect 7955 10982 7995 10988
+rect 8105 10982 8145 10988
+rect 2106 10964 2156 10969
+rect 2286 10964 2336 10970
+rect 2426 10964 2476 10969
+rect 1203 10955 1231 10961
+rect 1443 10955 1471 10961
+rect 1600 10955 1651 10961
+rect 7879 10958 7919 10963
+rect 8105 10956 8145 10963
+rect 1781 10950 1831 10956
+rect 2106 10922 2156 10927
+rect 2286 10922 2336 10928
+rect 2426 10922 2476 10927
+rect 1203 10913 1231 10919
+rect 1443 10913 1471 10919
+rect 1600 10913 1651 10919
+rect 1781 10908 1831 10914
+rect 2106 10897 2156 10903
+rect 2426 10897 2476 10903
 rect 2881 10901 2884 10951
 rect 2923 10901 2926 10951
 rect 3017 10901 3019 10951
 rect 3059 10901 3061 10951
-rect 4494 10901 4496 10951
-rect 4536 10901 4538 10951
-rect 4629 10901 4632 10951
-rect 4671 10901 4674 10951
-rect 7879 10950 7919 10960
-rect 8105 10948 8145 10960
-rect 5197 10939 5224 10946
-rect 4809 10901 4814 10925
-rect 5197 10915 5224 10922
-rect 7879 10908 7919 10918
-rect 8105 10906 8145 10918
-rect 4833 10884 4838 10901
-rect -951 10880 -912 10883
-rect 2106 10869 2156 10880
-rect 2372 10869 2377 10880
-rect 2426 10869 2476 10880
-rect 5197 10873 5224 10880
-rect 2396 10863 2401 10869
-rect 2522 10866 2539 10868
-rect 1242 10846 1270 10862
-rect 1384 10846 1412 10862
-rect 1488 10856 1519 10862
-rect 1519 10847 1569 10856
-rect 1818 10853 1852 10859
-rect 1852 10842 1902 10853
-rect 2078 10838 2106 10844
-rect 2156 10838 2184 10844
-rect 2396 10838 2426 10844
-rect -951 10826 -912 10829
-rect 2106 10827 2156 10838
-rect 2426 10827 2476 10838
+rect 5197 10939 5224 10945
+rect 5197 10914 5224 10920
+rect 7879 10916 7919 10921
+rect 8105 10914 8145 10921
+rect 1252 10883 1280 10889
+rect 1394 10883 1422 10890
+rect 1529 10883 1579 10889
+rect 1852 10884 1902 10890
+rect 5197 10872 5224 10878
+rect 2106 10855 2156 10861
+rect 2426 10855 2476 10861
+rect 1252 10841 1280 10847
+rect 1394 10841 1422 10848
+rect 1529 10841 1579 10847
+rect 1852 10842 1902 10848
 rect 2881 10822 2884 10872
 rect 2923 10822 2926 10872
 rect 3017 10822 3019 10872
 rect 3059 10822 3061 10872
-rect 4494 10822 4496 10872
-rect 4536 10822 4538 10872
-rect 4629 10822 4632 10872
-rect 4671 10822 4674 10872
-rect 7879 10849 7919 10859
-rect 8105 10849 8145 10861
-rect 5197 10833 5224 10840
-rect 1193 10795 1221 10812
-rect 1433 10795 1461 10812
-rect 1590 10801 1641 10811
-rect 7879 10807 7919 10817
-rect 8105 10807 8145 10819
-rect 1559 10795 1590 10801
-rect -951 10784 -912 10787
-rect 1668 10774 1673 10801
-rect 1781 10791 1831 10802
-rect 2760 10795 2769 10797
-rect 2820 10795 2852 10797
-rect 2884 10795 2923 10797
-rect 3019 10795 3059 10797
-rect 4496 10795 4536 10797
-rect 4632 10795 4671 10797
-rect 4703 10795 4735 10797
-rect 4786 10795 4795 10797
-rect 5197 10791 5224 10798
-rect 1749 10786 1781 10791
-rect 2106 10778 2156 10789
-rect 2426 10778 2476 10789
-rect 7955 10787 7995 10798
-rect 8105 10787 8145 10798
-rect 1193 10753 1221 10770
-rect 1320 10752 1325 10757
-rect 1433 10753 1461 10770
-rect 1654 10769 1673 10774
-rect 2078 10772 2106 10778
-rect 2156 10772 2184 10778
-rect 2396 10772 2426 10778
-rect 1590 10759 1641 10769
-rect 1909 10767 1926 10768
-rect 1749 10760 1777 10765
-rect 1781 10749 1831 10760
-rect 1242 10733 1270 10749
-rect 1384 10733 1412 10749
-rect 1909 10748 1926 10749
-rect 2396 10747 2401 10772
-rect 2696 10765 2746 10776
-rect 2768 10765 2818 10776
-rect 4737 10765 4787 10776
-rect 4809 10765 4859 10776
-rect 5197 10767 5224 10774
-rect 2818 10764 2852 10765
-rect 4703 10764 4737 10765
-rect 5376 10761 5400 10766
-rect 2522 10748 2539 10750
-rect 1519 10734 1569 10743
-rect 1852 10729 1902 10740
-rect 2106 10736 2156 10747
-rect 2372 10740 2377 10741
-rect 2360 10736 2377 10740
-rect 2426 10736 2476 10747
-rect 7955 10745 7995 10756
-rect 8105 10745 8145 10756
-rect 2522 10729 2539 10731
-rect 2106 10716 2156 10727
-rect 2286 10716 2336 10727
-rect 2426 10717 2476 10727
-rect 2696 10723 2746 10734
-rect 2768 10723 2818 10734
-rect 4737 10723 4787 10734
-rect 4809 10723 4859 10734
-rect 5197 10725 5224 10732
-rect 2522 10714 2539 10716
-rect 7955 10709 7995 10720
-rect 8105 10709 8145 10720
-rect 1242 10691 1270 10707
-rect 1384 10691 1412 10707
-rect 1488 10701 1519 10707
-rect 1519 10692 1569 10701
-rect 1818 10698 1852 10704
-rect 1852 10687 1902 10698
-rect 2522 10695 2539 10697
-rect 2106 10674 2156 10685
-rect 2286 10674 2336 10685
-rect 2426 10675 2476 10685
-rect 2697 10668 2747 10679
-rect 2769 10668 2819 10679
-rect 4737 10668 4787 10679
-rect 4809 10668 4859 10679
-rect 5197 10674 5224 10681
-rect 7955 10667 7995 10678
-rect 8105 10667 8145 10678
-rect 5400 10661 5417 10666
-rect 1193 10640 1221 10657
-rect 1433 10640 1461 10657
-rect 1590 10646 1641 10656
-rect 1559 10640 1590 10646
-rect 1668 10619 1673 10646
-rect 1781 10636 1831 10647
-rect 2106 10638 2156 10649
-rect 2286 10638 2336 10649
-rect 7879 10648 7919 10658
-rect 2426 10638 2476 10648
-rect 8105 10646 8145 10658
-rect 2819 10637 2853 10638
-rect 4703 10637 4737 10638
-rect 1749 10631 1781 10636
-rect 2522 10626 2539 10628
-rect 2697 10626 2747 10637
-rect 2769 10626 2819 10637
-rect 4737 10626 4787 10637
-rect 4809 10626 4859 10637
-rect 5197 10632 5224 10639
-rect 1193 10598 1221 10615
-rect 1320 10597 1325 10602
-rect 1433 10598 1461 10615
-rect 1654 10614 1673 10619
-rect 1590 10604 1641 10614
-rect 1909 10612 1926 10613
-rect 1749 10605 1777 10610
-rect 2336 10607 2366 10611
-rect 1781 10594 1831 10605
-rect 2106 10596 2156 10607
-rect 2286 10596 2336 10607
-rect 2396 10606 2401 10611
-rect 2522 10607 2539 10609
-rect 5197 10608 5224 10615
-rect 2426 10596 2476 10606
-rect 2761 10605 2770 10607
-rect 2821 10605 2853 10607
-rect 2885 10605 2924 10607
-rect 3020 10605 3060 10607
-rect 4496 10605 4536 10607
-rect 4632 10605 4671 10607
-rect 4703 10605 4735 10607
-rect 4786 10605 4795 10607
-rect 7879 10606 7919 10616
-rect 3058 10597 3060 10605
-rect 8105 10604 8145 10616
-rect 1242 10578 1270 10594
-rect 1384 10578 1412 10594
-rect 1909 10593 1926 10594
-rect 2522 10592 2539 10594
-rect 1519 10579 1569 10588
-rect 1852 10574 1902 10585
-rect 2106 10576 2156 10587
-rect 2372 10576 2377 10587
-rect 2426 10576 2476 10587
-rect 2396 10570 2401 10576
-rect 2522 10573 2539 10575
-rect 1242 10536 1270 10552
-rect 1384 10536 1412 10552
-rect 1488 10546 1519 10552
-rect 1519 10537 1569 10546
-rect 1818 10543 1852 10549
-rect 2078 10545 2106 10551
-rect 2156 10545 2184 10551
-rect 2396 10545 2426 10551
-rect 1852 10532 1902 10543
-rect 2106 10534 2156 10545
-rect 2426 10534 2476 10545
-rect 1193 10485 1221 10502
-rect 1433 10485 1461 10502
-rect 2742 10501 2747 10542
-rect 2882 10530 2885 10580
-rect 2924 10530 2927 10580
-rect 3018 10530 3020 10580
-rect 3060 10530 3062 10580
-rect 4494 10530 4496 10580
-rect 4536 10530 4538 10580
-rect 4629 10530 4632 10580
-rect 4671 10530 4674 10580
-rect 5197 10566 5224 10573
-rect 7879 10547 7919 10557
-rect 8105 10547 8145 10559
-rect 4809 10518 4814 10542
-rect 5197 10526 5224 10533
-rect 4833 10501 4838 10518
-rect 7879 10505 7919 10515
-rect 8105 10505 8145 10517
-rect 1590 10491 1641 10501
-rect 1559 10485 1590 10491
-rect 1668 10464 1673 10491
-rect 1781 10481 1831 10492
-rect 2106 10485 2156 10496
-rect 2426 10485 2476 10496
-rect 1749 10476 1781 10481
-rect 2078 10479 2106 10485
-rect 2156 10479 2184 10485
-rect 2396 10479 2426 10485
-rect 1193 10443 1221 10460
-rect 1320 10442 1325 10447
-rect 1433 10443 1461 10460
-rect 1654 10459 1673 10464
-rect 1590 10449 1641 10459
-rect 1909 10457 1926 10458
-rect 1749 10450 1777 10455
-rect 2396 10454 2401 10479
-rect 2522 10455 2539 10457
-rect 1781 10439 1831 10450
-rect 2106 10443 2156 10454
-rect 2372 10447 2377 10448
-rect 2360 10443 2377 10447
-rect 2426 10443 2476 10454
-rect 2882 10451 2885 10501
-rect 2924 10451 2927 10501
-rect 3018 10451 3020 10501
-rect 3060 10451 3062 10501
-rect 4494 10451 4496 10501
-rect 4536 10451 4538 10501
-rect 4629 10451 4632 10501
-rect 4671 10451 4674 10501
-rect 5197 10484 5224 10491
-rect 7955 10485 7995 10496
-rect 8105 10485 8145 10496
-rect 5197 10460 5224 10467
-rect 7955 10443 7995 10454
-rect 8105 10443 8145 10454
-rect 1242 10423 1270 10439
-rect 1384 10423 1412 10439
-rect 1909 10438 1926 10439
-rect 2522 10436 2539 10438
-rect 1519 10424 1569 10433
-rect 1852 10419 1902 10430
-rect 2106 10423 2156 10434
-rect 2286 10423 2336 10434
-rect 2426 10424 2476 10434
-rect 2522 10421 2539 10423
-rect 3480 10420 3497 10421
-rect 4059 10420 4076 10421
-rect 5197 10418 5224 10425
-rect 2522 10402 2539 10404
-rect 3480 10401 3497 10402
-rect 4059 10401 4076 10402
-rect 1242 10381 1270 10397
-rect 1384 10381 1412 10397
-rect 1488 10391 1519 10397
-rect 1519 10382 1569 10391
-rect 1818 10388 1852 10394
-rect 1852 10377 1902 10388
-rect 2106 10381 2156 10392
-rect 2286 10381 2336 10392
-rect 2426 10382 2476 10392
-rect 3480 10385 3497 10387
-rect 4059 10385 4076 10387
-rect 5197 10378 5224 10385
-rect 3481 10366 3498 10368
-rect 4059 10366 4076 10368
-rect 2742 10281 2747 10322
-rect 2882 10298 2885 10348
-rect 2924 10298 2927 10348
-rect 3018 10298 3020 10348
-rect 3060 10298 3062 10348
-rect 4494 10298 4496 10348
-rect 4536 10298 4538 10348
-rect 4629 10298 4632 10348
-rect 4671 10298 4674 10348
-rect 5197 10336 5224 10343
-rect 4809 10298 4814 10322
-rect 5197 10312 5224 10319
-rect 4833 10281 4838 10298
-rect 5197 10270 5224 10277
-rect 2882 10219 2885 10269
-rect 2924 10219 2927 10269
-rect 3018 10219 3020 10269
-rect 3060 10219 3062 10269
-rect 4494 10219 4496 10269
-rect 4536 10219 4538 10269
-rect 4629 10219 4632 10269
-rect 4671 10219 4674 10269
-rect 5197 10230 5224 10237
-rect 2761 10192 2770 10194
-rect 2821 10192 2853 10194
-rect 2885 10192 2924 10194
-rect 3020 10192 3060 10194
-rect 4496 10192 4536 10194
-rect 4632 10192 4671 10194
-rect 4703 10192 4735 10194
-rect 4786 10192 4795 10194
-rect 5197 10188 5224 10195
-rect 2697 10162 2747 10173
-rect 2769 10162 2819 10173
-rect 4737 10162 4787 10173
-rect 4809 10162 4859 10173
-rect 5197 10164 5224 10171
-rect 2819 10161 2853 10162
-rect 4703 10161 4737 10162
-rect 5376 10158 5400 10163
-rect 2697 10120 2747 10131
-rect 2769 10120 2819 10131
-rect 4737 10120 4787 10131
-rect 4809 10120 4859 10131
-rect 5197 10122 5224 10129
-rect 1193 9937 1221 9954
-rect 1433 9937 1461 9954
-rect 1590 9943 1641 9953
-rect 1559 9937 1590 9943
-rect 1668 9916 1673 9943
-rect 1781 9933 1831 9944
-rect 1749 9928 1781 9933
-rect 2106 9924 2156 9935
-rect 2286 9924 2336 9935
-rect 2426 9924 2476 9934
-rect 2841 9933 2891 9944
-rect 2913 9933 2963 9944
-rect 4597 9933 4647 9944
-rect 4669 9933 4719 9944
-rect 1193 9895 1221 9912
-rect 1320 9894 1325 9899
-rect 1433 9895 1461 9912
-rect 1654 9911 1673 9916
-rect 2522 9912 2539 9914
-rect 1590 9901 1641 9911
-rect 1909 9909 1926 9910
-rect 1749 9902 1777 9907
-rect 2963 9902 2995 9903
-rect 4565 9902 4597 9903
-rect 1781 9891 1831 9902
-rect 2336 9893 2366 9897
-rect 1242 9875 1270 9891
-rect 1384 9875 1412 9891
-rect 1909 9890 1926 9891
-rect 1519 9876 1569 9885
-rect 2106 9882 2156 9893
-rect 2286 9882 2336 9893
-rect 2396 9892 2401 9897
-rect 2522 9893 2539 9895
-rect 2426 9882 2476 9892
-rect 2841 9891 2891 9902
-rect 2913 9891 2963 9902
-rect 4597 9891 4647 9902
-rect 4669 9891 4719 9902
-rect 1852 9871 1902 9882
-rect 2522 9878 2539 9880
-rect 2106 9862 2156 9873
-rect 2372 9862 2377 9873
-rect 2426 9862 2476 9873
-rect 2913 9871 2963 9883
-rect 4597 9871 4647 9883
-rect 2396 9856 2401 9862
-rect 2522 9859 2539 9861
-rect 1242 9833 1270 9849
-rect 1384 9833 1412 9849
-rect 1488 9843 1519 9849
-rect 1519 9834 1569 9843
-rect 1818 9840 1852 9846
-rect 2882 9841 2886 9871
-rect 2963 9870 2992 9871
-rect 4568 9870 4597 9871
-rect 4674 9841 4678 9871
-rect 1852 9829 1902 9840
-rect 2078 9831 2106 9837
-rect 2156 9831 2184 9837
-rect 2396 9831 2426 9837
-rect 2106 9820 2156 9831
-rect 2426 9820 2476 9831
-rect 2913 9829 2963 9841
-rect 4597 9829 4647 9841
-rect 3088 9825 3105 9827
-rect 3482 9826 3499 9828
-rect 4061 9826 4078 9828
-rect 4455 9825 4472 9827
-rect 3088 9806 3105 9808
-rect 3482 9807 3499 9809
-rect 4061 9807 4078 9809
-rect 4455 9806 4472 9808
-rect 1193 9782 1221 9799
-rect 1433 9782 1461 9799
-rect 1590 9788 1641 9798
-rect 2913 9789 2963 9801
-rect 4597 9789 4647 9801
-rect 1559 9782 1590 9788
-rect 1668 9761 1673 9788
-rect 1781 9778 1831 9789
-rect 1749 9773 1781 9778
-rect 2106 9771 2156 9782
-rect 2426 9771 2476 9782
-rect 2078 9765 2106 9771
-rect 2156 9765 2184 9771
-rect 2396 9765 2426 9771
-rect 1193 9740 1221 9757
-rect 1320 9739 1325 9744
-rect 1433 9740 1461 9757
-rect 1654 9756 1673 9761
-rect 1590 9746 1641 9756
-rect 1909 9754 1926 9755
-rect 1749 9747 1777 9752
-rect 1781 9736 1831 9747
-rect 2396 9740 2401 9765
-rect 2882 9759 2886 9789
-rect 2963 9759 2992 9760
-rect 4568 9759 4597 9760
-rect 4674 9759 4678 9789
-rect 2913 9747 2963 9759
-rect 4597 9747 4647 9759
-rect 2522 9741 2539 9743
-rect 1242 9720 1270 9736
-rect 1384 9720 1412 9736
-rect 1909 9735 1926 9736
-rect 1519 9721 1569 9730
-rect 2106 9729 2156 9740
-rect 2372 9733 2377 9734
-rect 2360 9729 2377 9733
-rect 2426 9729 2476 9740
-rect 2841 9728 2891 9739
-rect 2913 9728 2963 9739
-rect 4597 9728 4647 9739
-rect 4669 9728 4719 9739
-rect 2963 9727 2995 9728
-rect 4565 9727 4597 9728
-rect 1852 9716 1902 9727
-rect 2522 9722 2539 9724
-rect 2106 9709 2156 9720
-rect 2286 9709 2336 9720
-rect 2426 9710 2476 9720
-rect 2522 9707 2539 9709
-rect 1242 9678 1270 9694
-rect 1384 9678 1412 9694
-rect 1488 9688 1519 9694
-rect 1519 9679 1569 9688
-rect 1818 9685 1852 9691
-rect 2522 9688 2539 9690
-rect 2841 9686 2891 9697
-rect 2913 9686 2963 9697
-rect 4597 9686 4647 9697
-rect 4669 9686 4719 9697
-rect 1852 9674 1902 9685
-rect 3481 9680 3498 9682
-rect 4062 9680 4079 9682
-rect 2106 9667 2156 9678
-rect 2286 9667 2336 9678
-rect 2426 9668 2476 9678
-rect 3088 9666 3105 9668
-rect 4455 9666 4472 9668
-rect 3481 9661 3498 9663
-rect 4062 9661 4079 9663
-rect 3088 9647 3105 9649
-rect 4455 9647 4472 9649
-rect 1193 9627 1221 9644
-rect 1433 9627 1461 9644
-rect 1590 9633 1641 9643
-rect 1559 9627 1590 9633
-rect 1668 9606 1673 9633
-rect 1781 9623 1831 9634
-rect 2106 9631 2156 9642
-rect 2286 9631 2336 9642
-rect 2426 9631 2476 9641
-rect 2841 9632 2891 9643
-rect 2913 9632 2963 9643
-rect 4597 9632 4647 9643
-rect 4669 9632 4719 9643
-rect 1749 9618 1781 9623
-rect 2522 9619 2539 9621
-rect 1193 9585 1221 9602
-rect 1320 9584 1325 9589
-rect 1433 9585 1461 9602
-rect 1654 9601 1673 9606
-rect 1590 9591 1641 9601
-rect 2336 9600 2366 9604
-rect 1909 9599 1926 9600
-rect 1749 9592 1777 9597
-rect 1781 9581 1831 9592
-rect 2106 9589 2156 9600
-rect 2286 9589 2336 9600
-rect 2396 9599 2401 9604
-rect 2522 9600 2539 9602
-rect 2963 9601 2995 9602
-rect 4565 9601 4597 9602
-rect 2426 9589 2476 9599
-rect 2841 9590 2891 9601
-rect 2913 9590 2963 9601
-rect 4597 9590 4647 9601
-rect 4669 9590 4719 9601
-rect 2522 9585 2539 9587
-rect 1242 9565 1270 9581
-rect 1384 9565 1412 9581
-rect 1909 9580 1926 9581
-rect 1519 9566 1569 9575
-rect 1852 9561 1902 9572
-rect 2106 9569 2156 9580
-rect 2372 9569 2377 9580
-rect 2426 9569 2476 9580
-rect 2913 9570 2963 9582
-rect 4597 9570 4647 9582
-rect 2396 9563 2401 9569
-rect 2522 9566 2539 9568
-rect 1242 9523 1270 9539
-rect 1384 9523 1412 9539
-rect 1488 9533 1519 9539
-rect 2078 9538 2106 9544
-rect 2156 9538 2184 9544
-rect 2396 9538 2426 9544
-rect 2882 9540 2886 9570
-rect 2963 9569 2992 9570
-rect 4568 9569 4597 9570
-rect 4674 9540 4678 9570
-rect 1519 9524 1569 9533
-rect 1818 9530 1852 9536
-rect 1852 9519 1902 9530
-rect 2106 9527 2156 9538
-rect 2426 9527 2476 9538
-rect 2913 9528 2963 9540
-rect 4597 9528 4647 9540
-rect 2913 9489 2963 9501
-rect 4597 9489 4647 9501
-rect 1193 9472 1221 9489
-rect 1433 9472 1461 9489
-rect 1590 9478 1641 9488
-rect 1559 9472 1590 9478
-rect 1668 9451 1673 9478
-rect 1781 9468 1831 9479
-rect 2106 9478 2156 9489
-rect 2426 9478 2476 9489
-rect 2078 9472 2106 9478
-rect 2156 9472 2184 9478
-rect 2396 9472 2426 9478
-rect 1749 9463 1781 9468
-rect 1193 9430 1221 9447
-rect 1320 9429 1325 9434
-rect 1433 9430 1461 9447
-rect 1654 9446 1673 9451
-rect 2396 9447 2401 9472
-rect 2882 9459 2886 9489
-rect 2963 9459 2992 9460
-rect 4568 9459 4597 9460
-rect 4674 9459 4678 9489
-rect 2522 9448 2539 9450
-rect 2913 9447 2963 9459
-rect 4597 9447 4647 9459
-rect 1590 9436 1641 9446
-rect 1909 9444 1926 9445
-rect 1749 9437 1777 9442
-rect 1781 9426 1831 9437
-rect 2106 9436 2156 9447
-rect 2372 9440 2377 9441
-rect 2360 9436 2377 9440
-rect 2426 9436 2476 9447
-rect 2522 9429 2539 9431
-rect 2841 9428 2891 9439
-rect 2913 9428 2963 9439
-rect 4597 9428 4647 9439
-rect 4669 9428 4719 9439
-rect 2963 9427 2995 9428
-rect 4565 9427 4597 9428
-rect 1242 9410 1270 9426
-rect 1384 9410 1412 9426
-rect 1909 9425 1926 9426
-rect 1519 9411 1569 9420
-rect 1852 9406 1902 9417
-rect 2106 9416 2156 9427
-rect 2286 9416 2336 9427
-rect 2426 9417 2476 9427
-rect 2522 9414 2539 9416
-rect 2522 9395 2539 9397
-rect 2841 9386 2891 9397
-rect 2913 9386 2963 9397
-rect 4597 9386 4647 9397
-rect 4669 9386 4719 9397
-rect 1242 9368 1270 9384
-rect 1384 9368 1412 9384
-rect 1488 9378 1519 9384
-rect 1519 9369 1569 9378
-rect 1818 9375 1852 9381
-rect 1852 9364 1902 9375
-rect 2106 9374 2156 9385
-rect 2286 9374 2336 9385
-rect 2426 9375 2476 9385
-rect 1193 8960 1221 8977
-rect 1433 8960 1461 8977
-rect 1590 8966 1641 8976
-rect 1559 8960 1590 8966
-rect 1668 8939 1673 8966
-rect 1781 8956 1831 8967
-rect 1749 8951 1781 8956
-rect 2106 8948 2156 8959
-rect 2286 8948 2336 8959
-rect 2426 8948 2476 8958
-rect 2841 8955 2891 8966
-rect 2913 8955 2963 8966
-rect 1193 8918 1221 8935
-rect 1320 8917 1325 8922
-rect 1433 8918 1461 8935
-rect 1654 8934 1673 8939
-rect 2522 8936 2539 8938
-rect 1590 8924 1641 8934
-rect 1909 8932 1926 8933
-rect 1749 8925 1777 8930
-rect 1781 8914 1831 8925
-rect 2963 8924 2995 8925
-rect 2336 8917 2366 8921
-rect 1242 8898 1270 8914
-rect 1384 8898 1412 8914
-rect 1909 8913 1926 8914
-rect 1519 8899 1569 8908
-rect 2106 8906 2156 8917
-rect 2286 8906 2336 8917
-rect 2396 8916 2401 8921
-rect 2522 8917 2539 8919
-rect 2426 8906 2476 8916
-rect 2841 8913 2891 8924
-rect 2913 8913 2963 8924
-rect 1852 8894 1902 8905
-rect 2522 8902 2539 8904
-rect 2106 8886 2156 8897
-rect 2372 8886 2377 8897
-rect 2426 8886 2476 8897
-rect 2913 8893 2963 8905
-rect 2396 8880 2401 8886
-rect 2522 8883 2539 8885
-rect 1242 8856 1270 8872
-rect 1384 8856 1412 8872
-rect 1488 8866 1519 8872
-rect 1519 8857 1569 8866
-rect 1818 8863 1852 8869
-rect 2882 8863 2886 8893
-rect 2963 8892 2992 8893
-rect 1852 8852 1902 8863
-rect 2078 8855 2106 8861
-rect 2156 8855 2184 8861
-rect 2396 8855 2426 8861
-rect 2106 8844 2156 8855
-rect 2426 8844 2476 8855
-rect 2913 8851 2963 8863
-rect 3503 8848 3520 8850
-rect 3101 8845 3118 8847
-rect 3503 8829 3520 8831
-rect 3101 8826 3118 8828
-rect 1193 8805 1221 8822
-rect 1433 8805 1461 8822
-rect 1590 8811 1641 8821
-rect 1559 8805 1590 8811
-rect 1668 8784 1673 8811
-rect 1781 8801 1831 8812
-rect 2913 8811 2963 8823
-rect 1749 8796 1781 8801
-rect 2106 8795 2156 8806
-rect 2426 8795 2476 8806
-rect 2078 8789 2106 8795
-rect 2156 8789 2184 8795
-rect 2396 8789 2426 8795
-rect 1193 8763 1221 8780
-rect 1320 8762 1325 8767
-rect 1433 8763 1461 8780
-rect 1654 8779 1673 8784
-rect 1590 8769 1641 8779
-rect 1909 8777 1926 8778
-rect 1749 8770 1777 8775
-rect 1781 8759 1831 8770
-rect 2396 8764 2401 8789
-rect 2882 8781 2886 8811
-rect 2963 8781 2992 8782
-rect 2913 8769 2963 8781
-rect 2522 8765 2539 8767
-rect 1242 8743 1270 8759
-rect 1384 8743 1412 8759
-rect 1909 8758 1926 8759
-rect 2106 8753 2156 8764
-rect 2372 8757 2377 8758
-rect 2360 8753 2377 8757
-rect 2426 8753 2476 8764
-rect 1519 8744 1569 8753
-rect 2841 8750 2891 8761
-rect 2913 8750 2963 8761
-rect 1852 8739 1902 8750
-rect 2963 8749 2995 8750
-rect 2522 8746 2539 8748
-rect 2106 8733 2156 8744
-rect 2286 8733 2336 8744
-rect 2426 8734 2476 8744
-rect 2522 8731 2539 8733
-rect 3100 8727 3117 8729
-rect 3502 8721 3519 8723
-rect 1242 8701 1270 8717
-rect 1384 8701 1412 8717
-rect 1488 8711 1519 8717
-rect 1519 8702 1569 8711
-rect 1818 8708 1852 8714
-rect 2522 8712 2539 8714
-rect 2841 8708 2891 8719
-rect 2913 8708 2963 8719
-rect 3100 8708 3117 8710
-rect 1852 8697 1902 8708
-rect 3502 8702 3519 8704
-rect 2106 8691 2156 8702
-rect 2286 8691 2336 8702
-rect 2426 8692 2476 8702
-rect 3100 8693 3117 8695
-rect 3502 8687 3519 8689
-rect 3100 8674 3117 8676
-rect 3502 8668 3519 8670
-rect 1193 8650 1221 8667
-rect 1433 8650 1461 8667
-rect 1590 8656 1641 8666
-rect 1559 8650 1590 8656
-rect 1668 8629 1673 8656
-rect 1781 8646 1831 8657
-rect 2106 8655 2156 8666
-rect 2286 8655 2336 8666
-rect 2426 8655 2476 8665
-rect 2841 8654 2891 8665
-rect 2913 8654 2963 8665
-rect 3100 8659 3117 8661
-rect 3502 8653 3519 8655
-rect 1749 8641 1781 8646
-rect 2522 8643 2539 8645
-rect 3100 8640 3117 8642
-rect 3502 8634 3519 8636
-rect 1193 8608 1221 8625
-rect 1320 8607 1325 8612
-rect 1433 8608 1461 8625
-rect 1654 8624 1673 8629
-rect 2336 8624 2366 8628
-rect 1590 8614 1641 8624
-rect 1909 8622 1926 8623
-rect 1749 8615 1777 8620
-rect 1781 8604 1831 8615
-rect 2106 8613 2156 8624
-rect 2286 8613 2336 8624
-rect 2396 8623 2401 8628
-rect 2522 8624 2539 8626
-rect 2963 8623 2995 8624
-rect 2426 8613 2476 8623
-rect 2841 8612 2891 8623
-rect 2913 8612 2963 8623
-rect 3502 8619 3519 8621
-rect 2522 8609 2539 8611
-rect 1242 8588 1270 8604
-rect 1384 8588 1412 8604
-rect 1909 8603 1926 8604
-rect 1519 8589 1569 8598
-rect 1852 8584 1902 8595
-rect 2106 8593 2156 8604
-rect 2372 8593 2377 8604
-rect 2426 8593 2476 8604
-rect 2396 8587 2401 8593
-rect 2913 8592 2963 8604
-rect 2522 8590 2539 8592
-rect 2078 8562 2106 8568
-rect 2156 8562 2184 8568
-rect 2396 8562 2426 8568
-rect 2882 8562 2886 8592
-rect 2963 8591 2992 8592
-rect 1242 8546 1270 8562
-rect 1384 8546 1412 8562
-rect 1488 8556 1519 8562
-rect 1519 8547 1569 8556
-rect 1818 8553 1852 8559
-rect 1852 8542 1902 8553
-rect 2106 8551 2156 8562
-rect 2426 8551 2476 8562
-rect 2913 8550 2963 8562
-rect 1193 8495 1221 8512
-rect 1433 8495 1461 8512
-rect 1590 8501 1641 8511
-rect 2106 8502 2156 8513
-rect 2426 8502 2476 8513
-rect 2913 8511 2963 8523
-rect 1559 8495 1590 8501
-rect 1668 8474 1673 8501
-rect 1781 8491 1831 8502
-rect 2078 8496 2106 8502
-rect 2156 8496 2184 8502
-rect 2396 8496 2426 8502
-rect 1749 8486 1781 8491
-rect 1193 8453 1221 8470
-rect 1320 8452 1325 8457
-rect 1433 8453 1461 8470
-rect 1654 8469 1673 8474
-rect 2396 8471 2401 8496
-rect 2882 8481 2886 8511
-rect 2963 8481 2992 8482
-rect 2522 8472 2539 8474
-rect 1590 8459 1641 8469
-rect 1909 8467 1926 8468
-rect 1749 8460 1777 8465
-rect 2106 8460 2156 8471
-rect 2372 8464 2377 8465
-rect 2360 8460 2377 8464
-rect 2426 8460 2476 8471
-rect 2913 8469 2963 8481
-rect 1781 8449 1831 8460
-rect 2522 8453 2539 8455
-rect 1242 8433 1270 8449
-rect 1384 8433 1412 8449
-rect 1909 8448 1926 8449
-rect 1519 8434 1569 8443
-rect 2106 8440 2156 8451
-rect 2286 8440 2336 8451
-rect 2426 8441 2476 8451
-rect 2841 8450 2891 8461
-rect 2913 8450 2963 8461
-rect 2963 8449 2995 8450
-rect 1852 8429 1902 8440
-rect 2522 8438 2539 8440
-rect 2522 8419 2539 8421
-rect 1242 8391 1270 8407
-rect 1384 8391 1412 8407
-rect 1488 8401 1519 8407
-rect 1519 8392 1569 8401
-rect 1818 8398 1852 8404
-rect 2106 8398 2156 8409
-rect 2286 8398 2336 8409
-rect 2426 8399 2476 8409
-rect 2841 8408 2891 8419
-rect 2913 8408 2963 8419
-rect 1852 8387 1902 8398
+rect 7879 10854 7919 10859
+rect 8105 10854 8145 10861
+rect 5197 10831 5224 10837
+rect 7879 10812 7919 10817
+rect 8105 10812 8145 10819
+rect 2106 10794 2156 10800
+rect 2426 10794 2476 10800
+rect 5197 10789 5224 10795
+rect 7955 10787 7995 10793
+rect 8105 10787 8145 10793
+rect 1203 10780 1231 10786
+rect 1443 10780 1471 10786
+rect 1600 10780 1651 10786
+rect 1781 10775 1831 10781
+rect 2696 10764 2746 10770
+rect 2768 10764 2818 10770
+rect 2106 10752 2156 10758
+rect 2426 10752 2476 10758
+rect 1203 10738 1231 10744
+rect 1443 10738 1471 10744
+rect 1600 10738 1651 10744
+rect 1781 10733 1831 10739
+rect 2106 10728 2156 10733
+rect 2286 10727 2336 10733
+rect 2426 10728 2476 10733
+rect 2696 10722 2746 10728
+rect 2768 10722 2818 10728
+rect 1252 10708 1280 10714
+rect 1394 10708 1422 10715
+rect 1529 10708 1579 10714
+rect 1852 10709 1902 10715
+rect 4595 10702 4596 10785
+rect 4737 10764 4787 10770
+rect 4809 10764 4859 10770
+rect 5197 10764 5224 10770
+rect 7955 10745 7995 10751
+rect 8105 10745 8145 10751
+rect 4737 10722 4787 10728
+rect 4809 10722 4859 10728
+rect 5197 10722 5224 10728
+rect 7955 10704 7995 10710
+rect 8105 10704 8145 10710
+rect 2106 10686 2156 10691
+rect 2286 10685 2336 10691
+rect 2426 10686 2476 10691
+rect 2697 10674 2747 10680
+rect 2769 10674 2819 10680
+rect 4737 10674 4787 10680
+rect 4809 10674 4859 10680
+rect 5197 10678 5224 10684
+rect 1252 10666 1280 10672
+rect 1394 10666 1422 10673
+rect 1529 10666 1579 10672
+rect 1852 10667 1902 10673
+rect 7955 10662 7995 10668
+rect 8105 10662 8145 10668
+rect 2106 10644 2156 10649
+rect 2286 10644 2336 10650
+rect 2426 10644 2476 10649
+rect 2697 10632 2747 10638
+rect 2769 10632 2819 10638
+rect 4737 10632 4787 10638
+rect 4809 10632 4859 10638
+rect 5197 10636 5224 10642
+rect 7879 10638 7919 10643
+rect 8105 10636 8145 10643
+rect 5197 10611 5224 10617
+rect 1203 10605 1231 10611
+rect 1443 10605 1471 10611
+rect 1600 10605 1651 10611
+rect 1781 10600 1831 10606
+rect 2106 10602 2156 10607
+rect 2286 10602 2336 10608
+rect 2426 10602 2476 10607
+rect 7879 10596 7919 10601
+rect 8105 10594 8145 10601
+rect 2106 10577 2156 10583
+rect 2426 10577 2476 10583
+rect 5197 10569 5224 10575
+rect 1203 10563 1231 10569
+rect 1443 10563 1471 10569
+rect 1600 10563 1651 10569
+rect 1781 10558 1831 10564
+rect 1252 10533 1280 10539
+rect 1394 10533 1422 10540
+rect 1529 10533 1579 10539
+rect 1852 10534 1902 10540
+rect 2106 10535 2156 10541
+rect 2426 10535 2476 10541
+rect 7879 10534 7919 10539
+rect 8105 10534 8145 10541
+rect 5197 10528 5224 10534
+rect 1252 10491 1280 10497
+rect 1394 10491 1422 10498
+rect 1529 10491 1579 10497
+rect 1852 10492 1902 10498
+rect 7879 10492 7919 10497
+rect 8105 10492 8145 10499
+rect 5197 10486 5224 10492
+rect 2106 10474 2156 10480
+rect 2426 10474 2476 10480
+rect 7955 10467 7995 10473
+rect 8105 10467 8145 10473
+rect 5197 10461 5224 10467
+rect 1203 10430 1231 10436
+rect 1443 10430 1471 10436
+rect 1600 10430 1651 10436
+rect 2106 10432 2156 10438
+rect 2426 10432 2476 10438
+rect 1781 10425 1831 10431
+rect 7955 10425 7995 10431
+rect 8105 10425 8145 10431
+rect 5197 10419 5224 10425
+rect 2106 10408 2156 10413
+rect 2286 10407 2336 10413
+rect 2426 10408 2476 10413
+rect 1203 10388 1231 10394
+rect 1443 10388 1471 10394
+rect 1600 10388 1651 10394
+rect 1781 10383 1831 10389
+rect 5197 10378 5224 10384
+rect 2106 10366 2156 10371
+rect 2286 10365 2336 10371
+rect 2426 10366 2476 10371
+rect 1252 10358 1280 10364
+rect 1394 10358 1422 10365
+rect 1529 10358 1579 10364
+rect 1852 10359 1902 10365
+rect 5197 10336 5224 10342
+rect 1252 10316 1280 10322
+rect 1394 10316 1422 10323
+rect 1529 10316 1579 10322
+rect 1852 10317 1902 10323
+rect 5197 10311 5224 10317
+rect 5197 10269 5224 10275
+rect 5197 10228 5224 10234
+rect 5197 10186 5224 10192
+rect 2697 10161 2747 10167
+rect 2769 10161 2819 10167
+rect 4737 10161 4787 10167
+rect 4809 10161 4859 10167
+rect 5197 10161 5224 10167
+rect 2697 10119 2747 10125
+rect 2769 10119 2819 10125
+rect 4737 10119 4787 10125
+rect 4809 10119 4859 10125
+rect 5197 10119 5224 10125
+rect 1203 9942 1231 9948
+rect 1443 9942 1471 9948
+rect 1600 9942 1651 9948
+rect 1781 9937 1831 9943
+rect 2104 9917 2154 9922
+rect 2284 9917 2334 9923
+rect 2424 9917 2474 9922
+rect 2838 9916 2888 9922
+rect 2910 9916 2960 9922
+rect 4594 9916 4644 9922
+rect 4666 9916 4716 9922
+rect 1203 9900 1231 9906
+rect 1443 9900 1471 9906
+rect 1600 9900 1651 9906
+rect 1781 9895 1831 9901
+rect 1252 9870 1280 9876
+rect 1394 9870 1422 9877
+rect 1529 9870 1579 9876
+rect 1852 9871 1902 9877
+rect 2104 9875 2154 9880
+rect 2284 9875 2334 9881
+rect 2424 9875 2474 9880
+rect 2838 9874 2888 9880
+rect 2910 9874 2960 9880
+rect 4594 9874 4644 9880
+rect 4666 9874 4716 9880
+rect 2104 9850 2154 9856
+rect 2424 9850 2474 9856
+rect 2910 9847 2960 9853
+rect 4594 9847 4644 9853
+rect 1252 9828 1280 9834
+rect 1394 9828 1422 9835
+rect 1529 9828 1579 9834
+rect 1852 9829 1902 9835
+rect 2104 9808 2154 9814
+rect 2424 9808 2474 9814
+rect 2910 9805 2960 9811
+rect 4594 9805 4644 9811
+rect 1203 9767 1231 9773
+rect 1443 9767 1471 9773
+rect 1600 9767 1651 9773
+rect 1781 9762 1831 9768
+rect 2910 9762 2960 9768
+rect 4594 9762 4644 9768
+rect 2104 9747 2154 9753
+rect 2424 9747 2474 9753
+rect 1203 9725 1231 9731
+rect 1443 9725 1471 9731
+rect 1600 9725 1651 9731
+rect 1781 9720 1831 9726
+rect 2910 9720 2960 9726
+rect 4594 9720 4644 9726
+rect 2104 9705 2154 9711
+rect 2424 9705 2474 9711
+rect 1252 9695 1280 9701
+rect 1394 9695 1422 9702
+rect 1529 9695 1579 9701
+rect 1852 9696 1902 9702
+rect 2838 9693 2888 9699
+rect 2910 9693 2960 9699
+rect 4594 9693 4644 9699
+rect 4666 9693 4716 9699
+rect 2104 9681 2154 9686
+rect 2284 9680 2334 9686
+rect 2424 9681 2474 9686
+rect 1252 9653 1280 9659
+rect 1394 9653 1422 9660
+rect 1529 9653 1579 9659
+rect 1852 9654 1902 9660
+rect 2838 9651 2888 9657
+rect 2910 9651 2960 9657
+rect 4594 9651 4644 9657
+rect 4666 9651 4716 9657
+rect 2104 9639 2154 9644
+rect 2284 9638 2334 9644
+rect 2424 9639 2474 9644
+rect 1203 9592 1231 9598
+rect 1443 9592 1471 9598
+rect 1600 9592 1651 9598
+rect 2104 9597 2154 9602
+rect 2284 9597 2334 9603
+rect 2424 9597 2474 9602
+rect 1781 9587 1831 9593
+rect 2838 9592 2888 9598
+rect 2910 9592 2960 9598
+rect 4594 9592 4644 9598
+rect 4666 9592 4716 9598
+rect 1203 9550 1231 9556
+rect 1443 9550 1471 9556
+rect 1600 9550 1651 9556
+rect 2104 9555 2154 9560
+rect 2284 9555 2334 9561
+rect 2424 9555 2474 9560
+rect 1781 9545 1831 9551
+rect 2838 9550 2888 9556
+rect 2910 9550 2960 9556
+rect 4594 9550 4644 9556
+rect 4666 9550 4716 9556
+rect 2104 9530 2154 9536
+rect 2424 9530 2474 9536
+rect 1252 9520 1280 9526
+rect 1394 9520 1422 9527
+rect 1529 9520 1579 9526
+rect 1852 9521 1902 9527
+rect 2910 9523 2960 9529
+rect 4594 9523 4644 9529
+rect 2104 9488 2154 9494
+rect 2424 9488 2474 9494
+rect 1252 9478 1280 9484
+rect 1394 9478 1422 9485
+rect 1529 9478 1579 9484
+rect 1852 9479 1902 9485
+rect 2910 9481 2960 9487
+rect 4594 9481 4644 9487
+rect 2910 9439 2960 9445
+rect 4594 9439 4644 9445
+rect 2104 9427 2154 9433
+rect 2424 9427 2474 9433
+rect 1203 9417 1231 9423
+rect 1443 9417 1471 9423
+rect 1600 9417 1651 9423
+rect 1781 9412 1831 9418
+rect 2910 9397 2960 9403
+rect 4594 9397 4644 9403
+rect 2104 9385 2154 9391
+rect 2424 9385 2474 9391
+rect 1203 9375 1231 9381
+rect 1443 9375 1471 9381
+rect 1600 9375 1651 9381
+rect 1781 9370 1831 9376
+rect 2838 9370 2888 9376
+rect 2910 9370 2960 9376
+rect 4594 9370 4644 9376
+rect 4666 9370 4716 9376
+rect 2104 9361 2154 9366
+rect 2284 9360 2334 9366
+rect 2424 9361 2474 9366
+rect 1252 9345 1280 9351
+rect 1394 9345 1422 9352
+rect 1529 9345 1579 9351
+rect 1852 9346 1902 9352
+rect 2838 9328 2888 9334
+rect 2910 9328 2960 9334
+rect 4594 9328 4644 9334
+rect 4666 9328 4716 9334
+rect 2104 9319 2154 9324
+rect 2284 9318 2334 9324
+rect 2424 9319 2474 9324
+rect 1252 9303 1280 9309
+rect 1394 9303 1422 9310
+rect 1529 9303 1579 9309
+rect 1852 9304 1902 9310
+rect 1199 9036 1227 9042
+rect 1439 9036 1467 9042
+rect 1596 9036 1647 9042
+rect 1777 9031 1827 9037
+rect 1199 8994 1227 9000
+rect 1439 8994 1467 9000
+rect 1596 8994 1647 9000
+rect 1777 8989 1827 8995
+rect 2107 8990 2157 8995
+rect 2287 8990 2337 8996
+rect 2427 8990 2477 8995
+rect 2841 8983 2891 8989
+rect 2913 8983 2963 8989
+rect 1248 8964 1276 8970
+rect 1390 8964 1418 8971
+rect 1525 8964 1575 8970
+rect 1848 8965 1898 8971
+rect 2107 8948 2157 8953
+rect 2287 8948 2337 8954
+rect 2427 8948 2477 8953
+rect 2841 8941 2891 8947
+rect 2913 8941 2963 8947
+rect 1248 8922 1276 8928
+rect 1390 8922 1418 8929
+rect 1525 8922 1575 8928
+rect 1848 8923 1898 8929
+rect 2107 8923 2157 8929
+rect 2427 8923 2477 8929
+rect 2913 8914 2963 8920
+rect 2107 8881 2157 8887
+rect 2427 8881 2477 8887
+rect 2913 8872 2963 8878
+rect 1199 8861 1227 8867
+rect 1439 8861 1467 8867
+rect 1596 8861 1647 8867
+rect 1777 8856 1827 8862
+rect 2913 8831 2963 8837
+rect 1199 8819 1227 8825
+rect 1439 8819 1467 8825
+rect 1596 8819 1647 8825
+rect 2107 8820 2157 8826
+rect 2427 8820 2477 8826
+rect 1777 8814 1827 8820
+rect 1248 8789 1276 8795
+rect 1390 8789 1418 8796
+rect 1525 8789 1575 8795
+rect 1848 8790 1898 8796
+rect 2913 8789 2963 8795
+rect 2107 8778 2157 8784
+rect 2427 8778 2477 8784
+rect 2841 8762 2891 8768
+rect 2913 8762 2963 8768
+rect 2107 8754 2157 8759
+rect 1248 8747 1276 8753
+rect 1390 8747 1418 8754
+rect 1525 8747 1575 8753
+rect 1848 8748 1898 8754
+rect 2287 8753 2337 8759
+rect 2427 8754 2477 8759
+rect 2841 8720 2891 8726
+rect 2913 8720 2963 8726
+rect 2107 8712 2157 8717
+rect 2287 8711 2337 8717
+rect 2427 8712 2477 8717
+rect 1199 8686 1227 8692
+rect 1439 8686 1467 8692
+rect 1596 8686 1647 8692
+rect 1777 8681 1827 8687
+rect 2107 8670 2157 8675
+rect 2287 8670 2337 8676
+rect 2427 8670 2477 8675
+rect 2841 8659 2891 8665
+rect 2913 8659 2963 8665
+rect 1199 8644 1227 8650
+rect 1439 8644 1467 8650
+rect 1596 8644 1647 8650
+rect 1777 8639 1827 8645
+rect 2107 8628 2157 8633
+rect 2287 8628 2337 8634
+rect 2427 8628 2477 8633
+rect 1248 8614 1276 8620
+rect 1390 8614 1418 8621
+rect 1525 8614 1575 8620
+rect 1848 8615 1898 8621
+rect 2841 8617 2891 8623
+rect 2913 8617 2963 8623
+rect 2107 8603 2157 8609
+rect 2427 8603 2477 8609
+rect 2913 8590 2963 8596
+rect 1248 8572 1276 8578
+rect 1390 8572 1418 8579
+rect 1525 8572 1575 8578
+rect 1848 8573 1898 8579
+rect 2107 8561 2157 8567
+rect 2427 8561 2477 8567
+rect 2913 8548 2963 8554
+rect 1199 8511 1227 8517
+rect 1439 8511 1467 8517
+rect 1596 8511 1647 8517
+rect 1777 8506 1827 8512
+rect 2913 8506 2963 8512
+rect 2107 8500 2157 8506
+rect 2427 8500 2477 8506
+rect 1199 8469 1227 8475
+rect 1439 8469 1467 8475
+rect 1596 8469 1647 8475
+rect 1777 8464 1827 8470
+rect 2913 8464 2963 8470
+rect 2107 8458 2157 8464
+rect 2427 8458 2477 8464
+rect 1248 8439 1276 8445
+rect 1390 8439 1418 8446
+rect 1525 8439 1575 8445
+rect 1848 8440 1898 8446
+rect 2107 8434 2157 8439
+rect 2287 8433 2337 8439
+rect 2427 8434 2477 8439
+rect 2841 8437 2891 8443
+rect 2913 8437 2963 8443
+rect 1248 8397 1276 8403
+rect 1390 8397 1418 8404
+rect 1525 8397 1575 8403
+rect 1848 8398 1898 8404
+rect 2107 8392 2157 8397
+rect 2287 8391 2337 8397
+rect 2427 8392 2477 8397
+rect 2841 8395 2891 8401
+rect 2913 8395 2963 8401
 rect 7469 7523 7472 7562
 rect 7511 7523 7514 7562
 rect 7565 7523 7568 7562
@@ -1238,8 +747,6 @@
 rect 7895 7200 7898 7239
 rect 7949 7201 7952 7240
 rect 7991 7201 7994 7240
-rect 8041 7134 8045 7166
-rect 8055 7120 8059 7180
 rect 7469 7040 7472 7079
 rect 7511 7040 7514 7079
 rect 7565 7039 7568 7078
@@ -1252,9 +759,6 @@
 rect 7895 7039 7898 7078
 rect 7949 7040 7952 7079
 rect 7991 7040 7994 7079
-rect 7571 7012 7607 7017
-rect 8041 6973 8045 7005
-rect 8055 6959 8059 7019
 rect 7469 6879 7472 6918
 rect 7511 6879 7514 6918
 rect 7565 6878 7568 6917
@@ -1268,8 +772,6 @@
 rect 7949 6879 7952 6918
 rect 7991 6879 7994 6918
 rect 7737 6828 7741 6829
-rect 8040 6812 8044 6844
-rect 8054 6798 8058 6858
 rect 7469 6718 7472 6757
 rect 7511 6718 7514 6757
 rect 7565 6717 7568 6756
@@ -1282,8 +784,6 @@
 rect 7895 6717 7898 6756
 rect 7949 6718 7952 6757
 rect 7991 6718 7994 6757
-rect 8040 6650 8045 6682
-rect 8054 6636 8059 6696
 rect 7469 6557 7472 6596
 rect 7511 6557 7514 6596
 rect 7565 6556 7568 6595
@@ -1296,8 +796,6 @@
 rect 7895 6556 7898 6595
 rect 7949 6557 7952 6596
 rect 7991 6557 7994 6596
-rect 8040 6489 8044 6521
-rect 8054 6475 8058 6535
 rect 7469 6396 7472 6435
 rect 7511 6396 7514 6435
 rect 7565 6395 7568 6434
@@ -1322,8 +820,6 @@
 rect 7895 6234 7898 6273
 rect 7949 6235 7952 6274
 rect 7991 6235 7994 6274
-rect 8041 6169 8044 6201
-rect 8055 6155 8058 6215
 rect 7469 6074 7472 6113
 rect 7511 6074 7514 6113
 rect 7565 6074 7568 6113
@@ -1336,6 +832,8 @@
 rect 7895 6074 7898 6113
 rect 7949 6074 7952 6113
 rect 7991 6074 7994 6113
+<< nwell >>
+rect -14876 -21561 -14873 -21516
 << metal1 >>
 rect -13106 14454 -12717 14571
 rect -10247 14453 -9858 14570
@@ -1883,22 +1381,22 @@
 rect 10049 -23816 10253 -23650
 rect -15053 -24304 -14913 -24107
 rect -14423 -24337 -14283 -23971
-use sky130_hilas_TopProtection  sky130_hilas_TopProtection_0
-timestamp 1627737364
-transform 1 0 -13875 0 1 13286
-box -2 -76 34131 1170
-use sky130_hilas_LeftProtection  sky130_hilas_LeftProtection_0
-timestamp 1627737364
-transform 1 0 -13278 0 1 -15672
-box -2065 -8439 -833 28728
-use sky130_hilas_RightProtection  sky130_hilas_RightProtection_0
-timestamp 1627737364
-transform 1 0 22518 0 1 -15744
-box -2054 8715 -826 28728
 use sky130_hilas_TopLevelTextStructure  sky130_hilas_TopLevelTextStructure_0
-timestamp 1627744303
+timestamp 1629420194
 transform 1 0 -2990 0 1 6624
 box 218 -793 13243 6785
+use sky130_hilas_RightProtection  sky130_hilas_RightProtection_0
+timestamp 1629421669
+transform 1 0 22518 0 1 -15744
+box -2054 8715 -826 28728
+use sky130_hilas_LeftProtection  sky130_hilas_LeftProtection_0
+timestamp 1629421669
+transform 1 0 -13278 0 1 -15672
+box -2065 -8439 -833 28728
+use sky130_hilas_TopProtection  sky130_hilas_TopProtection_0
+timestamp 1629421669
+transform 1 0 -13875 0 1 13286
+box -2 -76 34131 1170
 << labels >>
 rlabel metal1 21692 -6258 21817 -5869 0 IO07
 port 1 nsew

diff --git a/mag/sky130_hilas_TopProtection.mag b/mag/sky130_hilas_TopProtection.mag
index bb4ce38..d8baff4 100644
--- a/mag/sky130_hilas_TopProtection.mag
+++ b/mag/sky130_hilas_TopProtection.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1627737364
+timestamp 1629421669
 << metal1 >>
 rect 769 1088 1158 1168
 rect 3628 1088 4017 1168
@@ -25,15 +25,15 @@
 rect 29666 -76 30061 1
 rect 32525 -76 32920 1
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_1
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 3602 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_0
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 743 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_2
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 6461 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_polyresistorGND  sky130_hilas_polyresistorGND_0
@@ -41,31 +41,31 @@
 transform 1 0 11320 0 1 58
 box -2749 -57 2798 1032
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_3
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 14863 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_4
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 17722 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_5
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 20581 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_6
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 23440 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_9
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 26299 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_7
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 29158 0 1 230
 box -745 -229 2114 858
 use sky130_hilas_VinjDiodeProtect01  sky130_hilas_VinjDiodeProtect01_8
-timestamp 1627735001
+timestamp 1629421669
 transform 1 0 32017 0 1 230
 box -745 -229 2114 858
 << labels >>

diff --git a/mag/sky130_hilas_Trans2med.mag b/mag/sky130_hilas_Trans2med.mag
index 10b7e6e..067da62 100644
--- a/mag/sky130_hilas_Trans2med.mag
+++ b/mag/sky130_hilas_Trans2med.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -83 185 -27 382
 << psubdiff >>
@@ -90,75 +90,75 @@
 rect -380 -119 -181 -97
 rect -96 -116 -27 -95
 use sky130_hilas_nFETmed  sky130_hilas_nFETmed_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -290 0 1 -99
 box -12 -44 70 228
 use sky130_hilas_m12m2  sky130_hilas_m12m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -349 0 1 66
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_5
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -229 0 1 -64
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -299 0 1 -64
 box -14 -15 20 18
 use sky130_hilas_poly2m1  sky130_hilas_poly2m1_1
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 -335 0 1 114
 box -9 -26 24 25
 use sky130_hilas_nFETmed  sky130_hilas_nFETmed_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -171 0 1 -99
 box -12 -44 70 228
 use sky130_hilas_li2m2  sky130_hilas_li2m2_6
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -112 0 1 -108
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_7
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -177 0 1 -108
 box -14 -15 20 18
 use sky130_hilas_poly2m2  sky130_hilas_poly2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 0 -1 -54 1 0 115
 box -9 -26 24 29
 use sky130_hilas_pFETmed  sky130_hilas_pFETmed_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -467 0 1 187
 box 147 -22 266 265
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -349 0 1 221
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -227 0 1 325
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -296 0 1 324
 box -14 -15 20 18
 use sky130_hilas_poly2m1  sky130_hilas_poly2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -349 0 -1 185
 box -9 -26 24 25
 use sky130_hilas_pFETmed  sky130_hilas_pFETmed_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -349 0 1 187
 box 147 -22 266 265
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -108 0 1 408
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -179 0 1 402
 box -14 -15 20 18
 use sky130_hilas_poly2m2  sky130_hilas_poly2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 0 -1 -53 1 0 169
 box -9 -26 24 29
 << labels >>

diff --git a/mag/sky130_hilas_Trans4small.mag b/mag/sky130_hilas_Trans4small.mag
index b66533d..c7c0684 100644
--- a/mag/sky130_hilas_Trans4small.mag
+++ b/mag/sky130_hilas_Trans4small.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect 401 -18 455 159
 rect 395 -45 455 -18
@@ -64,47 +64,47 @@
 rect 191 -105 205 -103
 rect 191 -122 206 -105
 use sky130_hilas_pFETdevice01e  sky130_hilas_pFETdevice01e_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 319 0 1 17
 box -121 -55 82 44
 use sky130_hilas_pFETdevice01e  sky130_hilas_pFETdevice01e_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 319 0 1 -82
 box -121 -55 82 44
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 0 1 412 -1 0 -30
 box -10 -8 13 21
 use sky130_hilas_pFETdevice01e  sky130_hilas_pFETdevice01e_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 319 0 1 116
 box -121 -55 82 44
 use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 217 0 1 175
 box -14 -15 20 18
 use sky130_hilas_nFET03a  sky130_hilas_nFET03a_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 309 0 1 208
 box -111 -41 97 49
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 219 0 1 274
 box -14 -15 20 18
 use sky130_hilas_nFET03a  sky130_hilas_nFET03a_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 309 0 1 307
 box -111 -41 97 49
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 221 0 1 366
 box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 458 0 1 354
 box -10 -8 13 21
 use sky130_hilas_nFET03a  sky130_hilas_nFET03a_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 308 0 1 406
 box -111 -41 97 49
 << labels >>

diff --git a/mag/sky130_hilas_TunCap01.mag b/mag/sky130_hilas_TunCap01.mag
index 8a20e12..66d0da3 100644
--- a/mag/sky130_hilas_TunCap01.mag
+++ b/mag/sky130_hilas_TunCap01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -1451 -400 -1278 -210
 << mvvaractor >>

diff --git a/mag/sky130_hilas_VinjDiodeProtect01.mag b/mag/sky130_hilas_VinjDiodeProtect01.mag
index 890cdf2..522c93f 100644
--- a/mag/sky130_hilas_VinjDiodeProtect01.mag
+++ b/mag/sky130_hilas_VinjDiodeProtect01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1627735001
+timestamp 1629421669
 << nwell >>
 rect 742 -38 1947 556
 << mvndiff >>
@@ -55,11 +55,11 @@
 rect 592 -21 599 -4
 rect -559 -26 599 -21
 << mvpdiff >>
-rect 832 463 1850 472
-rect 832 446 839 463
+rect 834 463 1850 469
+rect 834 446 847 463
 rect 1819 446 1850 463
-rect 832 441 1850 446
-rect 1819 404 1850 441
+rect 834 440 1850 446
+rect 1819 404 1850 440
 rect 836 396 1850 404
 rect 836 379 844 396
 rect 1813 379 1850 396
@@ -101,7 +101,7 @@
 rect -551 40 593 57
 rect -552 -21 592 -4
 << mvpdiffc >>
-rect 839 446 1819 463
+rect 847 446 1819 463
 rect 844 379 1813 396
 rect 849 306 1824 323
 rect 848 238 1816 255
@@ -334,7 +334,7 @@
 rect 1886 492 1903 500
 rect 834 467 1845 469
 rect 834 463 1847 467
-rect 829 446 839 463
+rect 834 446 847 463
 rect 1819 446 1847 463
 rect 834 434 1847 446
 rect 834 417 854 434

diff --git a/mag/sky130_hilas_WTA4Stage01.mag b/mag/sky130_hilas_WTA4Stage01.mag
index 08405ff..a300465 100644
--- a/mag/sky130_hilas_WTA4Stage01.mag
+++ b/mag/sky130_hilas_WTA4Stage01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -994 555 -944 561
 rect -922 555 -872 561
@@ -119,43 +119,43 @@
 rect -1114 -41 -766 -33
 rect -1103 -57 -766 -41
 use sky130_hilas_m12m2  sky130_hilas_m12m2_5
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -791 0 1 103
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -1102 0 1 -37
 box -14 -15 20 18
 use sky130_hilas_m12m2  sky130_hilas_m12m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -1107 0 1 258
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -1105 0 1 359
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -776 0 1 514
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -778 0 1 409
 box -9 -10 23 22
 use sky130_hilas_m12m2  sky130_hilas_m12m2_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -778 0 1 221
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -1107 0 1 59
 box -14 -15 20 18
 use sky130_hilas_WTA4stage01  sky130_hilas_WTA4stage01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 67 0 1 -19
 box -54 1 229 535
 use sky130_hilas_swc4x1BiasCell  sky130_hilas_swc4x1BiasCell_0
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 -317 0 1 339
 box -264 -400 744 250
 << labels >>

diff --git a/mag/sky130_hilas_WTA4stage01.mag b/mag/sky130_hilas_WTA4stage01.mag
index 3d86c62..086f1c4 100644
--- a/mag/sky130_hilas_WTA4stage01.mag
+++ b/mag/sky130_hilas_WTA4stage01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << poly >>
 rect 142 506 162 535
 rect 141 229 162 308
@@ -8,20 +8,20 @@
 << metal1 >>
 rect 64 258 87 278
 rect 190 258 213 279
-use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_0
-timestamp 1628285143
-transform 1 0 54 0 1 77
-box -108 -76 175 67
-use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_1
-timestamp 1628285143
-transform 1 0 54 0 -1 182
+use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_3
+timestamp 1629420194
+transform 1 0 54 0 1 354
 box -108 -76 175 67
 use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 54 0 -1 459
 box -108 -76 175 67
-use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_3
-timestamp 1628285143
-transform 1 0 54 0 1 354
+use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_1
+timestamp 1629420194
+transform 1 0 54 0 -1 182
+box -108 -76 175 67
+use sky130_hilas_WTAsinglestage01  sky130_hilas_WTAsinglestage01_0
+timestamp 1629420194
+transform 1 0 54 0 1 77
 box -108 -76 175 67
 << end >>

diff --git a/mag/sky130_hilas_WTAsinglestage01.mag b/mag/sky130_hilas_WTAsinglestage01.mag
index 944c9dc..f812886 100644
--- a/mag/sky130_hilas_WTAsinglestage01.mag
+++ b/mag/sky130_hilas_WTAsinglestage01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nmos >>
 rect -18 -34 2 25
 rect 88 -34 108 25
@@ -116,12 +116,12 @@
 << metal2 >>
 rect -54 -2 175 14
 rect -108 -72 -96 -51
-use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
-transform 1 0 -84 0 1 -61
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -69 0 1 7
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_1
+timestamp 1629420194
+transform 1 0 -84 0 1 -61
+box -14 -15 20 18
 << end >>

diff --git a/mag/sky130_hilas_cellAttempt01.mag b/mag/sky130_hilas_cellAttempt01.mag
index 3976421..4de2af3 100644
--- a/mag/sky130_hilas_cellAttempt01.mag
+++ b/mag/sky130_hilas_cellAttempt01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 555 212 605 218
 rect 627 212 677 218
@@ -187,59 +187,59 @@
 rect -263 -305 499 -287
 rect -263 -347 497 -330
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 -4
 box -1451 -400 -1278 -210
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 135
 box -1451 -400 -1278 -210
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 -9
 box -957 -395 -734 -209
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 130
 box -957 -395 -734 -209
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 1 -445
 box -289 41 -33 232
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 -1 -37
 box -289 41 -33 232
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 324
 box -1451 -400 -1278 -210
 use sky130_hilas_wellContact  sky130_hilas_wellContact_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1185 0 1 293
 box -1448 -441 -1275 -255
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 315
 box -957 -395 -734 -209
 use sky130_hilas_wellContact  sky130_hilas_wellContact_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1588 0 1 286
 box -1448 -441 -1275 -255
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 1 -122
 box -289 41 -33 232
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 455
 box -1451 -400 -1278 -210
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 455
 box -957 -395 -734 -209
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 -1 287
 box -289 41 -33 232
 << labels >>

diff --git a/mag/sky130_hilas_drainSelect01.mag b/mag/sky130_hilas_drainSelect01.mag
index 9f8bb98..d06477f 100644
--- a/mag/sky130_hilas_drainSelect01.mag
+++ b/mag/sky130_hilas_drainSelect01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 1135 598 1185 603
 rect 1275 598 1325 604
@@ -64,21 +64,21 @@
 rect 1614 197 1622 220
 rect 1613 63 1622 86
 rect 1050 15 1228 32
-use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_1
-timestamp 1628285143
-transform 1 0 1282 0 -1 586
-box -232 -45 336 125
-use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_0
-timestamp 1628285143
-transform 1 0 1282 0 1 337
+use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_3
+timestamp 1629420194
+transform 1 0 1282 0 -1 266
 box -232 -45 336 125
 use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1282 0 1 17
 box -232 -45 336 125
-use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_3
-timestamp 1628285143
-transform 1 0 1282 0 -1 266
+use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_0
+timestamp 1629420194
+transform 1 0 1282 0 1 337
+box -232 -45 336 125
+use sky130_hilas_TgateVinj01  sky130_hilas_TgateVinj01_1
+timestamp 1629420194
+transform 1 0 1282 0 -1 586
 box -232 -45 336 125
 << labels >>
 rlabel space 1107 356 1112 374 0 DRAIN2

diff --git a/mag/sky130_hilas_horizPcell01.mag b/mag/sky130_hilas_horizPcell01.mag
index aa2424a..44610c1 100644
--- a/mag/sky130_hilas_horizPcell01.mag
+++ b/mag/sky130_hilas_horizPcell01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -222 180 -172 186
 rect -222 138 -172 144
@@ -100,12 +100,12 @@
 rect -289 140 -280 158
 rect -250 140 -33 158
 rect -251 97 -33 115
-use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
-transform 1 0 -266 0 -1 156
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -266 0 -1 101
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_1
+timestamp 1629420194
+transform 1 0 -266 0 -1 156
+box -14 -15 20 18
 << end >>

diff --git a/mag/sky130_hilas_horizTransCell01.mag b/mag/sky130_hilas_horizTransCell01.mag
index ce78c45..9129db2 100644
--- a/mag/sky130_hilas_horizTransCell01.mag
+++ b/mag/sky130_hilas_horizTransCell01.mag

@@ -1,13 +1,13 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -222 111 -172 117
 rect -150 111 -100 117
 rect -222 69 -172 75
 rect -150 69 -100 75
 << nwell >>
-rect -364 42 -33 359
+rect -363 42 -33 359
 << mvpmos >>
 rect -224 142 -173 326
 rect -222 75 -172 111

diff --git a/mag/sky130_hilas_horizTransCell01a.mag b/mag/sky130_hilas_horizTransCell01a.mag
index ef76abf..acaea73 100644
--- a/mag/sky130_hilas_horizTransCell01a.mag
+++ b/mag/sky130_hilas_horizTransCell01a.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -465 248 -463 298
 rect -423 248 -421 298

diff --git a/mag/sky130_hilas_li2m1.mag b/mag/sky130_hilas_li2m1.mag
index 6a88c4e..0782ef1 100644
--- a/mag/sky130_hilas_li2m1.mag
+++ b/mag/sky130_hilas_li2m1.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -10 15 13 21
 rect -10 -2 -7 15

diff --git a/mag/sky130_hilas_li2m2.mag b/mag/sky130_hilas_li2m2.mag
index 27d5a5f..2b163dd 100644
--- a/mag/sky130_hilas_li2m2.mag
+++ b/mag/sky130_hilas_li2m2.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << locali >>
 rect -13 10 19 14
 rect -13 9 20 10

diff --git a/mag/sky130_hilas_m12m2.mag b/mag/sky130_hilas_m12m2.mag
index 261ec05..8786d3f 100644
--- a/mag/sky130_hilas_m12m2.mag
+++ b/mag/sky130_hilas_m12m2.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << metal1 >>
 rect -6 19 20 22
 rect -6 -10 20 -7

diff --git a/mag/sky130_hilas_nDiffThOxContact.mag b/mag/sky130_hilas_nDiffThOxContact.mag
index d7ffb07..13bfab1 100644
--- a/mag/sky130_hilas_nDiffThOxContact.mag
+++ b/mag/sky130_hilas_nDiffThOxContact.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -24 41 39 42
 << mvndiff >>

diff --git a/mag/sky130_hilas_nFET03.mag b/mag/sky130_hilas_nFET03.mag
index 9d5d25e..e3a2199 100644
--- a/mag/sky130_hilas_nFET03.mag
+++ b/mag/sky130_hilas_nFET03.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect 0 29 27 36
 rect 0 -13 27 -6

diff --git a/mag/sky130_hilas_nFET03a.mag b/mag/sky130_hilas_nFET03a.mag
index ff7e465..23c216b 100644
--- a/mag/sky130_hilas_nFET03a.mag
+++ b/mag/sky130_hilas_nFET03a.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nmos >>
 rect 0 -6 27 36
 << ndiff >>
@@ -35,12 +35,12 @@
 << metal2 >>
 rect -111 2 -51 19
 rect 75 3 97 20
-use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
-transform 1 0 -44 0 1 10
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 65 0 1 11
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_1
+timestamp 1629420194
+transform 1 0 -44 0 1 10
+box -14 -15 20 18
 << end >>

diff --git a/mag/sky130_hilas_nFETLarge.mag b/mag/sky130_hilas_nFETLarge.mag
index 5b65be6..a6aaf19 100644
--- a/mag/sky130_hilas_nFETLarge.mag
+++ b/mag/sky130_hilas_nFETLarge.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << psubdiff >>
 rect 77 642 117 896
 rect 77 625 88 642
@@ -99,92 +99,92 @@
 rect 466 497 501 741
 rect 207 465 501 497
 rect 207 464 478 465
-use sky130_hilas_li2m2  sky130_hilas_li2m2_8
-timestamp 1628285143
-transform 1 0 107 0 1 482
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_7
-timestamp 1628285143
-transform 1 0 108 0 1 435
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_9
-timestamp 1628285143
-transform 1 0 164 0 1 546
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_19
-timestamp 1628285143
-transform 1 0 439 0 1 479
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_17
-timestamp 1628285143
-transform 1 0 329 0 1 478
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_15
-timestamp 1628285143
-transform 1 0 220 0 1 478
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_6
-timestamp 1628285143
-transform 1 0 384 0 1 546
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_10
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 274 0 1 546
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
-transform 1 0 164 0 1 683
+use sky130_hilas_li2m2  sky130_hilas_li2m2_6
+timestamp 1629420194
+transform 1 0 384 0 1 546
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
-transform 1 0 384 0 1 683
+use sky130_hilas_li2m2  sky130_hilas_li2m2_15
+timestamp 1629420194
+transform 1 0 220 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_17
+timestamp 1629420194
+transform 1 0 329 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_19
+timestamp 1629420194
+transform 1 0 439 0 1 479
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_9
+timestamp 1629420194
+transform 1 0 164 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_7
+timestamp 1629420194
+transform 1 0 108 0 1 435
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_8
+timestamp 1629420194
+transform 1 0 107 0 1 482
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 274 0 1 683
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_2
+timestamp 1629420194
+transform 1 0 384 0 1 683
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_0
+timestamp 1629420194
+transform 1 0 164 0 1 683
+box -14 -15 20 18
 use sky130_hilas_nFETLargePart1  sky130_hilas_nFETLargePart1_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 319 0 1 473
 box -165 -31 137 241
-use sky130_hilas_li2m2  sky130_hilas_li2m2_5
-timestamp 1628285143
-transform 1 0 439 0 1 756
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_4
-timestamp 1628285143
-transform 1 0 220 0 1 756
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 329 0 1 756
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_13
-timestamp 1628285143
-transform 1 0 440 0 1 890
+use sky130_hilas_li2m2  sky130_hilas_li2m2_4
+timestamp 1629420194
+transform 1 0 220 0 1 756
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_12
-timestamp 1628285143
-transform 1 0 329 0 1 891
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_16
-timestamp 1628285143
-transform 1 0 220 0 1 893
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_11
-timestamp 1628285143
-transform 1 0 165 0 1 961
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_18
-timestamp 1628285143
-transform 1 0 384 0 1 960
+use sky130_hilas_li2m2  sky130_hilas_li2m2_5
+timestamp 1629420194
+transform 1 0 439 0 1 756
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_14
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 274 0 1 961
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_18
+timestamp 1629420194
+transform 1 0 384 0 1 960
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_11
+timestamp 1629420194
+transform 1 0 165 0 1 961
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_16
+timestamp 1629420194
+transform 1 0 220 0 1 893
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_12
+timestamp 1629420194
+transform 1 0 329 0 1 891
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_13
+timestamp 1629420194
+transform 1 0 440 0 1 890
+box -14 -15 20 18
 use sky130_hilas_nFETLargePart1  sky130_hilas_nFETLargePart1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 319 0 1 751
 box -165 -31 137 241
 << labels >>

diff --git a/mag/sky130_hilas_nFETLargePart1.mag b/mag/sky130_hilas_nFETLargePart1.mag
index 7ac3a81..8cecca6 100644
--- a/mag/sky130_hilas_nFETLargePart1.mag
+++ b/mag/sky130_hilas_nFETLargePart1.mag

@@ -1,24 +1,24 @@
 magic
 tech sky130A
-timestamp 1628285143
-use sky130_hilas_nFETmed  sky130_hilas_nFETmed_2
-timestamp 1628285143
-transform 1 0 12 0 1 13
-box -12 -44 70 228
-use sky130_hilas_nFETmed  sky130_hilas_nFETmed_1
-timestamp 1628285143
-transform 1 0 -43 0 1 13
-box -12 -44 70 228
-use sky130_hilas_nFETmed  sky130_hilas_nFETmed_0
-timestamp 1628285143
-transform 1 0 -98 0 1 13
+timestamp 1629420194
+use sky130_hilas_nFETmed  sky130_hilas_nFETmed_3
+timestamp 1629420194
+transform 1 0 67 0 1 13
 box -12 -44 70 228
 use sky130_hilas_nFETmed  sky130_hilas_nFETmed_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -153 0 1 13
 box -12 -44 70 228
-use sky130_hilas_nFETmed  sky130_hilas_nFETmed_3
-timestamp 1628285143
-transform 1 0 67 0 1 13
+use sky130_hilas_nFETmed  sky130_hilas_nFETmed_0
+timestamp 1629420194
+transform 1 0 -98 0 1 13
+box -12 -44 70 228
+use sky130_hilas_nFETmed  sky130_hilas_nFETmed_1
+timestamp 1629420194
+transform 1 0 -43 0 1 13
+box -12 -44 70 228
+use sky130_hilas_nFETmed  sky130_hilas_nFETmed_2
+timestamp 1629420194
+transform 1 0 12 0 1 13
 box -12 -44 70 228
 << end >>

diff --git a/mag/sky130_hilas_nFETmed.mag b/mag/sky130_hilas_nFETmed.mag
index d04278c..093f1ba 100644
--- a/mag/sky130_hilas_nFETmed.mag
+++ b/mag/sky130_hilas_nFETmed.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nmos >>
 rect 16 -31 42 215
 << ndiff >>

diff --git a/mag/sky130_hilas_nMirror03.mag b/mag/sky130_hilas_nMirror03.mag
index 62a0a44..1d71b0f 100644
--- a/mag/sky130_hilas_nMirror03.mag
+++ b/mag/sky130_hilas_nMirror03.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 26 110 53 116
 rect 26 68 53 74
@@ -48,28 +48,28 @@
 rect 79 9 114 17
 << metal2 >>
 rect -59 14 -26 35
-use sky130_hilas_poly2li  sky130_hilas_poly2li_0
-timestamp 1628285143
-transform 1 0 -37 0 1 24
-box -9 -14 18 19
-use sky130_hilas_nFET03  sky130_hilas_nFET03_0
-timestamp 1628285143
-transform 1 0 26 0 1 14
-box -31 -19 58 42
-use sky130_hilas_nFET03  sky130_hilas_nFET03_1
-timestamp 1628285143
-transform 1 0 26 0 1 80
-box -31 -19 58 42
-use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
-transform 1 0 -10 0 1 90
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
-transform 1 0 -15 0 1 25
-box -14 -15 20 18
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 88 0 1 52
 box -10 -8 13 21
+use sky130_hilas_li2m2  sky130_hilas_li2m2_0
+timestamp 1629420194
+transform 1 0 -15 0 1 25
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_1
+timestamp 1629420194
+transform 1 0 -10 0 1 90
+box -14 -15 20 18
+use sky130_hilas_nFET03  sky130_hilas_nFET03_1
+timestamp 1629420194
+transform 1 0 26 0 1 80
+box -31 -19 58 42
+use sky130_hilas_nFET03  sky130_hilas_nFET03_0
+timestamp 1629420194
+transform 1 0 26 0 1 14
+box -31 -19 58 42
+use sky130_hilas_poly2li  sky130_hilas_poly2li_0
+timestamp 1629420194
+transform 1 0 -37 0 1 24
+box -9 -14 18 19
 << end >>

diff --git a/mag/sky130_hilas_nOverlapCap01.mag b/mag/sky130_hilas_nOverlapCap01.mag
index c25dd1b..b80557e 100644
--- a/mag/sky130_hilas_nOverlapCap01.mag
+++ b/mag/sky130_hilas_nOverlapCap01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -12 68 17 86
 rect -12 36 -11 37

diff --git a/mag/sky130_hilas_overlapCap02a.mag b/mag/sky130_hilas_overlapCap02a.mag
index c0112b4..ef1be0b 100644
--- a/mag/sky130_hilas_overlapCap02a.mag
+++ b/mag/sky130_hilas_overlapCap02a.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -454 77 -425 93
 rect -375 77 -346 93

diff --git a/mag/sky130_hilas_pFETLarge.mag b/mag/sky130_hilas_pFETLarge.mag
index 324df9f..268c3a9 100644
--- a/mag/sky130_hilas_pFETLarge.mag
+++ b/mag/sky130_hilas_pFETLarge.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect 145 728 213 729
 rect 145 725 221 728
@@ -97,92 +97,92 @@
 rect 466 497 501 741
 rect 207 465 501 497
 rect 207 464 478 465
-use sky130_hilas_li2m2  sky130_hilas_li2m2_8
-timestamp 1628285143
-transform 1 0 107 0 1 482
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_7
-timestamp 1628285143
-transform 1 0 108 0 1 435
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_9
-timestamp 1628285143
-transform 1 0 164 0 1 546
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_19
-timestamp 1628285143
-transform 1 0 439 0 1 479
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_17
-timestamp 1628285143
-transform 1 0 329 0 1 478
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_15
-timestamp 1628285143
-transform 1 0 220 0 1 478
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_6
-timestamp 1628285143
-transform 1 0 384 0 1 546
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_10
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 274 0 1 546
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
-transform 1 0 164 0 1 683
+use sky130_hilas_li2m2  sky130_hilas_li2m2_6
+timestamp 1629420194
+transform 1 0 384 0 1 546
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
-transform 1 0 384 0 1 683
+use sky130_hilas_li2m2  sky130_hilas_li2m2_15
+timestamp 1629420194
+transform 1 0 220 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_17
+timestamp 1629420194
+transform 1 0 329 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_19
+timestamp 1629420194
+transform 1 0 439 0 1 479
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_9
+timestamp 1629420194
+transform 1 0 164 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_7
+timestamp 1629420194
+transform 1 0 108 0 1 435
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_8
+timestamp 1629420194
+transform 1 0 107 0 1 482
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 274 0 1 683
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_2
+timestamp 1629420194
+transform 1 0 384 0 1 683
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_0
+timestamp 1629420194
+transform 1 0 164 0 1 683
+box -14 -15 20 18
 use sky130_hilas_pFETLargePart1  sky130_hilas_pFETLargePart1_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 142 0 1 446
 box -6 -9 333 278
-use sky130_hilas_li2m2  sky130_hilas_li2m2_5
-timestamp 1628285143
-transform 1 0 439 0 1 756
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_4
-timestamp 1628285143
-transform 1 0 220 0 1 756
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 329 0 1 756
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_13
-timestamp 1628285143
-transform 1 0 440 0 1 890
+use sky130_hilas_li2m2  sky130_hilas_li2m2_4
+timestamp 1629420194
+transform 1 0 220 0 1 756
 box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_12
-timestamp 1628285143
-transform 1 0 329 0 1 891
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_16
-timestamp 1628285143
-transform 1 0 220 0 1 893
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_11
-timestamp 1628285143
-transform 1 0 165 0 1 961
-box -14 -15 20 18
-use sky130_hilas_li2m2  sky130_hilas_li2m2_18
-timestamp 1628285143
-transform 1 0 384 0 1 960
+use sky130_hilas_li2m2  sky130_hilas_li2m2_5
+timestamp 1629420194
+transform 1 0 439 0 1 756
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_14
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 274 0 1 961
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_18
+timestamp 1629420194
+transform 1 0 384 0 1 960
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_11
+timestamp 1629420194
+transform 1 0 165 0 1 961
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_16
+timestamp 1629420194
+transform 1 0 220 0 1 893
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_12
+timestamp 1629420194
+transform 1 0 329 0 1 891
+box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_13
+timestamp 1629420194
+transform 1 0 440 0 1 890
+box -14 -15 20 18
 use sky130_hilas_pFETLargePart1  sky130_hilas_pFETLargePart1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 142 0 1 729
 box -6 -9 333 278
 << labels >>

diff --git a/mag/sky130_hilas_pFETLargePart1.mag b/mag/sky130_hilas_pFETLargePart1.mag
index 698f1f6..9140af6 100644
--- a/mag/sky130_hilas_pFETLargePart1.mag
+++ b/mag/sky130_hilas_pFETLargePart1.mag

@@ -1,24 +1,24 @@
 magic
 tech sky130A
-timestamp 1628285143
-use sky130_hilas_pFETmed  sky130_hilas_pFETmed_2
-timestamp 1628285143
-transform 1 0 12 0 1 13
-box 147 -22 266 265
-use sky130_hilas_pFETmed  sky130_hilas_pFETmed_1
-timestamp 1628285143
-transform 1 0 -43 0 1 13
-box 147 -22 266 265
-use sky130_hilas_pFETmed  sky130_hilas_pFETmed_0
-timestamp 1628285143
-transform 1 0 -98 0 1 13
+timestamp 1629420194
+use sky130_hilas_pFETmed  sky130_hilas_pFETmed_3
+timestamp 1629420194
+transform 1 0 67 0 1 13
 box 147 -22 266 265
 use sky130_hilas_pFETmed  sky130_hilas_pFETmed_4
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -153 0 1 13
 box 147 -22 266 265
-use sky130_hilas_pFETmed  sky130_hilas_pFETmed_3
-timestamp 1628285143
-transform 1 0 67 0 1 13
+use sky130_hilas_pFETmed  sky130_hilas_pFETmed_0
+timestamp 1629420194
+transform 1 0 -98 0 1 13
+box 147 -22 266 265
+use sky130_hilas_pFETmed  sky130_hilas_pFETmed_1
+timestamp 1629420194
+transform 1 0 -43 0 1 13
+box 147 -22 266 265
+use sky130_hilas_pFETmed  sky130_hilas_pFETmed_2
+timestamp 1629420194
+transform 1 0 12 0 1 13
 box 147 -22 266 265
 << end >>

diff --git a/mag/sky130_hilas_pFETdevice01.mag b/mag/sky130_hilas_pFETdevice01.mag
index 4349333..b31b5ef 100644
--- a/mag/sky130_hilas_pFETdevice01.mag
+++ b/mag/sky130_hilas_pFETdevice01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -18 20 21 23
 rect -18 -22 21 -19

diff --git a/mag/sky130_hilas_pFETdevice01a.mag b/mag/sky130_hilas_pFETdevice01a.mag
index 1540d08..dbbbd1d 100644
--- a/mag/sky130_hilas_pFETdevice01a.mag
+++ b/mag/sky130_hilas_pFETdevice01a.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -18 20 21 23
 rect -18 -22 21 -19

diff --git a/mag/sky130_hilas_pFETdevice01aa.mag b/mag/sky130_hilas_pFETdevice01aa.mag
index 221d124..660eaf8 100644
--- a/mag/sky130_hilas_pFETdevice01aa.mag
+++ b/mag/sky130_hilas_pFETdevice01aa.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_p >>
 rect -18 20 21 23
 rect -18 -22 21 -19

diff --git a/mag/sky130_hilas_pFETdevice01b.mag b/mag/sky130_hilas_pFETdevice01b.mag
index 7611e77..10f51d5 100644
--- a/mag/sky130_hilas_pFETdevice01b.mag
+++ b/mag/sky130_hilas_pFETdevice01b.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -18 20 21 23
 rect -18 -22 21 -19
@@ -20,7 +20,7 @@
 rect 80 -79 85 -78
 rect 93 -90 108 -78
 use sky130_hilas_poly2m1  sky130_hilas_poly2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 76 0 1 -88
 box -9 -26 24 25
 << end >>

diff --git a/mag/sky130_hilas_pFETdevice01d.mag b/mag/sky130_hilas_pFETdevice01d.mag
index de9d764..deefffa 100644
--- a/mag/sky130_hilas_pFETdevice01d.mag
+++ b/mag/sky130_hilas_pFETdevice01d.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -18 20 21 23
 rect -18 -22 21 -19
@@ -34,12 +34,12 @@
 rect -41 -16 -24 -8
 rect 27 9 44 17
 rect 27 -16 44 -8
-use sky130_hilas_poly2m1  sky130_hilas_poly2m1_2
-timestamp 1628285143
-transform 1 0 73 0 -1 -77
-box -9 -26 24 25
 use sky130_hilas_poly2m1  sky130_hilas_poly2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 -85 0 1 7
 box -9 -26 24 25
+use sky130_hilas_poly2m1  sky130_hilas_poly2m1_2
+timestamp 1629420194
+transform 1 0 73 0 -1 -77
+box -9 -26 24 25
 << end >>

diff --git a/mag/sky130_hilas_pFETdevice01e.mag b/mag/sky130_hilas_pFETdevice01e.mag
index 375a5c4..6e4e094 100644
--- a/mag/sky130_hilas_pFETdevice01e.mag
+++ b/mag/sky130_hilas_pFETdevice01e.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -121 -55 82 44
 << pmos >>
@@ -32,16 +32,16 @@
 << metal2 >>
 rect -121 -3 -84 16
 rect -121 -45 -83 -26
-use sky130_hilas_poly2m2  sky130_hilas_poly2m2_0
-timestamp 1628285143
-transform 0 1 -87 -1 0 -28
-box -9 -26 24 29
-use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
-transform 1 0 -73 0 1 9
-box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 57 0 1 -1
 box -14 -15 20 18
+use sky130_hilas_li2m2  sky130_hilas_li2m2_1
+timestamp 1629420194
+transform 1 0 -73 0 1 9
+box -14 -15 20 18
+use sky130_hilas_poly2m2  sky130_hilas_poly2m2_0
+timestamp 1629420194
+transform 0 1 -87 -1 0 -28
+box -9 -26 24 29
 << end >>

diff --git a/mag/sky130_hilas_pFETdevice01w1.mag b/mag/sky130_hilas_pFETdevice01w1.mag
index 1923bfe..4ea09cc 100644
--- a/mag/sky130_hilas_pFETdevice01w1.mag
+++ b/mag/sky130_hilas_pFETdevice01w1.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -79 -78 82 43
 << pmos >>

diff --git a/mag/sky130_hilas_pFETmed.mag b/mag/sky130_hilas_pFETmed.mag
index cc419c8..0ff4be8 100644
--- a/mag/sky130_hilas_pFETmed.mag
+++ b/mag/sky130_hilas_pFETmed.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect 147 -22 266 265
 << pmos >>

diff --git a/mag/sky130_hilas_pFETmirror02.mag b/mag/sky130_hilas_pFETmirror02.mag
index 7212c0c..8442bab 100644
--- a/mag/sky130_hilas_pFETmirror02.mag
+++ b/mag/sky130_hilas_pFETmirror02.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -61 89 67 373
 << pmos >>
@@ -73,7 +73,7 @@
 rect -5 112 31 140
 rect -5 95 28 112
 use sky130_hilas_poly2li  sky130_hilas_poly2li_0
-timestamp 1628285143
+timestamp 1629420194
 transform 0 1 39 -1 0 108
 box -9 -14 18 19
 << end >>

diff --git a/mag/sky130_hilas_pTransistorPair.mag b/mag/sky130_hilas_pTransistorPair.mag
index 3bd92c3..d5b5f92 100644
--- a/mag/sky130_hilas_pTransistorPair.mag
+++ b/mag/sky130_hilas_pTransistorPair.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect 133 -140 319 -133
 rect 267 -169 312 -146
@@ -25,43 +25,43 @@
 rect 255 -352 310 -327
 rect 201 -438 289 -413
 use sky130_hilas_poly2li  sky130_hilas_poly2li_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 236 0 1 -426
 box -9 -14 18 19
 use sky130_hilas_pTransistorVert01  sky130_hilas_pTransistorVert01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 496 0 1 5
 box -363 -444 -177 -145
 use sky130_hilas_m12m2  sky130_hilas_m12m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 287 0 1 -244
 box -9 -10 23 22
 use sky130_hilas_li2m2  sky130_hilas_li2m2_2
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 290 0 -1 -338
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 248 0 1 -159
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_3
-timestamp 1628285143
+timestamp 1629420194
 transform -1 0 275 0 -1 -421
 box -14 -15 20 18
 use sky130_hilas_li2m2  sky130_hilas_li2m2_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 175 0 1 -287
 box -14 -15 20 18
 use sky130_hilas_poly2li  sky130_hilas_poly2li_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 234 0 1 -123
 box -9 -14 18 19
 use sky130_hilas_pTransistorVert01  sky130_hilas_pTransistorVert01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 496 0 1 310
 box -363 -444 -177 -145
 use sky130_hilas_li2m1  sky130_hilas_li2m1_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 291 0 1 -85
 box -10 -8 13 21
 << end >>

diff --git a/mag/sky130_hilas_pTransistorVert01.mag b/mag/sky130_hilas_pTransistorVert01.mag
index 87df93b..036b964 100644
--- a/mag/sky130_hilas_pTransistorVert01.mag
+++ b/mag/sky130_hilas_pTransistorVert01.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -363 -444 -177 -145
 << mvpmos >>

diff --git a/mag/sky130_hilas_poly2li.mag b/mag/sky130_hilas_poly2li.mag
index 3239d98..4e695b0 100644
--- a/mag/sky130_hilas_poly2li.mag
+++ b/mag/sky130_hilas_poly2li.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << poly >>
 rect -9 11 18 19
 rect -9 -6 -4 11

diff --git a/mag/sky130_hilas_poly2m1.mag b/mag/sky130_hilas_poly2m1.mag
index 365267c..1f39a18 100644
--- a/mag/sky130_hilas_poly2m1.mag
+++ b/mag/sky130_hilas_poly2m1.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << poly >>
 rect -9 17 24 25
 rect -9 0 -1 17

diff --git a/mag/sky130_hilas_poly2m2.mag b/mag/sky130_hilas_poly2m2.mag
index 82f7248..e064e23 100644
--- a/mag/sky130_hilas_poly2m2.mag
+++ b/mag/sky130_hilas_poly2m2.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << poly >>
 rect -9 17 24 25
 rect -9 0 -1 17

diff --git a/mag/sky130_hilas_swc4x1BiasCell.mag b/mag/sky130_hilas_swc4x1BiasCell.mag
index f07ce32..cd8ec22 100644
--- a/mag/sky130_hilas_swc4x1BiasCell.mag
+++ b/mag/sky130_hilas_swc4x1BiasCell.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect 555 216 605 222
 rect 627 216 677 222
@@ -212,59 +212,59 @@
 rect 733 -301 744 -283
 rect 733 -344 744 -326
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 0
 box -1451 -400 -1278 -210
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 135
 box -1451 -400 -1278 -210
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 -5
 box -957 -395 -734 -209
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 130
 box -957 -395 -734 -209
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 1 -441
 box -289 41 -33 232
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 -1 -33
 box -289 41 -33 232
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 324
 box -1451 -400 -1278 -210
 use sky130_hilas_wellContact  sky130_hilas_wellContact_1
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1185 0 1 293
 box -1448 -441 -1275 -255
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_2
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 315
 box -957 -395 -734 -209
 use sky130_hilas_wellContact  sky130_hilas_wellContact_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1588 0 1 286
 box -1448 -441 -1275 -255
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 1 -116
 box -289 41 -33 232
 use sky130_hilas_TunCap01  sky130_hilas_TunCap01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1188 0 1 460
 box -1451 -400 -1278 -210
 use sky130_hilas_FGVaractorCapacitor  sky130_hilas_FGVaractorCapacitor_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 1069 0 1 459
 box -957 -395 -734 -209
 use sky130_hilas_horizPcell01  sky130_hilas_horizPcell01_3
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 777 0 -1 291
 box -289 41 -33 232
 << labels >>

diff --git a/mag/sky130_hilas_swc4x2cell.mag b/mag/sky130_hilas_swc4x2cell.mag
index 32aff4e..13046f1 100644
--- a/mag/sky130_hilas_swc4x2cell.mag
+++ b/mag/sky130_hilas_swc4x2cell.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << error_s >>
 rect -937 590 -887 596
 rect -865 590 -815 596
@@ -124,14 +124,14 @@
 rect 999 73 1008 91
 rect -1004 30 -997 48
 rect 999 30 1008 48
-use sky130_hilas_cellAttempt01  sky130_hilas_cellAttempt01_1
-timestamp 1628285143
-transform -1 0 -260 0 1 378
-box -263 -404 744 246
 use sky130_hilas_cellAttempt01  sky130_hilas_cellAttempt01_0
-timestamp 1628285143
+timestamp 1629420194
 transform 1 0 264 0 1 378
 box -263 -404 744 246
+use sky130_hilas_cellAttempt01  sky130_hilas_cellAttempt01_1
+timestamp 1629420194
+transform -1 0 -260 0 1 378
+box -263 -404 744 246
 << labels >>
 rlabel metal1 441 591 479 601 0 GATE2
 port 1 nsew analog default

diff --git a/mag/sky130_hilas_wellContact.mag b/mag/sky130_hilas_wellContact.mag
index 2c5c1c0..da5325d 100644
--- a/mag/sky130_hilas_wellContact.mag
+++ b/mag/sky130_hilas_wellContact.mag

@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1628285143
+timestamp 1629420194
 << nwell >>
 rect -1448 -440 -1275 -256
 << mvnsubdiff >>

diff --git a/verilog/rtl/sky130_hilas_sc.v b/verilog/rtl/sky130_hilas_sc.v
index bcdc2bc..14cb803 100644
--- a/verilog/rtl/sky130_hilas_sc.v
+++ b/verilog/rtl/sky130_hilas_sc.v

@@ -36,13 +36,13 @@
 
 `define USE_POWER_PINS 1
 
-`ifndef SKY130_HILAS_PTRANSISTORPAIR
-`define SKY130_HILAS_PTRANSISTORPAIR
+`ifndef SKY130_HILAS_VINJDIODEPROTECT01
+`define SKY130_HILAS_VINJDIODEPROTECT01
 
 /**
- * sky130_hilas_pTransistorPair: None
+ * sky130_hilas_VinjDiodeProtect01: protective ESD diode for VINJ line
  *
- * Verilog wrapper for sky130_hilas_pTransistorPair.
+ * Verilog wrapper for sky130_hilas_VinjDiodeProtect01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -55,91 +55,15 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pTransistorPair (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorPair (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PTRANSISTORPAIR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATE4DOUBLE01
-`define SKY130_HILAS_TGATE4DOUBLE01
-
-/**
- * sky130_hilas_Tgate4Double01: 4 double-throw transmission gates
- *
- * Verilog wrapper for sky130_hilas_Tgate4Double01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_Tgate4Double01 (
-    INPUT1_1,
-    SELECT1,
-    SELECT2,
-    INPUT2_2,
-    INPUT1_2,
-    SELECT3,
-    INPUT2_3,
-    SELECT4,
-    INPUT2_4,
-    INPUT1_4,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT2,
-    OUTPUT1,
-    INPUT2_1,
-    INPUT1_3,
+module sky130_hilas_VinjDiodeProtect01 (
+    VINJ,
+    INPUT,
     VGND,
     VNB,
     VPB
 );
-        inout INPUT1_1;
-        inout SELECT1;
-        inout SELECT2;
-        inout INPUT2_2;
-        inout INPUT1_2;
-        inout SELECT3;
-        inout INPUT2_3;
-        inout SELECT4;
-        inout INPUT2_4;
-        inout INPUT1_4;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT2;
-        inout OUTPUT1;
-        inout INPUT2_1;
-        inout INPUT1_3;
+        inout VINJ;
+        inout INPUT;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -151,40 +75,12 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_Tgate4Double01 (
-    INPUT1_1,
-    SELECT1,
-    SELECT2,
-    INPUT2_2,
-    INPUT1_2,
-    SELECT3,
-    INPUT2_3,
-    SELECT4,
-    INPUT2_4,
-    INPUT1_4,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT2,
-    OUTPUT1,
-    INPUT2_1,
-    INPUT1_3
+module sky130_hilas_VinjDiodeProtect01 (
+    VINJ,
+    INPUT
 );
-        inout INPUT1_1;
-        inout SELECT1;
-        inout SELECT2;
-        inout INPUT2_2;
-        inout INPUT1_2;
-        inout SELECT3;
-        inout INPUT2_3;
-        inout SELECT4;
-        inout INPUT2_4;
-        inout INPUT1_4;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT2;
-        inout OUTPUT1;
-        inout INPUT2_1;
-        inout INPUT1_3;
+        inout VINJ;
+        inout INPUT;
 endmodule
 `endcelldefine
 
@@ -192,18 +88,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_TGATE4DOUBLE01
+`endif  // SKY130_HILAS_VINJDIODEPROTECT01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_TGATE4SINGLE01
-`define SKY130_HILAS_TGATE4SINGLE01
+`ifndef SKY130_HILAS_TGATESINGLE01PART2
+`define SKY130_HILAS_TGATESINGLE01PART2
 
 /**
- * sky130_hilas_Tgate4Single01: 4 single-throw transmission gates
+ * sky130_hilas_TgateSingle01Part2: None
  *
- * Verilog wrapper for sky130_hilas_Tgate4Single01.
+ * Verilog wrapper for sky130_hilas_TgateSingle01Part2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -216,106 +112,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_Tgate4Single01 (
-    INPUT1_2,
-    SELECT2,
-    OUTPUT2,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT1,
-    INPUT1_4,
-    SELECT4,
-    SELECT3,
-    INPUT1_3,
-    SELECT1,
-    INPUT1_1,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout INPUT1_2;
-        inout SELECT2;
-        inout OUTPUT2;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT1;
-        inout INPUT1_4;
-        inout SELECT4;
-        inout SELECT3;
-        inout INPUT1_3;
-        inout SELECT1;
-        inout INPUT1_1;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_Tgate4Single01 (
-    INPUT1_2,
-    SELECT2,
-    OUTPUT2,
-    OUTPUT4,
-    OUTPUT3,
-    OUTPUT1,
-    INPUT1_4,
-    SELECT4,
-    SELECT3,
-    INPUT1_3,
-    SELECT1,
-    INPUT1_1
-);
-        inout INPUT1_2;
-        inout SELECT2;
-        inout OUTPUT2;
-        inout OUTPUT4;
-        inout OUTPUT3;
-        inout OUTPUT1;
-        inout INPUT1_4;
-        inout SELECT4;
-        inout SELECT3;
-        inout INPUT1_3;
-        inout SELECT1;
-        inout INPUT1_1;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATE4SINGLE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_MCAP2M4
-`define SKY130_HILAS_MCAP2M4
-
-/**
- * sky130_hilas_mcap2m4: metal capacitor layer contact to m4
- *
- * Verilog wrapper for sky130_hilas_mcap2m4.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_mcap2m4 (
+module sky130_hilas_TgateSingle01Part2 (
     VNB,
     VPB
 );
@@ -329,7 +126,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_mcap2m4 (
+module sky130_hilas_TgateSingle01Part2 (
     
 );
 endmodule
@@ -339,297 +136,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_MCAP2M4
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DECOUP_CAP_01
-`define SKY130_HILAS_DECOUP_CAP_01
-
-/**
- * sky130_hilas_decoup_cap_01: decoupling cap (intended as fill), variant
- *
- * Verilog wrapper for sky130_hilas_decoup_cap_01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_decoup_cap_01 (
-    VPWR,
-    VNB,
-    VPB
-);
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_decoup_cap_01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DECOUP_CAP_01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFET03
-`define SKY130_HILAS_NFET03
-
-/**
- * sky130_hilas_nFET03: None
- *
- * Verilog wrapper for sky130_hilas_nFET03.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFET03 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFET03 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFET03
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_M22M4
-`define SKY130_HILAS_M22M4
-
-/**
- * sky130_hilas_m22m4: m2 to m4 contact
- *
- * Verilog wrapper for sky130_hilas_m22m4.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_m22m4 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_m22m4 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_M22M4
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETMIRROR02
-`define SKY130_HILAS_PFETMIRROR02
-
-/**
- * sky130_hilas_pFETmirror02: second pFET current mirror
- *
- * Verilog wrapper for sky130_hilas_pFETmirror02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmirror02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmirror02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETMIRROR02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01A
-`define SKY130_HILAS_PFETDEVICE01A
-
-/**
- * sky130_hilas_pFETdevice01a: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETMIRROR
-`define SKY130_HILAS_PFETMIRROR
-
-/**
- * sky130_hilas_pFETmirror: pFET current mirror
- *
- * Verilog wrapper for sky130_hilas_pFETmirror.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmirror (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmirror (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETMIRROR
+`endif  // SKY130_HILAS_TGATESINGLE01PART2
 
 
 //--------EOF---------
@@ -682,13 +189,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_POLY2M2
-`define SKY130_HILAS_POLY2M2
+`ifndef SKY130_HILAS_NFET03A
+`define SKY130_HILAS_NFET03A
 
 /**
- * sky130_hilas_poly2m2: polysilicon layer to m2 contact
+ * sky130_hilas_nFET03a: None
  *
- * Verilog wrapper for sky130_hilas_poly2m2.
+ * Verilog wrapper for sky130_hilas_nFET03a.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -701,7 +208,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_poly2m2 (
+module sky130_hilas_nFET03a (
     VNB,
     VPB
 );
@@ -715,7 +222,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_poly2m2 (
+module sky130_hilas_nFET03a (
     
 );
 endmodule
@@ -725,18 +232,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_POLY2M2
+`endif  // SKY130_HILAS_NFET03A
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_WELLCONTACT
-`define SKY130_HILAS_WELLCONTACT
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01
 
 /**
- * sky130_hilas_wellContact: contact to a well block, typically used for contacting tunneling junctions in a well.
+ * sky130_hilas_DAC6TransistorStack01: None
  *
- * Verilog wrapper for sky130_hilas_wellContact.
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -749,7 +256,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_wellContact (
+module sky130_hilas_DAC6TransistorStack01 (
     VNB,
     VPB
 );
@@ -763,7 +270,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_wellContact (
+module sky130_hilas_DAC6TransistorStack01 (
     
 );
 endmodule
@@ -773,106 +280,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_WELLCONTACT
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TA2CELL_NOFG
-`define SKY130_HILAS_TA2CELL_NOFG
-
-/**
- * sky130_hilas_TA2Cell_NoFG: Two transimpedane amplifiers with no floating-gate inputs.
- *
- * Verilog wrapper for sky130_hilas_TA2Cell_NoFG.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_NoFG (
-    COLSEL1,
-    VIN12,
-    VIN21,
-    VIN22,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    VTUN,
-    GATE1,
-    VINJ,
-    VIN11,
-    VGND,
-    VPWR,
-    VNB,
-    VPB
-);
-        inout COLSEL1;
-        inout VIN12;
-        inout VIN21;
-        inout VIN22;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout VIN11;
-        inout VGND;
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_NoFG (
-    COLSEL1,
-    VIN12,
-    VIN21,
-    VIN22,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    VTUN,
-    GATE1,
-    VINJ,
-    VIN11
-);
-        inout COLSEL1;
-        inout VIN12;
-        inout VIN21;
-        inout VIN22;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout VIN11;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TA2CELL_NOFG
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01
 
 
 //--------EOF---------
@@ -992,573 +400,6 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01C
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01C
-
-/**
- * sky130_hilas_DAC6TransistorStack01c: None
- *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01c.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01c (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01c (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01C
-
-
-//--------EOF---------
-
-`ifndef M12M3
-`define M12M3
-
-/**
- * m12m3: 
- *
- * Verilog wrapper for m12m3.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module m12m3 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module m12m3 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // M12M3
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGCHARACTERIZATION01
-`define SKY130_HILAS_FGCHARACTERIZATION01
-
-/**
- * sky130_hilas_FGcharacterization01: FG test strucure that uses a capacitor around a transconductance amplifier
- *
- * Verilog wrapper for sky130_hilas_FGcharacterization01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGcharacterization01 (
-    VTUN,
-    GATE1,
-    GATE3,
-    VTUNOVERLAP01,
-    GATE2,
-    GATE4,
-    LARGECAPACITOR,
-    VINJ,
-    OUTPUT,
-    VREF,
-    VBIAS,
-    DRAIN1,
-    SOURCE1,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VTUN;
-        inout GATE1;
-        inout GATE3;
-        inout VTUNOVERLAP01;
-        inout GATE2;
-        inout GATE4;
-        inout LARGECAPACITOR;
-        inout VINJ;
-        inout OUTPUT;
-        inout VREF;
-        inout VBIAS;
-        inout DRAIN1;
-        inout SOURCE1;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGcharacterization01 (
-    VTUN,
-    GATE1,
-    GATE3,
-    VTUNOVERLAP01,
-    GATE2,
-    GATE4,
-    LARGECAPACITOR,
-    VINJ,
-    OUTPUT,
-    VREF,
-    VBIAS,
-    DRAIN1,
-    SOURCE1
-);
-        inout VTUN;
-        inout GATE1;
-        inout GATE3;
-        inout VTUNOVERLAP01;
-        inout GATE2;
-        inout GATE4;
-        inout LARGECAPACITOR;
-        inout VINJ;
-        inout OUTPUT;
-        inout VREF;
-        inout VBIAS;
-        inout DRAIN1;
-        inout SOURCE1;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGCHARACTERIZATION01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_INVERT01
-`define SKY130_HILAS_INVERT01
-
-/**
- * sky130_hilas_invert01: None
- *
- * Verilog wrapper for sky130_hilas_invert01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_invert01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_invert01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_INVERT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGVARACTORCAPACITOR02
-`define SKY130_HILAS_FGVARACTORCAPACITOR02
-
-/**
- * sky130_hilas_FGVaractorCapacitor02: variant 2, varactor cap for floating-gate charge storage
- *
- * Verilog wrapper for sky130_hilas_FGVaractorCapacitor02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGVARACTORCAPACITOR02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TACOREBLOCK
-`define SKY130_HILAS_TACOREBLOCK
-
-/**
- * sky130_hilas_TACoreBlock: None
- *
- * Verilog wrapper for sky130_hilas_TACoreBlock.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TACOREBLOCK
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_OVERLAPCAP01
-`define SKY130_HILAS_OVERLAPCAP01
-
-/**
- * sky130_hilas_overlapCap01: overlap capacitor based capacitor
- *
- * Verilog wrapper for sky130_hilas_overlapCap01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_OVERLAPCAP01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DRAINSELECT01
-`define SKY130_HILAS_DRAINSELECT01
-
-/**
- * sky130_hilas_drainSelect01: multiplexor for drain selection for 4 drain lines, pitch matched
- *
- * Verilog wrapper for sky130_hilas_drainSelect01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_drainSelect01 (
-    DRAIN3,
-    VINJ,
-    DRAIN_MUX,
-    SELECT2,
-    SELECT1,
-    SELECT3,
-    SELECT4,
-    VGND,
-    VNB,
-    VPB
-);
-        inout DRAIN3;
-        inout VINJ;
-        inout DRAIN_MUX;
-        inout SELECT2;
-        inout SELECT1;
-        inout SELECT3;
-        inout SELECT4;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_drainSelect01 (
-    DRAIN3,
-    VINJ,
-    DRAIN_MUX,
-    SELECT2,
-    SELECT1,
-    SELECT3,
-    SELECT4
-);
-        inout DRAIN3;
-        inout VINJ;
-        inout DRAIN_MUX;
-        inout SELECT2;
-        inout SELECT1;
-        inout SELECT3;
-        inout SELECT4;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DRAINSELECT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGTRANS2X1CELL
-`define SKY130_HILAS_FGTRANS2X1CELL
-
-/**
- * sky130_hilas_FGtrans2x1cell: None
- *
- * Verilog wrapper for sky130_hilas_FGtrans2x1cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGtrans2x1cell (
-    COLSEL1,
-    VINJ,
-    DRAIN1,
-    DRAIN2,
-    PROG,
-    RUN,
-    VIN2,
-    VIN1,
-    GATE1,
-    VTUN,
-    COL1,
-    ROW1,
-    ROW2,
-    VGND,
-    VNB,
-    VPB
-);
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout PROG;
-        inout RUN;
-        inout VIN2;
-        inout VIN1;
-        inout GATE1;
-        inout VTUN;
-        inout COL1;
-        inout ROW1;
-        inout ROW2;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGtrans2x1cell (
-    COLSEL1,
-    VINJ,
-    DRAIN1,
-    DRAIN2,
-    PROG,
-    RUN,
-    VIN2,
-    VIN1,
-    GATE1,
-    VTUN,
-    COL1,
-    ROW1,
-    ROW2
-);
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout PROG;
-        inout RUN;
-        inout VIN2;
-        inout VIN1;
-        inout GATE1;
-        inout VTUN;
-        inout COL1;
-        inout ROW1;
-        inout ROW2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGTRANS2X1CELL
-
-
-//--------EOF---------
-
 `ifndef SKY130_HILAS_WTA4STAGE01
 `define SKY130_HILAS_WTA4STAGE01
 
@@ -1607,13 +448,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_CAPACITORSIZE01
-`define SKY130_HILAS_CAPACITORSIZE01
+`ifndef SKY130_HILAS_PFETMED
+`define SKY130_HILAS_PFETMED
 
 /**
- * sky130_hilas_capacitorSize01: smallest cap
+ * sky130_hilas_pFETmed: Medium-sized (W/L=10) pFET transistor
  *
- * Verilog wrapper for sky130_hilas_capacitorSize01.
+ * Verilog wrapper for sky130_hilas_pFETmed.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -1626,167 +467,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_capacitorSize01 (
-    CAPTERM02,
-    CAPTERM01,
-    VNB,
-    VPB
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorSize01 (
-    CAPTERM02,
-    CAPTERM01
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPACITORSIZE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC4X2CELL
-`define SKY130_HILAS_SWC4X2CELL
-
-/**
- * sky130_hilas_swc4x2cell: 4x2 array of FG switch cell, Varactor capacitor cell
- *
- * Verilog wrapper for sky130_hilas_swc4x2cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x2cell (
-    DRAIN1,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4,
-    GATE1,
-    GATE2,
-    GATESELECT1,
-    GATESELECT2,
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VINJ,
-    VTUN,
-    VGND,
-    VNB,
-    VPB
-);
-        inout DRAIN1;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout GATE1;
-        inout GATE2;
-        inout GATESELECT1;
-        inout GATESELECT2;
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VINJ;
-        inout VTUN;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x2cell (
-    DRAIN1,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4,
-    GATE1,
-    GATE2,
-    GATESELECT1,
-    GATESELECT2,
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VINJ,
-    VTUN
-);
-        inout DRAIN1;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout GATE1;
-        inout GATE2;
-        inout GATESELECT1;
-        inout GATESELECT2;
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VINJ;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X2CELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NMIRROR03
-`define SKY130_HILAS_NMIRROR03
-
-/**
- * sky130_hilas_nMirror03: None
- *
- * Verilog wrapper for sky130_hilas_nMirror03.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nMirror03 (
+module sky130_hilas_pFETmed (
     VNB,
     VPB
 );
@@ -1800,7 +481,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nMirror03 (
+module sky130_hilas_pFETmed (
     
 );
 endmodule
@@ -1810,648 +491,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NMIRROR03
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01
-
-/**
- * sky130_hilas_DAC6TransistorStack01: None
- *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TACOREBLOCK2
-`define SKY130_HILAS_TACOREBLOCK2
-
-/**
- * sky130_hilas_TACoreBlock2: None
- *
- * Verilog wrapper for sky130_hilas_TACoreBlock2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TACoreBlock2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TACOREBLOCK2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETMIRRORPAIRS
-`define SKY130_HILAS_NFETMIRRORPAIRS
-
-/**
- * sky130_hilas_nFETmirrorPairs: pairs of nFET current mirrors
- *
- * Verilog wrapper for sky130_hilas_nFETmirrorPairs.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETMIRRORPAIRS
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_HORIZPCELL01
-`define SKY130_HILAS_HORIZPCELL01
-
-/**
- * sky130_hilas_horizPcell01: None
- *
- * Verilog wrapper for sky130_hilas_horizPcell01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizPcell01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizPcell01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_HORIZPCELL01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETMED
-`define SKY130_HILAS_NFETMED
-
-/**
- * sky130_hilas_nFETmed: None
- *
- * Verilog wrapper for sky130_hilas_nFETmed.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmed (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmed (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETMED
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TOPPROTECTION
-`define SKY130_HILAS_TOPPROTECTION
-
-/**
- * sky130_hilas_TopProtection: 
- *
- * Verilog wrapper for sky130_hilas_TopProtection.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TopProtection (
-    ANALOG00,
-    ANALOG01,
-    ANALOG02,
-    ANALOG03,
-    ANALOG04,
-    ANALOG05,
-    ANALOG06,
-    ANALOG07,
-    ANALOG08,
-    ANALOG09,
-    ANALOG10,
-    PIN1,
-    PIN2,
-    PIN3,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    VTUN,
-    VNB,
-    VPB
-);
-        inout ANALOG00;
-        inout ANALOG01;
-        inout ANALOG02;
-        inout ANALOG03;
-        inout ANALOG04;
-        inout ANALOG05;
-        inout ANALOG06;
-        inout ANALOG07;
-        inout ANALOG08;
-        inout ANALOG09;
-        inout ANALOG10;
-        inout PIN1;
-        inout PIN2;
-        inout PIN3;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout VTUN;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TopProtection (
-    ANALOG00,
-    ANALOG01,
-    ANALOG02,
-    ANALOG03,
-    ANALOG04,
-    ANALOG05,
-    ANALOG06,
-    ANALOG07,
-    ANALOG08,
-    ANALOG09,
-    ANALOG10,
-    PIN1,
-    PIN2,
-    PIN3,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    VTUN
-);
-        inout ANALOG00;
-        inout ANALOG01;
-        inout ANALOG02;
-        inout ANALOG03;
-        inout ANALOG04;
-        inout ANALOG05;
-        inout ANALOG06;
-        inout ANALOG07;
-        inout ANALOG08;
-        inout ANALOG09;
-        inout ANALOG10;
-        inout PIN1;
-        inout PIN2;
-        inout PIN3;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TOPPROTECTION
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC2X2VARACTOR
-`define SKY130_HILAS_SWC2X2VARACTOR
-
-/**
- * sky130_hilas_swc2x2varactor: ??  Is this part of the library?
- *
- * Verilog wrapper for sky130_hilas_swc2x2varactor.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc2x2varactor (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc2x2varactor (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC2X2VARACTOR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_LEVELSHIFT4INPUTUP
-`define SKY130_HILAS_LEVELSHIFT4INPUTUP
-
-/**
- * sky130_hilas_LevelShift4InputUp: 4-channel level shifter
- *
- * Verilog wrapper for sky130_hilas_LevelShift4InputUp.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LevelShift4InputUp (
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
-    OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
-        inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LevelShift4InputUp (
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
-    OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4
-);
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
-        inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_LEVELSHIFT4INPUTUP
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01
-`define SKY130_HILAS_PFETDEVICE01
-
-/**
- * sky130_hilas_pFETdevice01: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TA2SIGNALBIASCELL
-`define SKY130_HILAS_TA2SIGNALBIASCELL
-
-/**
- * sky130_hilas_TA2SignalBiasCell: None
- *
- * Verilog wrapper for sky130_hilas_TA2SignalBiasCell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2SignalBiasCell (
-    VOUT_AMP2,
-    VOUT_AMP1,
-    VIN22,
-    VIN21,
-    VIN11,
-    VIN12,
-    VBIAS2,
-    VBIAS1,
-    VGND,
-    VPWR,
-    VNB,
-    VPB
-);
-        inout VOUT_AMP2;
-        inout VOUT_AMP1;
-        inout VIN22;
-        inout VIN21;
-        inout VIN11;
-        inout VIN12;
-        inout VBIAS2;
-        inout VBIAS1;
-        inout VGND;
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2SignalBiasCell (
-    VOUT_AMP2,
-    VOUT_AMP1,
-    VIN22,
-    VIN21,
-    VIN11,
-    VIN12,
-    VBIAS2,
-    VBIAS1
-);
-        inout VOUT_AMP2;
-        inout VOUT_AMP1;
-        inout VIN22;
-        inout VIN21;
-        inout VIN11;
-        inout VIN12;
-        inout VBIAS2;
-        inout VBIAS1;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TA2SIGNALBIASCELL
+`endif  // SKY130_HILAS_PFETMED
 
 
 //--------EOF---------
@@ -2511,6 +551,261 @@
 
 //--------EOF---------
 
+`ifndef SKY130_HILAS_SWC4X2CELLOVERLAP
+`define SKY130_HILAS_SWC4X2CELLOVERLAP
+
+/**
+ * sky130_hilas_swc4x2cellOverlap: Core switch cell, built with overlap capacitor
+ *
+ * Verilog wrapper for sky130_hilas_swc4x2cellOverlap.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cellOverlap (
+    VERT1,
+    HORIZ1,
+    DRAIN1,
+    HORIZ2,
+    DRAIN2,
+    DRAIN3,
+    HORIZ3,
+    HORIZ4,
+    DRAIN4,
+    VINJ,
+    GATESELECT1,
+    VERT2,
+    GATESELECT2,
+    GATE2,
+    GATE1,
+    VTUN,
+    VNB,
+    VPB
+);
+        inout VERT1;
+        inout HORIZ1;
+        inout DRAIN1;
+        inout HORIZ2;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout HORIZ3;
+        inout HORIZ4;
+        inout DRAIN4;
+        inout VINJ;
+        inout GATESELECT1;
+        inout VERT2;
+        inout GATESELECT2;
+        inout GATE2;
+        inout GATE1;
+        inout VTUN;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cellOverlap (
+    VERT1,
+    HORIZ1,
+    DRAIN1,
+    HORIZ2,
+    DRAIN2,
+    DRAIN3,
+    HORIZ3,
+    HORIZ4,
+    DRAIN4,
+    VINJ,
+    GATESELECT1,
+    VERT2,
+    GATESELECT2,
+    GATE2,
+    GATE1,
+    VTUN
+);
+        inout VERT1;
+        inout HORIZ1;
+        inout DRAIN1;
+        inout HORIZ2;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout HORIZ3;
+        inout HORIZ4;
+        inout DRAIN4;
+        inout VINJ;
+        inout GATESELECT1;
+        inout VERT2;
+        inout GATESELECT2;
+        inout GATE2;
+        inout GATE1;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X2CELLOVERLAP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLY2LI
+`define SKY130_HILAS_POLY2LI
+
+/**
+ * sky130_hilas_poly2li: polysilicon layer to li contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2li.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2li (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2li (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_POLY2LI
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DUALTACORE01
+`define SKY130_HILAS_DUALTACORE01
+
+/**
+ * sky130_hilas_DualTACore01: None
+ *
+ * Verilog wrapper for sky130_hilas_DualTACore01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DualTACore01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DualTACore01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DUALTACORE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATEVINJ01
+`define SKY130_HILAS_TGATEVINJ01
+
+/**
+ * sky130_hilas_TgateVinj01: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateVinj01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateVinj01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateVinj01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATEVINJ01
+
+
+//--------EOF---------
+
 `ifndef USER_ANALOG_PROJECT_WRAPPER
 `define USER_ANALOG_PROJECT_WRAPPER
 
@@ -5210,13 +3505,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_POLY2LI
-`define SKY130_HILAS_POLY2LI
+`ifndef SKY130_HILAS_DAC6BIT01
+`define SKY130_HILAS_DAC6BIT01
 
 /**
- * sky130_hilas_poly2li: polysilicon layer to li contact
+ * sky130_hilas_DAC6bit01: None
  *
- * Verilog wrapper for sky130_hilas_poly2li.
+ * Verilog wrapper for sky130_hilas_DAC6bit01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -5229,7 +3524,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_poly2li (
+module sky130_hilas_DAC6bit01 (
     VNB,
     VPB
 );
@@ -5243,7 +3538,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_poly2li (
+module sky130_hilas_DAC6bit01 (
     
 );
 endmodule
@@ -5253,18 +3548,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_POLY2LI
+`endif  // SKY130_HILAS_DAC6BIT01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_TGATESINGLE01
-`define SKY130_HILAS_TGATESINGLE01
+`ifndef SKY130_HILAS_SWC2X2VARACTOR
+`define SKY130_HILAS_SWC2X2VARACTOR
 
 /**
- * sky130_hilas_TgateSingle01: None
+ * sky130_hilas_swc2x2varactor: ??  Is this part of the library?
  *
- * Verilog wrapper for sky130_hilas_TgateSingle01.
+ * Verilog wrapper for sky130_hilas_swc2x2varactor.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -5277,7 +3572,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateSingle01 (
+module sky130_hilas_swc2x2varactor (
     VNB,
     VPB
 );
@@ -5291,7 +3586,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateSingle01 (
+module sky130_hilas_swc2x2varactor (
     
 );
 endmodule
@@ -5301,18 +3596,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_TGATESINGLE01
+`endif  // SKY130_HILAS_SWC2X2VARACTOR
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP2
-`define SKY130_HILAS_SWC4X1CELLOVERLAP2
+`ifndef SKY130_HILAS_LI2M2
+`define SKY130_HILAS_LI2M2
 
 /**
- * sky130_hilas_swc4x1cellOverlap2: 4x1 analog mux with overlap
+ * sky130_hilas_li2m2: local interconnect to m2 contact
  *
- * Verilog wrapper for sky130_hilas_swc4x1cellOverlap2.
+ * Verilog wrapper for sky130_hilas_li2m2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -5325,7 +3620,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_swc4x1cellOverlap2 (
+module sky130_hilas_li2m2 (
     VNB,
     VPB
 );
@@ -5339,7 +3634,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_swc4x1cellOverlap2 (
+module sky130_hilas_li2m2 (
     
 );
 endmodule
@@ -5349,660 +3644,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_RESISTOR01
-`define SKY130_HILAS_RESISTOR01
-
-/**
- * sky130_hilas_resistor01: 
- *
- * Verilog wrapper for sky130_hilas_resistor01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_resistor01 (
-    TERM1,
-    TERM2,
-    VGND,
-    VNB,
-    VPB
-);
-        inout TERM1;
-        inout TERM2;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_resistor01 (
-    TERM1,
-    TERM2
-);
-        inout TERM1;
-        inout TERM2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_RESISTOR01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DOUBLETGATE01
-`define SKY130_HILAS_DOUBLETGATE01
-
-/**
- * sky130_hilas_DoubleTGate01: 2x1 array of transmission gates
- *
- * Verilog wrapper for sky130_hilas_DoubleTGate01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DoubleTGate01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DoubleTGate01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DOUBLETGATE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01A
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01A
-
-/**
- * sky130_hilas_DAC6TransistorStack01a: None
- *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_POLY2M1
-`define SKY130_HILAS_POLY2M1
-
-/**
- * sky130_hilas_poly2m1: polysilicon layer to m1 contact
- *
- * Verilog wrapper for sky130_hilas_poly2m1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2m1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_poly2m1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_POLY2M1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_STEPUPDIGITALPART1
-`define SKY130_HILAS_STEPUPDIGITALPART1
-
-/**
- * sky130_hilas_StepUpDigitalPart1: step-up level shifter part
- *
- * Verilog wrapper for sky130_hilas_StepUpDigitalPart1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigitalPart1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigitalPart1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_STEPUPDIGITALPART1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC4X1BIASCELL
-`define SKY130_HILAS_SWC4X1BIASCELL
-
-/**
- * sky130_hilas_swc4x1BiasCell: 4x1 array of FG switch cell configured pFET as current sources
- *
- * Verilog wrapper for sky130_hilas_swc4x1BiasCell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1BiasCell (
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VTUN,
-    GATE1,
-    VINJ,
-    DRAIN3,
-    DRAIN4,
-    DRAIN1,
-    DRAIN2,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1BiasCell (
-    ROW1,
-    ROW2,
-    ROW3,
-    ROW4,
-    VTUN,
-    GATE1,
-    VINJ,
-    DRAIN3,
-    DRAIN4,
-    DRAIN1,
-    DRAIN2
-);
-        inout ROW1;
-        inout ROW2;
-        inout ROW3;
-        inout ROW4;
-        inout VTUN;
-        inout GATE1;
-        inout VINJ;
-        inout DRAIN3;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout DRAIN2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X1BIASCELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_WTASINGLESTAGE01
-`define SKY130_HILAS_WTASINGLESTAGE01
-
-/**
- * sky130_hilas_WTAsinglestage01: None
- *
- * Verilog wrapper for sky130_hilas_WTAsinglestage01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAsinglestage01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAsinglestage01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_WTASINGLESTAGE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATESINGLE01PART2
-`define SKY130_HILAS_TGATESINGLE01PART2
-
-/**
- * sky130_hilas_TgateSingle01Part2: None
- *
- * Verilog wrapper for sky130_hilas_TgateSingle01Part2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateSingle01Part2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateSingle01Part2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATESINGLE01PART2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TA2CELL_1FG
-`define SKY130_HILAS_TA2CELL_1FG
-
-/**
- * sky130_hilas_TA2Cell_1FG: Two transimpedance amps with one (of two) amplifiers using floating-gate
-  inputs. FG amplifier with wide linear range.
- *
- * Verilog wrapper for sky130_hilas_TA2Cell_1FG.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_1FG (
-    VIN12,
-    VIN11,
-    VIN21,
-    VIN22,
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    COLSEL2,
-    GATE2,
-    GATE1,
-    COLSEL1,
-    VTUN,
-    VPWR,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VIN12;
-        inout VIN11;
-        inout VIN21;
-        inout VIN22;
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout COLSEL2;
-        inout GATE2;
-        inout GATE1;
-        inout COLSEL1;
-        inout VTUN;
-        inout VPWR;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TA2Cell_1FG (
-    VIN12,
-    VIN11,
-    VIN21,
-    VIN22,
-    VINJ,
-    OUTPUT1,
-    OUTPUT2,
-    DRAIN1,
-    DRAIN2,
-    COLSEL2,
-    GATE2,
-    GATE1,
-    COLSEL1,
-    VTUN
-);
-        inout VIN12;
-        inout VIN11;
-        inout VIN21;
-        inout VIN22;
-        inout VINJ;
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout DRAIN1;
-        inout DRAIN2;
-        inout COLSEL2;
-        inout GATE2;
-        inout GATE1;
-        inout COLSEL1;
-        inout VTUN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TA2CELL_1FG
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_POLYRESISTORGND
-`define SKY130_HILAS_POLYRESISTORGND
-
-/**
- * sky130_hilas_polyresistorGND: protective current-limiting resistor to ground
- *
- * Verilog wrapper for sky130_hilas_polyresistorGND.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_polyresistorGND (
-    INPUT,
-    OUTPUT,
-    VGND,
-    VNB,
-    VPB
-);
-        inout INPUT;
-        inout OUTPUT;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_polyresistorGND (
-    INPUT,
-    OUTPUT
-);
-        inout INPUT;
-        inout OUTPUT;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_POLYRESISTORGND
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP
-`define SKY130_HILAS_SWC4X1CELLOVERLAP
-
-/**
- * sky130_hilas_swc4x1cellOverlap: 4x1 array of FG switch cell using overlap capacitors
- *
- * Verilog wrapper for sky130_hilas_swc4x1cellOverlap.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1cellOverlap (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_swc4x1cellOverlap (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP
+`endif  // SKY130_HILAS_LI2M2
 
 
 //--------EOF---------
@@ -6266,13 +3908,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DECOUPVINJ01
-`define SKY130_HILAS_DECOUPVINJ01
+`ifndef SKY130_HILAS_CAPACITORARRAY01
+`define SKY130_HILAS_CAPACITORARRAY01
 
 /**
- * sky130_hilas_DecoupVinj01: 
+ * sky130_hilas_capacitorArray01: selectable capacitor array
  *
- * Verilog wrapper for sky130_hilas_DecoupVinj01.
+ * Verilog wrapper for sky130_hilas_capacitorArray01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -6285,11 +3927,31 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DecoupVinj01 (
+module sky130_hilas_capacitorArray01 (
+    CAPTERM2,
+    CAPTERM1,
+    VINJ,
+    GATESELECT,
+    VTUN,
+    GATE,
+    DRAIN2,
+    DRAIN1,
+    DRAIN4,
+    DRAIN3,
     VGND,
     VNB,
     VPB
 );
+        inout CAPTERM2;
+        inout CAPTERM1;
+        inout VINJ;
+        inout GATESELECT;
+        inout VTUN;
+        inout GATE;
+        inout DRAIN2;
+        inout DRAIN1;
+        inout DRAIN4;
+        inout DRAIN3;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -6301,7 +3963,74 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DecoupVinj01 (
+module sky130_hilas_capacitorArray01 (
+    CAPTERM2,
+    CAPTERM1,
+    VINJ,
+    GATESELECT,
+    VTUN,
+    GATE,
+    DRAIN2,
+    DRAIN1,
+    DRAIN4,
+    DRAIN3
+);
+        inout CAPTERM2;
+        inout CAPTERM1;
+        inout VINJ;
+        inout GATESELECT;
+        inout VTUN;
+        inout GATE;
+        inout DRAIN2;
+        inout DRAIN1;
+        inout DRAIN4;
+        inout DRAIN3;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPACITORARRAY01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01A
+`define SKY130_HILAS_PFETDEVICE01A
+
+/**
+ * sky130_hilas_pFETdevice01a: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01a (
     
 );
 endmodule
@@ -6311,18 +4040,19 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DECOUPVINJ01
+`endif  // SKY130_HILAS_PFETDEVICE01A
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_FGBIAS2X1CELL
-`define SKY130_HILAS_FGBIAS2X1CELL
+`ifndef SKY130_HILAS_TA2CELL_1FG
+`define SKY130_HILAS_TA2CELL_1FG
 
 /**
- * sky130_hilas_FGBias2x1cell: None
+ * sky130_hilas_TA2Cell_1FG: Two transimpedance amps with one (of two) amplifiers using floating-gate
+  inputs. FG amplifier with wide linear range.
  *
- * Verilog wrapper for sky130_hilas_FGBias2x1cell.
+ * Verilog wrapper for sky130_hilas_TA2Cell_1FG.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -6335,13 +4065,1303 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_FGBias2x1cell (
-    DRAIN1,
-    DRAIN4,
-    GATECOL,
-    GATE_CONTROL,
+module sky130_hilas_TA2Cell_1FG (
+    VIN12,
+    VIN11,
+    VIN21,
+    VIN22,
+    VINJ,
     OUTPUT1,
     OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    COLSEL2,
+    GATE2,
+    GATE1,
+    COLSEL1,
+    VTUN,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VIN12;
+        inout VIN11;
+        inout VIN21;
+        inout VIN22;
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout COLSEL2;
+        inout GATE2;
+        inout GATE1;
+        inout COLSEL1;
+        inout VTUN;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG (
+    VIN12,
+    VIN11,
+    VIN21,
+    VIN22,
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    COLSEL2,
+    GATE2,
+    GATE1,
+    COLSEL1,
+    VTUN
+);
+        inout VIN12;
+        inout VIN11;
+        inout VIN21;
+        inout VIN22;
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout COLSEL2;
+        inout GATE2;
+        inout GATE1;
+        inout COLSEL1;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TA2CELL_1FG
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TUNVARACTORCAPCITOR
+`define SKY130_HILAS_TUNVARACTORCAPCITOR
+
+/**
+ * sky130_hilas_TunVaractorCapcitor: Tunneling capacitor using a standard varactor capacitor
+ *
+ * Verilog wrapper for sky130_hilas_TunVaractorCapcitor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunVaractorCapcitor (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunVaractorCapcitor (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TUNVARACTORCAPCITOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORCAPACITOR
+`define SKY130_HILAS_FGVARACTORCAPACITOR
+
+/**
+ * sky130_hilas_FGVaractorCapacitor: varactor cap for floating-gate charge storage
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorCapacitor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGVARACTORCAPACITOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TACOREBLOCK2
+`define SKY130_HILAS_TACOREBLOCK2
+
+/**
+ * sky130_hilas_TACoreBlock2: None
+ *
+ * Verilog wrapper for sky130_hilas_TACoreBlock2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TACOREBLOCK2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LI2M1
+`define SKY130_HILAS_LI2M1
+
+/**
+ * sky130_hilas_li2m1: local interconnect to m1 contact
+ *
+ * Verilog wrapper for sky130_hilas_li2m1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_LI2M1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+`define SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+
+/**
+ * sky130_hilas_FGBiasWeakGate2x1cell: 2x1 array of FG switch cells configured as pFET current sources with weak capacitive gate inputs
+ *
+ * Verilog wrapper for sky130_hilas_FGBiasWeakGate2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBiasWeakGate2x1cell (
+    DRAIN1,
+    VIN11,
+    ROW1,
+    ROW2,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    VTUN,
+    DRAIN2,
+    VIN12,
+    COMMONSOURCE,
+    VGND,
+    VNB,
+    VPB
+);
+        inout DRAIN1;
+        inout VIN11;
+        inout ROW1;
+        inout ROW2;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout VTUN;
+        inout DRAIN2;
+        inout VIN12;
+        inout COMMONSOURCE;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBiasWeakGate2x1cell (
+    DRAIN1,
+    VIN11,
+    ROW1,
+    ROW2,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    VTUN,
+    DRAIN2,
+    VIN12,
+    COMMONSOURCE
+);
+        inout DRAIN1;
+        inout VIN11;
+        inout ROW1;
+        inout ROW2;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout VTUN;
+        inout DRAIN2;
+        inout VIN12;
+        inout COMMONSOURCE;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMIRRORPAIRS
+`define SKY130_HILAS_NFETMIRRORPAIRS
+
+/**
+ * sky130_hilas_nFETmirrorPairs: pairs of nFET current mirrors
+ *
+ * Verilog wrapper for sky130_hilas_nFETmirrorPairs.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETMIRRORPAIRS
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DOUBLETGATE01
+`define SKY130_HILAS_DOUBLETGATE01
+
+/**
+ * sky130_hilas_DoubleTGate01: 2x1 array of transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_DoubleTGate01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DoubleTGate01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DoubleTGate01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DOUBLETGATE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01BA
+`define SKY130_HILAS_PFETDEVICE01BA
+
+/**
+ * sky130_hilas_pFETdevice01ba: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01ba.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01ba (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01ba (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01BA
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_INVERT01
+`define SKY130_HILAS_INVERT01
+
+/**
+ * sky130_hilas_invert01: None
+ *
+ * Verilog wrapper for sky130_hilas_invert01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_invert01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_invert01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_INVERT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+`define SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+
+/**
+ * sky130_hilas_FGHugeVaractorCapacitor01: one large varactor cap
+ *
+ * Verilog wrapper for sky130_hilas_FGHugeVaractorCapacitor01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGHugeVaractorCapacitor01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGHugeVaractorCapacitor01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP
+`define SKY130_HILAS_SWC4X1CELLOVERLAP
+
+/**
+ * sky130_hilas_swc4x1cellOverlap: 4x1 array of FG switch cell using overlap capacitors
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1cellOverlap.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETLARGEPART1
+`define SKY130_HILAS_PFETLARGEPART1
+
+/**
+ * sky130_hilas_pFETLargePart1: Part of the W/L=100 pFET transistor
+ *
+ * Verilog wrapper for sky130_hilas_pFETLargePart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLargePart1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLargePart1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETLARGEPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_M22M4
+`define SKY130_HILAS_M22M4
+
+/**
+ * sky130_hilas_m22m4: m2 to m4 contact
+ *
+ * Verilog wrapper for sky130_hilas_m22m4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m22m4 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m22m4 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_M22M4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORTUNNELCAP01
+`define SKY130_HILAS_FGVARACTORTUNNELCAP01
+
+/**
+ * sky130_hilas_FGVaractorTunnelCap01: Tunneling cpacitor using a standard varactor capacitor
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorTunnelCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorTunnelCap01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorTunnelCap01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGVARACTORTUNNELCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETLARGE
+`define SKY130_HILAS_NFETLARGE
+
+/**
+ * sky130_hilas_nFETLarge: Single Large (W//L=100) nFET Transistor
+ *
+ * Verilog wrapper for sky130_hilas_nFETLarge.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN,
+    VGND,
+    VNB,
+    VPB
+);
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN
+);
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETLARGE
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZPCELL01
+`define SKY130_HILAS_HORIZPCELL01
+
+/**
+ * sky130_hilas_horizPcell01: None
+ *
+ * Verilog wrapper for sky130_hilas_horizPcell01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizPcell01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizPcell01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_HORIZPCELL01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETLARGE
+`define SKY130_HILAS_PFETLARGE
+
+/**
+ * sky130_hilas_pFETLarge: Single Large (W/L=100) pFET Transistor
+ *
+ * Verilog wrapper for sky130_hilas_pFETLarge.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN,
+    WELL,
+    VNB,
+    VPB
+);
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+        inout WELL;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLarge (
+    GATE,
+    SOURCE,
+    DRAIN,
+    WELL
+);
+        inout GATE;
+        inout SOURCE;
+        inout DRAIN;
+        inout WELL;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETLARGE
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLYRESISTORGND
+`define SKY130_HILAS_POLYRESISTORGND
+
+/**
+ * sky130_hilas_polyresistorGND: protective current-limiting resistor to ground
+ *
+ * Verilog wrapper for sky130_hilas_polyresistorGND.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_polyresistorGND (
+    INPUT,
+    OUTPUT,
+    VGND,
+    VNB,
+    VPB
+);
+        inout INPUT;
+        inout OUTPUT;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_polyresistorGND (
+    INPUT,
+    OUTPUT
+);
+        inout INPUT;
+        inout OUTPUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_POLYRESISTORGND
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTASINGLESTAGE01
+`define SKY130_HILAS_WTASINGLESTAGE01
+
+/**
+ * sky130_hilas_WTAsinglestage01: None
+ *
+ * Verilog wrapper for sky130_hilas_WTAsinglestage01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAsinglestage01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAsinglestage01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_WTASINGLESTAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LEVELSHIFT4INPUTUP
+`define SKY130_HILAS_LEVELSHIFT4INPUTUP
+
+/**
+ * sky130_hilas_LevelShift4InputUp: 4-channel level shifter
+ *
+ * Verilog wrapper for sky130_hilas_LevelShift4InputUp.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LevelShift4InputUp (
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LevelShift4InputUp (
+    VINJ,
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4
+);
+        inout VINJ;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_LEVELSHIFT4INPUTUP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMED
+`define SKY130_HILAS_NFETMED
+
+/**
+ * sky130_hilas_nFETmed: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETmed.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmed (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmed (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETMED
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TACOREBLOCK
+`define SKY130_HILAS_TACOREBLOCK
+
+/**
+ * sky130_hilas_TACoreBlock: None
+ *
+ * Verilog wrapper for sky130_hilas_TACoreBlock.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TACOREBLOCK
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X2CELL
+`define SKY130_HILAS_SWC4X2CELL
+
+/**
+ * sky130_hilas_swc4x2cell: 4x2 array of FG switch cell, Varactor capacitor cell
+ *
+ * Verilog wrapper for sky130_hilas_swc4x2cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cell (
+    DRAIN1,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4,
+    GATE1,
+    GATE2,
+    GATESELECT1,
+    GATESELECT2,
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
     VINJ,
     VTUN,
     VGND,
@@ -6349,11 +5369,17 @@
     VPB
 );
         inout DRAIN1;
+        inout DRAIN2;
+        inout DRAIN3;
         inout DRAIN4;
-        inout GATECOL;
-        inout GATE_CONTROL;
-        inout OUTPUT1;
-        inout OUTPUT2;
+        inout GATE1;
+        inout GATE2;
+        inout GATESELECT1;
+        inout GATESELECT2;
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
         inout VINJ;
         inout VTUN;
         inout VGND;
@@ -6367,22 +5393,34 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_FGBias2x1cell (
+module sky130_hilas_swc4x2cell (
     DRAIN1,
+    DRAIN2,
+    DRAIN3,
     DRAIN4,
-    GATECOL,
-    GATE_CONTROL,
-    OUTPUT1,
-    OUTPUT2,
+    GATE1,
+    GATE2,
+    GATESELECT1,
+    GATESELECT2,
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
     VINJ,
     VTUN
 );
         inout DRAIN1;
+        inout DRAIN2;
+        inout DRAIN3;
         inout DRAIN4;
-        inout GATECOL;
-        inout GATE_CONTROL;
-        inout OUTPUT1;
-        inout OUTPUT2;
+        inout GATE1;
+        inout GATE2;
+        inout GATESELECT1;
+        inout GATESELECT2;
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
         inout VINJ;
         inout VTUN;
 endmodule
@@ -6392,7 +5430,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_FGBIAS2X1CELL
+`endif  // SKY130_HILAS_SWC4X2CELL
 
 
 //--------EOF---------
@@ -6522,13 +5560,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETDEVICE01B
-`define SKY130_HILAS_PFETDEVICE01B
+`ifndef SKY130_HILAS_DRAINSELECT01
+`define SKY130_HILAS_DRAINSELECT01
 
 /**
- * sky130_hilas_pFETdevice01b: pFET transistor used in DAC block
+ * sky130_hilas_drainSelect01: multiplexor for drain selection for 4 drain lines, pitch matched
  *
- * Verilog wrapper for sky130_hilas_pFETdevice01b.
+ * Verilog wrapper for sky130_hilas_drainSelect01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -6541,532 +5579,25 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETdevice01b (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01b (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01B
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETMIRRORPAIRS2
-`define SKY130_HILAS_NFETMIRRORPAIRS2
-
-/**
- * sky130_hilas_nFETmirrorPairs2: None
- *
- * Verilog wrapper for sky130_hilas_nFETmirrorPairs2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETmirrorPairs2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETMIRRORPAIRS2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NDIFFTHOXCONTACT
-`define SKY130_HILAS_NDIFFTHOXCONTACT
-
-/**
- * sky130_hilas_nDiffThOxContact: None
- *
- * Verilog wrapper for sky130_hilas_nDiffThOxContact.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nDiffThOxContact (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nDiffThOxContact (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NDIFFTHOXCONTACT
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DAC5BIT01
-`define SKY130_HILAS_DAC5BIT01
-
-/**
- * sky130_hilas_DAC5bit01: 5-bit digital-to-analog converter (under 6.05um at the moment; thinking through expansion to 6bit and 7bit, and they would use this cell
- *
- * Verilog wrapper for sky130_hilas_DAC5bit01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC5bit01 (
-    A0,
-    A1,
-    A2,
-    A3,
-    A4,
-    OUT,
-    VPWR,
-    VNB,
-    VPB
-);
-        inout A0;
-        inout A1;
-        inout A2;
-        inout A3;
-        inout A4;
-        inout OUT;
-        inout VPWR;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC5bit01 (
-    A0,
-    A1,
-    A2,
-    A3,
-    A4,
-    OUT
-);
-        inout A0;
-        inout A1;
-        inout A2;
-        inout A3;
-        inout A4;
-        inout OUT;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC5BIT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_HORIZTRANSCELL01A
-`define SKY130_HILAS_HORIZTRANSCELL01A
-
-/**
- * sky130_hilas_horizTransCell01a: 
- *
- * Verilog wrapper for sky130_hilas_horizTransCell01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_HORIZTRANSCELL01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_VINJINV2
-`define SKY130_HILAS_VINJINV2
-
-/**
- * sky130_hilas_VinjInv2: logical inverter for VINJ-level voltages
- *
- * Verilog wrapper for sky130_hilas_VinjInv2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjInv2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjInv2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_VINJINV2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DECOUP_CAP_00
-`define SKY130_HILAS_DECOUP_CAP_00
-
-/**
- * sky130_hilas_decoup_cap_00: decoupling cap (intended as fill)
- *
- * Verilog wrapper for sky130_hilas_decoup_cap_00.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_decoup_cap_00 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_decoup_cap_00 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DECOUP_CAP_00
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_OVERLAPCAP02
-`define SKY130_HILAS_OVERLAPCAP02
-
-/**
- * sky130_hilas_overlapCap02: overlap capacitor based capacitor)
- *
- * Verilog wrapper for sky130_hilas_overlapCap02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_OVERLAPCAP02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGVARACTORCAPACITOR
-`define SKY130_HILAS_FGVARACTORCAPACITOR
-
-/**
- * sky130_hilas_FGVaractorCapacitor: varactor cap for floating-gate charge storage
- *
- * Verilog wrapper for sky130_hilas_FGVaractorCapacitor.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorCapacitor (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGVARACTORCAPACITOR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01W1
-`define SKY130_HILAS_PFETDEVICE01W1
-
-/**
- * sky130_hilas_pFETdevice01w1: 
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01w1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01w1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01w1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01W1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_VINJDECODE2TO4
-`define SKY130_HILAS_VINJDECODE2TO4
-
-/**
- * sky130_hilas_VinjDecode2to4: a 2-to-4 decoder capable of handling VINJ voltage
- *
- * Verilog wrapper for sky130_hilas_VinjDecode2to4.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_VinjDecode2to4 (
-    OUTPUT00,
-    OUTPUT01,
-    OUTPUT10,
-    OUTPUT11,
+module sky130_hilas_drainSelect01 (
+    DRAIN3,
     VINJ,
-    IN2,
-    IN1,
-    ENABLE,
+    DRAIN_MUX,
+    SELECT2,
+    SELECT1,
+    SELECT3,
+    SELECT4,
     VGND,
     VNB,
     VPB
 );
-        inout OUTPUT00;
-        inout OUTPUT01;
-        inout OUTPUT10;
-        inout OUTPUT11;
+        inout DRAIN3;
         inout VINJ;
-        inout IN2;
-        inout IN1;
-        inout ENABLE;
+        inout DRAIN_MUX;
+        inout SELECT2;
+        inout SELECT1;
+        inout SELECT3;
+        inout SELECT4;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -7078,24 +5609,22 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjDecode2to4 (
-    OUTPUT00,
-    OUTPUT01,
-    OUTPUT10,
-    OUTPUT11,
+module sky130_hilas_drainSelect01 (
+    DRAIN3,
     VINJ,
-    IN2,
-    IN1,
-    ENABLE
+    DRAIN_MUX,
+    SELECT2,
+    SELECT1,
+    SELECT3,
+    SELECT4
 );
-        inout OUTPUT00;
-        inout OUTPUT01;
-        inout OUTPUT10;
-        inout OUTPUT11;
+        inout DRAIN3;
         inout VINJ;
-        inout IN2;
-        inout IN1;
-        inout ENABLE;
+        inout DRAIN_MUX;
+        inout SELECT2;
+        inout SELECT1;
+        inout SELECT3;
+        inout SELECT4;
 endmodule
 `endcelldefine
 
@@ -7103,18 +5632,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_VINJDECODE2TO4
+`endif  // SKY130_HILAS_DRAINSELECT01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETDEVICE01BA
-`define SKY130_HILAS_PFETDEVICE01BA
+`ifndef SKY130_HILAS_CAPMODULE01
+`define SKY130_HILAS_CAPMODULE01
 
 /**
- * sky130_hilas_pFETdevice01ba: pFET transistor used in DAC block
+ * sky130_hilas_CapModule01: None
  *
- * Verilog wrapper for sky130_hilas_pFETdevice01ba.
+ * Verilog wrapper for sky130_hilas_CapModule01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -7127,7 +5656,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETdevice01ba (
+module sky130_hilas_CapModule01 (
     VNB,
     VPB
 );
@@ -7141,7 +5670,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETdevice01ba (
+module sky130_hilas_CapModule01 (
     
 );
 endmodule
@@ -7151,7 +5680,250 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01BA
+`endif  // SKY130_HILAS_CAPMODULE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LEFTPROTECTION
+`define SKY130_HILAS_LEFTPROTECTION
+
+/**
+ * sky130_hilas_LeftProtection: 
+ *
+ * Verilog wrapper for sky130_hilas_LeftProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LeftProtection (
+    IO25,
+    IO26,
+    IO27,
+    IO28,
+    IO29,
+    IO30,
+    IO31,
+    IO32,
+    IO33,
+    IO34,
+    IO35,
+    IO36,
+    IO37,
+    PIN1,
+    PIN2,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    PIN11,
+    PIN12,
+    PIN13,
+    VNB,
+    VPB
+);
+        inout IO25;
+        inout IO26;
+        inout IO27;
+        inout IO28;
+        inout IO29;
+        inout IO30;
+        inout IO31;
+        inout IO32;
+        inout IO33;
+        inout IO34;
+        inout IO35;
+        inout IO36;
+        inout IO37;
+        inout PIN1;
+        inout PIN2;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout PIN11;
+        inout PIN12;
+        inout PIN13;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LeftProtection (
+    IO25,
+    IO26,
+    IO27,
+    IO28,
+    IO29,
+    IO30,
+    IO31,
+    IO32,
+    IO33,
+    IO34,
+    IO35,
+    IO36,
+    IO37,
+    PIN1,
+    PIN2,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    PIN11,
+    PIN12,
+    PIN13
+);
+        inout IO25;
+        inout IO26;
+        inout IO27;
+        inout IO28;
+        inout IO29;
+        inout IO30;
+        inout IO31;
+        inout IO32;
+        inout IO33;
+        inout IO34;
+        inout IO35;
+        inout IO36;
+        inout IO37;
+        inout PIN1;
+        inout PIN2;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout PIN11;
+        inout PIN12;
+        inout PIN13;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_LEFTPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORCAPACITOR02
+`define SKY130_HILAS_FGVARACTORCAPACITOR02
+
+/**
+ * sky130_hilas_FGVaractorCapacitor02: variant 2, varactor cap for floating-gate charge storage
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorCapacitor02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGVARACTORCAPACITOR02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01PART1
+`define SKY130_HILAS_TGATESINGLE01PART1
+
+/**
+ * sky130_hilas_TgateSingle01Part1: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01Part1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATESINGLE01PART1
 
 
 //--------EOF---------
@@ -7259,13 +6031,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETLARGE
-`define SKY130_HILAS_PFETLARGE
+`ifndef SKY130_HILAS_VINJINV2
+`define SKY130_HILAS_VINJINV2
 
 /**
- * sky130_hilas_pFETLarge: Single Large (W/L=100) pFET Transistor
+ * sky130_hilas_VinjInv2: logical inverter for VINJ-level voltages
  *
- * Verilog wrapper for sky130_hilas_pFETLarge.
+ * Verilog wrapper for sky130_hilas_VinjInv2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -7278,70 +6050,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN,
-    WELL,
-    VNB,
-    VPB
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-        inout WELL;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN,
-    WELL
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-        inout WELL;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETLARGE
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFET03A
-`define SKY130_HILAS_NFET03A
-
-/**
- * sky130_hilas_nFET03a: None
- *
- * Verilog wrapper for sky130_hilas_nFET03a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFET03a (
+module sky130_hilas_VinjInv2 (
     VNB,
     VPB
 );
@@ -7355,7 +6064,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFET03a (
+module sky130_hilas_VinjInv2 (
     
 );
 endmodule
@@ -7365,18 +6074,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NFET03A
+`endif  // SKY130_HILAS_VINJINV2
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
-`define SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+`ifndef SKY130_HILAS_CAPMODULE02
+`define SKY130_HILAS_CAPMODULE02
 
 /**
- * sky130_hilas_FGHugeVaractorCapacitor01: one large varactor cap
+ * sky130_hilas_CapModule02: None
  *
- * Verilog wrapper for sky130_hilas_FGHugeVaractorCapacitor01.
+ * Verilog wrapper for sky130_hilas_CapModule02.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -7389,7 +6098,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_FGHugeVaractorCapacitor01 (
+module sky130_hilas_CapModule02 (
     VNB,
     VPB
 );
@@ -7403,7 +6112,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_FGHugeVaractorCapacitor01 (
+module sky130_hilas_CapModule02 (
     
 );
 endmodule
@@ -7413,18 +6122,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+`endif  // SKY130_HILAS_CAPMODULE02
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_TGATEVINJ01
-`define SKY130_HILAS_TGATEVINJ01
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01C
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01C
 
 /**
- * sky130_hilas_TgateVinj01: None
+ * sky130_hilas_DAC6TransistorStack01c: None
  *
- * Verilog wrapper for sky130_hilas_TgateVinj01.
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01c.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -7437,7 +6146,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateVinj01 (
+module sky130_hilas_DAC6TransistorStack01c (
     VNB,
     VPB
 );
@@ -7451,7 +6160,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_TgateVinj01 (
+module sky130_hilas_DAC6TransistorStack01c (
     
 );
 endmodule
@@ -7461,7 +6170,839 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_TGATEVINJ01
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01C
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGCHARACTERIZATION01
+`define SKY130_HILAS_FGCHARACTERIZATION01
+
+/**
+ * sky130_hilas_FGcharacterization01: FG test strucure that uses a capacitor around a transconductance amplifier
+ *
+ * Verilog wrapper for sky130_hilas_FGcharacterization01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGcharacterization01 (
+    VTUN,
+    GATE1,
+    GATE3,
+    VTUNOVERLAP01,
+    GATE2,
+    GATE4,
+    LARGECAPACITOR,
+    VINJ,
+    OUTPUT,
+    VREF,
+    VBIAS,
+    DRAIN1,
+    SOURCE1,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VTUN;
+        inout GATE1;
+        inout GATE3;
+        inout VTUNOVERLAP01;
+        inout GATE2;
+        inout GATE4;
+        inout LARGECAPACITOR;
+        inout VINJ;
+        inout OUTPUT;
+        inout VREF;
+        inout VBIAS;
+        inout DRAIN1;
+        inout SOURCE1;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGcharacterization01 (
+    VTUN,
+    GATE1,
+    GATE3,
+    VTUNOVERLAP01,
+    GATE2,
+    GATE4,
+    LARGECAPACITOR,
+    VINJ,
+    OUTPUT,
+    VREF,
+    VBIAS,
+    DRAIN1,
+    SOURCE1
+);
+        inout VTUN;
+        inout GATE1;
+        inout GATE3;
+        inout VTUNOVERLAP01;
+        inout GATE2;
+        inout GATE4;
+        inout LARGECAPACITOR;
+        inout VINJ;
+        inout OUTPUT;
+        inout VREF;
+        inout VBIAS;
+        inout DRAIN1;
+        inout SOURCE1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGCHARACTERIZATION01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP01
+`define SKY130_HILAS_OVERLAPCAP01
+
+/**
+ * sky130_hilas_overlapCap01: overlap capacitor based capacitor
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_OVERLAPCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PTRANSISTORPAIR
+`define SKY130_HILAS_PTRANSISTORPAIR
+
+/**
+ * sky130_hilas_pTransistorPair: None
+ *
+ * Verilog wrapper for sky130_hilas_pTransistorPair.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorPair (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorPair (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PTRANSISTORPAIR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CELLATTEMPT01
+`define SKY130_HILAS_CELLATTEMPT01
+
+/**
+ * sky130_hilas_cellAttempt01: 4x1 array of FG switch cell, Varactor capacitor cell
+ *
+ * Verilog wrapper for sky130_hilas_cellAttempt01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_cellAttempt01 (
+    VTUN,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    ROW4,
+    DRAIN4,
+    DRAIN1,
+    ROW1,
+    ROW3,
+    DRAIN3,
+    DRAIN2,
+    ROW2,
+    VGND,
+    VNB,
+    VPB
+);
+        inout VTUN;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout ROW4;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout ROW1;
+        inout ROW3;
+        inout DRAIN3;
+        inout DRAIN2;
+        inout ROW2;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_cellAttempt01 (
+    VTUN,
+    VINJ,
+    COLSEL1,
+    GATE1,
+    ROW4,
+    DRAIN4,
+    DRAIN1,
+    ROW1,
+    ROW3,
+    DRAIN3,
+    DRAIN2,
+    ROW2
+);
+        inout VTUN;
+        inout VINJ;
+        inout COLSEL1;
+        inout GATE1;
+        inout ROW4;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout ROW1;
+        inout ROW3;
+        inout DRAIN3;
+        inout DRAIN2;
+        inout ROW2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CELLATTEMPT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLY2M1
+`define SKY130_HILAS_POLY2M1
+
+/**
+ * sky130_hilas_poly2m1: polysilicon layer to m1 contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2m1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_POLY2M1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01W1
+`define SKY130_HILAS_PFETDEVICE01W1
+
+/**
+ * sky130_hilas_pFETdevice01w1: 
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01w1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01w1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01w1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01W1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC5BIT01
+`define SKY130_HILAS_DAC5BIT01
+
+/**
+ * sky130_hilas_DAC5bit01: 5-bit digital-to-analog converter (under 6.05um at the moment; thinking through expansion to 6bit and 7bit, and they would use this cell
+ *
+ * Verilog wrapper for sky130_hilas_DAC5bit01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC5bit01 (
+    A0,
+    A1,
+    A2,
+    A3,
+    A4,
+    OUT,
+    VPWR,
+    VNB,
+    VPB
+);
+        inout A0;
+        inout A1;
+        inout A2;
+        inout A3;
+        inout A4;
+        inout OUT;
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC5bit01 (
+    A0,
+    A1,
+    A2,
+    A3,
+    A4,
+    OUT
+);
+        inout A0;
+        inout A1;
+        inout A2;
+        inout A3;
+        inout A4;
+        inout OUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC5BIT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJNOR3
+`define SKY130_HILAS_VINJNOR3
+
+/**
+ * sky130_hilas_VinjNOR3: 3-input NOR gate capable of VING voltage
+ *
+ * Verilog wrapper for sky130_hilas_VinjNOR3.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjNOR3 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjNOR3 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_VINJNOR3
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJDECODE2TO4
+`define SKY130_HILAS_VINJDECODE2TO4
+
+/**
+ * sky130_hilas_VinjDecode2to4: a 2-to-4 decoder capable of handling VINJ voltage
+ *
+ * Verilog wrapper for sky130_hilas_VinjDecode2to4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDecode2to4 (
+    OUTPUT00,
+    OUTPUT01,
+    OUTPUT10,
+    OUTPUT11,
+    VINJ,
+    IN2,
+    IN1,
+    ENABLE,
+    VGND,
+    VNB,
+    VPB
+);
+        inout OUTPUT00;
+        inout OUTPUT01;
+        inout OUTPUT10;
+        inout OUTPUT11;
+        inout VINJ;
+        inout IN2;
+        inout IN1;
+        inout ENABLE;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDecode2to4 (
+    OUTPUT00,
+    OUTPUT01,
+    OUTPUT10,
+    OUTPUT11,
+    VINJ,
+    IN2,
+    IN1,
+    ENABLE
+);
+        inout OUTPUT00;
+        inout OUTPUT01;
+        inout OUTPUT10;
+        inout OUTPUT11;
+        inout VINJ;
+        inout IN2;
+        inout IN1;
+        inout ENABLE;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_VINJDECODE2TO4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01AA
+`define SKY130_HILAS_PFETDEVICE01AA
+
+/**
+ * sky130_hilas_pFETdevice01aa: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01aa.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01aa (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01aa (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01AA
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NDIFFTHOXCONTACT
+`define SKY130_HILAS_NDIFFTHOXCONTACT
+
+/**
+ * sky130_hilas_nDiffThOxContact: None
+ *
+ * Verilog wrapper for sky130_hilas_nDiffThOxContact.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nDiffThOxContact (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nDiffThOxContact (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NDIFFTHOXCONTACT
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WELLCONTACT
+`define SKY130_HILAS_WELLCONTACT
+
+/**
+ * sky130_hilas_wellContact: contact to a well block, typically used for contacting tunneling junctions in a well.
+ *
+ * Verilog wrapper for sky130_hilas_wellContact.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_wellContact (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_wellContact (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_WELLCONTACT
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP02
+`define SKY130_HILAS_OVERLAPCAP02
+
+/**
+ * sky130_hilas_overlapCap02: overlap capacitor based capacitor)
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_OVERLAPCAP02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01C
+`define SKY130_HILAS_PFETDEVICE01C
+
+/**
+ * sky130_hilas_pFETdevice01c: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01c.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01c (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01c (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01C
 
 
 //--------EOF---------
@@ -7529,6 +7070,1268 @@
 
 //--------EOF---------
 
+`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP2
+`define SKY130_HILAS_SWC4X1CELLOVERLAP2
+
+/**
+ * sky130_hilas_swc4x1cellOverlap2: 4x1 analog mux with overlap
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1cellOverlap2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZTRANSCELL01A
+`define SKY130_HILAS_HORIZTRANSCELL01A
+
+/**
+ * sky130_hilas_horizTransCell01a: 
+ *
+ * Verilog wrapper for sky130_hilas_horizTransCell01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_HORIZTRANSCELL01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2CELL_NOFG
+`define SKY130_HILAS_TA2CELL_NOFG
+
+/**
+ * sky130_hilas_TA2Cell_NoFG: Two transimpedane amplifiers with no floating-gate inputs.
+ *
+ * Verilog wrapper for sky130_hilas_TA2Cell_NoFG.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_NoFG (
+    COLSEL1,
+    VIN12,
+    VIN21,
+    VIN22,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    VTUN,
+    GATE1,
+    VINJ,
+    VIN11,
+    VGND,
+    VPWR,
+    VNB,
+    VPB
+);
+        inout COLSEL1;
+        inout VIN12;
+        inout VIN21;
+        inout VIN22;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout VIN11;
+        inout VGND;
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_NoFG (
+    COLSEL1,
+    VIN12,
+    VIN21,
+    VIN22,
+    OUTPUT1,
+    OUTPUT2,
+    DRAIN1,
+    DRAIN2,
+    VTUN,
+    GATE1,
+    VINJ,
+    VIN11
+);
+        inout COLSEL1;
+        inout VIN12;
+        inout VIN21;
+        inout VIN22;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout VIN11;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TA2CELL_NOFG
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGBIAS2X1CELL
+`define SKY130_HILAS_FGBIAS2X1CELL
+
+/**
+ * sky130_hilas_FGBias2x1cell: None
+ *
+ * Verilog wrapper for sky130_hilas_FGBias2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBias2x1cell (
+    DRAIN1,
+    DRAIN4,
+    GATECOL,
+    GATE_CONTROL,
+    OUTPUT1,
+    OUTPUT2,
+    VINJ,
+    VTUN,
+    VGND,
+    VNB,
+    VPB
+);
+        inout DRAIN1;
+        inout DRAIN4;
+        inout GATECOL;
+        inout GATE_CONTROL;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout VINJ;
+        inout VTUN;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBias2x1cell (
+    DRAIN1,
+    DRAIN4,
+    GATECOL,
+    GATE_CONTROL,
+    OUTPUT1,
+    OUTPUT2,
+    VINJ,
+    VTUN
+);
+        inout DRAIN1;
+        inout DRAIN4;
+        inout GATECOL;
+        inout GATE_CONTROL;
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout VINJ;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGBIAS2X1CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE03
+`define SKY130_HILAS_CAPMODULE03
+
+/**
+ * sky130_hilas_CapModule03: None
+ *
+ * Verilog wrapper for sky130_hilas_CapModule03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule03 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule03 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPMODULE03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMIRROR02
+`define SKY130_HILAS_PFETMIRROR02
+
+/**
+ * sky130_hilas_pFETmirror02: second pFET current mirror
+ *
+ * Verilog wrapper for sky130_hilas_pFETmirror02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror02 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror02 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETMIRROR02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMIRRORPAIRS2
+`define SKY130_HILAS_NFETMIRRORPAIRS2
+
+/**
+ * sky130_hilas_nFETmirrorPairs2: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETmirrorPairs2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETMIRRORPAIRS2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TOPPROTECTION
+`define SKY130_HILAS_TOPPROTECTION
+
+/**
+ * sky130_hilas_TopProtection: 
+ *
+ * Verilog wrapper for sky130_hilas_TopProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopProtection (
+    ANALOG00,
+    ANALOG01,
+    ANALOG02,
+    ANALOG03,
+    ANALOG04,
+    ANALOG05,
+    ANALOG06,
+    ANALOG07,
+    ANALOG08,
+    ANALOG09,
+    ANALOG10,
+    PIN1,
+    PIN2,
+    PIN3,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    VTUN,
+    VNB,
+    VPB
+);
+        inout ANALOG00;
+        inout ANALOG01;
+        inout ANALOG02;
+        inout ANALOG03;
+        inout ANALOG04;
+        inout ANALOG05;
+        inout ANALOG06;
+        inout ANALOG07;
+        inout ANALOG08;
+        inout ANALOG09;
+        inout ANALOG10;
+        inout PIN1;
+        inout PIN2;
+        inout PIN3;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout VTUN;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopProtection (
+    ANALOG00,
+    ANALOG01,
+    ANALOG02,
+    ANALOG03,
+    ANALOG04,
+    ANALOG05,
+    ANALOG06,
+    ANALOG07,
+    ANALOG08,
+    ANALOG09,
+    ANALOG10,
+    PIN1,
+    PIN2,
+    PIN3,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    VTUN
+);
+        inout ANALOG00;
+        inout ANALOG01;
+        inout ANALOG02;
+        inout ANALOG03;
+        inout ANALOG04;
+        inout ANALOG05;
+        inout ANALOG06;
+        inout ANALOG07;
+        inout ANALOG08;
+        inout ANALOG09;
+        inout ANALOG10;
+        inout PIN1;
+        inout PIN2;
+        inout PIN3;
+        inout PIN4;
+        inout PIN5;
+        inout PIN6;
+        inout PIN7;
+        inout PIN8;
+        inout PIN9;
+        inout PIN10;
+        inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TOPPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATE4SINGLE01
+`define SKY130_HILAS_TGATE4SINGLE01
+
+/**
+ * sky130_hilas_Tgate4Single01: 4 single-throw transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_Tgate4Single01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Single01 (
+    INPUT1_2,
+    SELECT2,
+    OUTPUT2,
+    OUTPUT4,
+    OUTPUT3,
+    OUTPUT1,
+    INPUT1_4,
+    SELECT4,
+    SELECT3,
+    INPUT1_3,
+    SELECT1,
+    INPUT1_1,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout INPUT1_2;
+        inout SELECT2;
+        inout OUTPUT2;
+        inout OUTPUT4;
+        inout OUTPUT3;
+        inout OUTPUT1;
+        inout INPUT1_4;
+        inout SELECT4;
+        inout SELECT3;
+        inout INPUT1_3;
+        inout SELECT1;
+        inout INPUT1_1;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Single01 (
+    INPUT1_2,
+    SELECT2,
+    OUTPUT2,
+    OUTPUT4,
+    OUTPUT3,
+    OUTPUT1,
+    INPUT1_4,
+    SELECT4,
+    SELECT3,
+    INPUT1_3,
+    SELECT1,
+    INPUT1_1
+);
+        inout INPUT1_2;
+        inout SELECT2;
+        inout OUTPUT2;
+        inout OUTPUT4;
+        inout OUTPUT3;
+        inout OUTPUT1;
+        inout INPUT1_4;
+        inout SELECT4;
+        inout SELECT3;
+        inout INPUT1_3;
+        inout SELECT1;
+        inout INPUT1_1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATE4SINGLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP02A
+`define SKY130_HILAS_OVERLAPCAP02A
+
+/**
+ * sky130_hilas_overlapCap02a: overlap capacitor based capacitor
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap02a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_OVERLAPCAP02A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1BIASCELL
+`define SKY130_HILAS_SWC4X1BIASCELL
+
+/**
+ * sky130_hilas_swc4x1BiasCell: 4x1 array of FG switch cell configured pFET as current sources
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1BiasCell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1BiasCell (
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
+    VTUN,
+    GATE1,
+    VINJ,
+    DRAIN3,
+    DRAIN4,
+    DRAIN1,
+    DRAIN2,
+    VPWR,
+    VGND,
+    VNB,
+    VPB
+);
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout VPWR;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1BiasCell (
+    ROW1,
+    ROW2,
+    ROW3,
+    ROW4,
+    VTUN,
+    GATE1,
+    VINJ,
+    DRAIN3,
+    DRAIN4,
+    DRAIN1,
+    DRAIN2
+);
+        inout ROW1;
+        inout ROW2;
+        inout ROW3;
+        inout ROW4;
+        inout VTUN;
+        inout GATE1;
+        inout VINJ;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout DRAIN1;
+        inout DRAIN2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_SWC4X1BIASCELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE03
+`define SKY130_HILAS_CAPACITORSIZE03
+
+/**
+ * sky130_hilas_capacitorSize03: mid-large cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize03 (
+    CAPTERM02,
+    CAPTERM01,
+    VNB,
+    VPB
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize03 (
+    CAPTERM02,
+    CAPTERM01
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPACITORSIZE03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGTRANS2X1CELL
+`define SKY130_HILAS_FGTRANS2X1CELL
+
+/**
+ * sky130_hilas_FGtrans2x1cell: None
+ *
+ * Verilog wrapper for sky130_hilas_FGtrans2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGtrans2x1cell (
+    COLSEL1,
+    VINJ,
+    DRAIN1,
+    DRAIN2,
+    PROG,
+    RUN,
+    VIN2,
+    VIN1,
+    GATE1,
+    VTUN,
+    COL1,
+    ROW1,
+    ROW2,
+    VGND,
+    VNB,
+    VPB
+);
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout PROG;
+        inout RUN;
+        inout VIN2;
+        inout VIN1;
+        inout GATE1;
+        inout VTUN;
+        inout COL1;
+        inout ROW1;
+        inout ROW2;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGtrans2x1cell (
+    COLSEL1,
+    VINJ,
+    DRAIN1,
+    DRAIN2,
+    PROG,
+    RUN,
+    VIN2,
+    VIN1,
+    GATE1,
+    VTUN,
+    COL1,
+    ROW1,
+    ROW2
+);
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN1;
+        inout DRAIN2;
+        inout PROG;
+        inout RUN;
+        inout VIN2;
+        inout VIN1;
+        inout GATE1;
+        inout VTUN;
+        inout COL1;
+        inout ROW1;
+        inout ROW2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_FGTRANS2X1CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLY2M2
+`define SKY130_HILAS_POLY2M2
+
+/**
+ * sky130_hilas_poly2m2: polysilicon layer to m2 contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2m2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m2 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m2 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_POLY2M2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE01A
+`define SKY130_HILAS_CAPMODULE01A
+
+/**
+ * sky130_hilas_CapModule01a: primitive cap, variant 01a
+ *
+ * Verilog wrapper for sky130_hilas_CapModule01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01a (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01a (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPMODULE01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01D
+`define SKY130_HILAS_PFETDEVICE01D
+
+/**
+ * sky130_hilas_pFETdevice01d: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01d.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01d (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01d (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01D
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTA4STAGE01
+`define SKY130_HILAS_WTA4STAGE01
+
+/**
+ * sky130_hilas_WTA4Stage01: 4-input winner-take-all circuit. Connects directly to array of swc4x2cell. Can array vertically. Needs one nFET transistor current source.
+ *
+ * Verilog wrapper for sky130_hilas_WTA4Stage01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTA4Stage01 (
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4,
+    DRAIN1,
+    GATE1,
+    VTUN,
+    WTAMIDDLENODE,
+    COLSEL1,
+    VINJ,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4,
+    VGND,
+    VNB,
+    VPB
+);
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+        inout DRAIN1;
+        inout GATE1;
+        inout VTUN;
+        inout WTAMIDDLENODE;
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout DRAIN4;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTA4Stage01 (
+    OUTPUT1,
+    OUTPUT2,
+    OUTPUT3,
+    OUTPUT4,
+    INPUT1,
+    INPUT2,
+    INPUT3,
+    INPUT4,
+    DRAIN1,
+    GATE1,
+    VTUN,
+    WTAMIDDLENODE,
+    COLSEL1,
+    VINJ,
+    DRAIN2,
+    DRAIN3,
+    DRAIN4
+);
+        inout OUTPUT1;
+        inout OUTPUT2;
+        inout OUTPUT3;
+        inout OUTPUT4;
+        inout INPUT1;
+        inout INPUT2;
+        inout INPUT3;
+        inout INPUT4;
+        inout DRAIN1;
+        inout GATE1;
+        inout VTUN;
+        inout WTAMIDDLENODE;
+        inout COLSEL1;
+        inout VINJ;
+        inout DRAIN2;
+        inout DRAIN3;
+        inout DRAIN4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_WTA4STAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTABLOCKSAMPLE01
+`define SKY130_HILAS_WTABLOCKSAMPLE01
+
+/**
+ * sky130_hilas_WTAblockSample01: None
+ *
+ * Verilog wrapper for sky130_hilas_WTAblockSample01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAblockSample01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAblockSample01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_WTABLOCKSAMPLE01
+
+
+//--------EOF---------
+
 `ifndef SKY130_HILAS_TOPPROTECTSTRUCTURE
 `define SKY130_HILAS_TOPPROTECTSTRUCTURE
 
@@ -7828,1206 +8631,6 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_M12M2
-`define SKY130_HILAS_M12M2
-
-/**
- * sky130_hilas_m12m2: m1 to m2 contact
- *
- * Verilog wrapper for sky130_hilas_m12m2.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_m12m2 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_m12m2 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_M12M2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01AA
-`define SKY130_HILAS_PFETDEVICE01AA
-
-/**
- * sky130_hilas_pFETdevice01aa: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01aa.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01aa (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01aa (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01AA
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGVARACTORTUNNELCAP01
-`define SKY130_HILAS_FGVARACTORTUNNELCAP01
-
-/**
- * sky130_hilas_FGVaractorTunnelCap01: Tunneling cpacitor using a standard varactor capacitor
- *
- * Verilog wrapper for sky130_hilas_FGVaractorTunnelCap01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorTunnelCap01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGVaractorTunnelCap01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGVARACTORTUNNELCAP01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TUNCAP01
-`define SKY130_HILAS_TUNCAP01
-
-/**
- * sky130_hilas_TunCap01: None
- *
- * Verilog wrapper for sky130_hilas_TunCap01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunCap01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunCap01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TUNCAP01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETMED
-`define SKY130_HILAS_PFETMED
-
-/**
- * sky130_hilas_pFETmed: Medium-sized (W/L=10) pFET transistor
- *
- * Verilog wrapper for sky130_hilas_pFETmed.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmed (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETmed (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETMED
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPACITORSIZE03
-`define SKY130_HILAS_CAPACITORSIZE03
-
-/**
- * sky130_hilas_capacitorSize03: mid-large cap
- *
- * Verilog wrapper for sky130_hilas_capacitorSize03.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorSize03 (
-    CAPTERM02,
-    CAPTERM01,
-    VNB,
-    VPB
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorSize03 (
-    CAPTERM02,
-    CAPTERM01
-);
-        inout CAPTERM02;
-        inout CAPTERM01;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPACITORSIZE03
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPMODULE02
-`define SKY130_HILAS_CAPMODULE02
-
-/**
- * sky130_hilas_CapModule02: None
- *
- * Verilog wrapper for sky130_hilas_CapModule02.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule02 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule02 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE02
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATESINGLE01PART1
-`define SKY130_HILAS_TGATESINGLE01PART1
-
-/**
- * sky130_hilas_TgateSingle01Part1: None
- *
- * Verilog wrapper for sky130_hilas_TgateSingle01Part1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateSingle01Part1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateSingle01Part1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATESINGLE01PART1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TUNVARACTORCAPCITOR
-`define SKY130_HILAS_TUNVARACTORCAPCITOR
-
-/**
- * sky130_hilas_TunVaractorCapcitor: Tunneling capacitor using a standard varactor capacitor
- *
- * Verilog wrapper for sky130_hilas_TunVaractorCapcitor.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunVaractorCapcitor (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TunVaractorCapcitor (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TUNVARACTORCAPCITOR
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_FGBIASWEAKGATE2X1CELL
-`define SKY130_HILAS_FGBIASWEAKGATE2X1CELL
-
-/**
- * sky130_hilas_FGBiasWeakGate2x1cell: 2x1 array of FG switch cells configured as pFET current sources with weak capacitive gate inputs
- *
- * Verilog wrapper for sky130_hilas_FGBiasWeakGate2x1cell.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGBiasWeakGate2x1cell (
-    DRAIN1,
-    VIN11,
-    ROW1,
-    ROW2,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    VTUN,
-    DRAIN2,
-    VIN12,
-    COMMONSOURCE,
-    VGND,
-    VNB,
-    VPB
-);
-        inout DRAIN1;
-        inout VIN11;
-        inout ROW1;
-        inout ROW2;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout VTUN;
-        inout DRAIN2;
-        inout VIN12;
-        inout COMMONSOURCE;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_FGBiasWeakGate2x1cell (
-    DRAIN1,
-    VIN11,
-    ROW1,
-    ROW2,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    VTUN,
-    DRAIN2,
-    VIN12,
-    COMMONSOURCE
-);
-        inout DRAIN1;
-        inout VIN11;
-        inout ROW1;
-        inout ROW2;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout VTUN;
-        inout DRAIN2;
-        inout VIN12;
-        inout COMMONSOURCE;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_FGBIASWEAKGATE2X1CELL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_LI2M1
-`define SKY130_HILAS_LI2M1
-
-/**
- * sky130_hilas_li2m1: local interconnect to m1 contact
- *
- * Verilog wrapper for sky130_hilas_li2m1.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_li2m1 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_li2m1 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_LI2M1
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DUALTACORE01
-`define SKY130_HILAS_DUALTACORE01
-
-/**
- * sky130_hilas_DualTACore01: None
- *
- * Verilog wrapper for sky130_hilas_DualTACore01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DualTACore01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DualTACore01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DUALTACORE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_STEPUPDIGITAL
-`define SKY130_HILAS_STEPUPDIGITAL
-
-/**
- * sky130_hilas_StepUpDigital: a single level shifter
- *
- * Verilog wrapper for sky130_hilas_StepUpDigital.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigital (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_StepUpDigital (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_STEPUPDIGITAL
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PTRANSISTORVERT01
-`define SKY130_HILAS_PTRANSISTORVERT01
-
-/**
- * sky130_hilas_pTransistorVert01: None
- *
- * Verilog wrapper for sky130_hilas_pTransistorVert01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorVert01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pTransistorVert01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PTRANSISTORVERT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPMODULE01A
-`define SKY130_HILAS_CAPMODULE01A
-
-/**
- * sky130_hilas_CapModule01a: primitive cap, variant 01a
- *
- * Verilog wrapper for sky130_hilas_CapModule01a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule01a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule01a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE01A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01C
-`define SKY130_HILAS_PFETDEVICE01C
-
-/**
- * sky130_hilas_pFETdevice01c: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01c.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01c (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01c (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01C
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPACITORARRAY01
-`define SKY130_HILAS_CAPACITORARRAY01
-
-/**
- * sky130_hilas_capacitorArray01: selectable capacitor array
- *
- * Verilog wrapper for sky130_hilas_capacitorArray01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorArray01 (
-    CAPTERM2,
-    CAPTERM1,
-    VINJ,
-    GATESELECT,
-    VTUN,
-    GATE,
-    DRAIN2,
-    DRAIN1,
-    DRAIN4,
-    DRAIN3,
-    VGND,
-    VNB,
-    VPB
-);
-        inout CAPTERM2;
-        inout CAPTERM1;
-        inout VINJ;
-        inout GATESELECT;
-        inout VTUN;
-        inout GATE;
-        inout DRAIN2;
-        inout DRAIN1;
-        inout DRAIN4;
-        inout DRAIN3;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_capacitorArray01 (
-    CAPTERM2,
-    CAPTERM1,
-    VINJ,
-    GATESELECT,
-    VTUN,
-    GATE,
-    DRAIN2,
-    DRAIN1,
-    DRAIN4,
-    DRAIN3
-);
-        inout CAPTERM2;
-        inout CAPTERM1;
-        inout VINJ;
-        inout GATESELECT;
-        inout VTUN;
-        inout GATE;
-        inout DRAIN2;
-        inout DRAIN1;
-        inout DRAIN4;
-        inout DRAIN3;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPACITORARRAY01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01E
-`define SKY130_HILAS_PFETDEVICE01E
-
-/**
- * sky130_hilas_pFETdevice01e: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01e.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01e (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01e (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01E
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_HORIZTRANSCELL01
-`define SKY130_HILAS_HORIZTRANSCELL01
-
-/**
- * sky130_hilas_horizTransCell01: None
- *
- * Verilog wrapper for sky130_hilas_horizTransCell01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_horizTransCell01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_HORIZTRANSCELL01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_LEFTPROTECTION
-`define SKY130_HILAS_LEFTPROTECTION
-
-/**
- * sky130_hilas_LeftProtection: 
- *
- * Verilog wrapper for sky130_hilas_LeftProtection.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LeftProtection (
-    IO25,
-    IO26,
-    IO27,
-    IO28,
-    IO29,
-    IO30,
-    IO31,
-    IO32,
-    IO33,
-    IO34,
-    IO35,
-    IO36,
-    IO37,
-    PIN1,
-    PIN2,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    PIN11,
-    PIN12,
-    PIN13,
-    VNB,
-    VPB
-);
-        inout IO25;
-        inout IO26;
-        inout IO27;
-        inout IO28;
-        inout IO29;
-        inout IO30;
-        inout IO31;
-        inout IO32;
-        inout IO33;
-        inout IO34;
-        inout IO35;
-        inout IO36;
-        inout IO37;
-        inout PIN1;
-        inout PIN2;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout PIN11;
-        inout PIN12;
-        inout PIN13;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_LeftProtection (
-    IO25,
-    IO26,
-    IO27,
-    IO28,
-    IO29,
-    IO30,
-    IO31,
-    IO32,
-    IO33,
-    IO34,
-    IO35,
-    IO36,
-    IO37,
-    PIN1,
-    PIN2,
-    PIN4,
-    PIN5,
-    PIN6,
-    PIN7,
-    PIN8,
-    PIN9,
-    PIN10,
-    PIN11,
-    PIN12,
-    PIN13
-);
-        inout IO25;
-        inout IO26;
-        inout IO27;
-        inout IO28;
-        inout IO29;
-        inout IO30;
-        inout IO31;
-        inout IO32;
-        inout IO33;
-        inout IO34;
-        inout IO35;
-        inout IO36;
-        inout IO37;
-        inout PIN1;
-        inout PIN2;
-        inout PIN4;
-        inout PIN5;
-        inout PIN6;
-        inout PIN7;
-        inout PIN8;
-        inout PIN9;
-        inout PIN10;
-        inout PIN11;
-        inout PIN12;
-        inout PIN13;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_LEFTPROTECTION
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01B
-`define SKY130_HILAS_DAC6TRANSISTORSTACK01B
-
-/**
- * sky130_hilas_DAC6TransistorStack01b: None
- *
- * Verilog wrapper for sky130_hilas_DAC6TransistorStack01b.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01b (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_DAC6TransistorStack01b (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01B
-
-
-//--------EOF---------
-
 `ifndef SKY130_HILAS_TRANS2MED
 `define SKY130_HILAS_TRANS2MED
 
@@ -9129,13 +8732,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_LI2M2
-`define SKY130_HILAS_LI2M2
+`ifndef SKY130_HILAS_PFETDEVICE01
+`define SKY130_HILAS_PFETDEVICE01
 
 /**
- * sky130_hilas_li2m2: local interconnect to m2 contact
+ * sky130_hilas_pFETdevice01: pFET transistor used in DAC block
  *
- * Verilog wrapper for sky130_hilas_li2m2.
+ * Verilog wrapper for sky130_hilas_pFETdevice01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9148,7 +8751,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_li2m2 (
+module sky130_hilas_pFETdevice01 (
     VNB,
     VPB
 );
@@ -9162,7 +8765,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_li2m2 (
+module sky130_hilas_pFETdevice01 (
     
 );
 endmodule
@@ -9172,405 +8775,7 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_LI2M2
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CELLATTEMPT01
-`define SKY130_HILAS_CELLATTEMPT01
-
-/**
- * sky130_hilas_cellAttempt01: 4x1 array of FG switch cell, Varactor capacitor cell
- *
- * Verilog wrapper for sky130_hilas_cellAttempt01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_cellAttempt01 (
-    VTUN,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    ROW4,
-    DRAIN4,
-    DRAIN1,
-    ROW1,
-    ROW3,
-    DRAIN3,
-    DRAIN2,
-    ROW2,
-    VGND,
-    VNB,
-    VPB
-);
-        inout VTUN;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout ROW4;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout ROW1;
-        inout ROW3;
-        inout DRAIN3;
-        inout DRAIN2;
-        inout ROW2;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_cellAttempt01 (
-    VTUN,
-    VINJ,
-    COLSEL1,
-    GATE1,
-    ROW4,
-    DRAIN4,
-    DRAIN1,
-    ROW1,
-    ROW3,
-    DRAIN3,
-    DRAIN2,
-    ROW2
-);
-        inout VTUN;
-        inout VINJ;
-        inout COLSEL1;
-        inout GATE1;
-        inout ROW4;
-        inout DRAIN4;
-        inout DRAIN1;
-        inout ROW1;
-        inout ROW3;
-        inout DRAIN3;
-        inout DRAIN2;
-        inout ROW2;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CELLATTEMPT01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_OVERLAPCAP02A
-`define SKY130_HILAS_OVERLAPCAP02A
-
-/**
- * sky130_hilas_overlapCap02a: overlap capacitor based capacitor
- *
- * Verilog wrapper for sky130_hilas_overlapCap02a.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02a (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_overlapCap02a (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_OVERLAPCAP02A
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_WTABLOCKSAMPLE01
-`define SKY130_HILAS_WTABLOCKSAMPLE01
-
-/**
- * sky130_hilas_WTAblockSample01: None
- *
- * Verilog wrapper for sky130_hilas_WTAblockSample01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAblockSample01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_WTAblockSample01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_WTABLOCKSAMPLE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_PFETDEVICE01D
-`define SKY130_HILAS_PFETDEVICE01D
-
-/**
- * sky130_hilas_pFETdevice01d: pFET transistor used in DAC block
- *
- * Verilog wrapper for sky130_hilas_pFETdevice01d.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01d (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_pFETdevice01d (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_PFETDEVICE01D
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_CAPMODULE01
-`define SKY130_HILAS_CAPMODULE01
-
-/**
- * sky130_hilas_CapModule01: None
- *
- * Verilog wrapper for sky130_hilas_CapModule01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_CapModule01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE01
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_NFETLARGE
-`define SKY130_HILAS_NFETLARGE
-
-/**
- * sky130_hilas_nFETLarge: Single Large (W//L=100) nFET Transistor
- *
- * Verilog wrapper for sky130_hilas_nFETLarge.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN,
-    VGND,
-    VNB,
-    VPB
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-        inout VGND;
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_nFETLarge (
-    GATE,
-    SOURCE,
-    DRAIN
-);
-        inout GATE;
-        inout SOURCE;
-        inout DRAIN;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_NFETLARGE
-
-
-//--------EOF---------
-
-`ifndef SKY130_HILAS_TGATEDOUBLE01
-`define SKY130_HILAS_TGATEDOUBLE01
-
-/**
- * sky130_hilas_TgateDouble01: None
- *
- * Verilog wrapper for sky130_hilas_TgateDouble01.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateDouble01 (
-    VNB,
-    VPB
-);
-        inout VNB;
-        inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TgateDouble01 (
-    
-);
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif  // SKY130_HILAS_TGATEDOUBLE01
+`endif  // SKY130_HILAS_PFETDEVICE01
 
 
 //--------EOF---------
@@ -9623,13 +8828,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_CAPMODULE03
-`define SKY130_HILAS_CAPMODULE03
+`ifndef SKY130_HILAS_PFETMIRROR
+`define SKY130_HILAS_PFETMIRROR
 
 /**
- * sky130_hilas_CapModule03: None
+ * sky130_hilas_pFETmirror: pFET current mirror
  *
- * Verilog wrapper for sky130_hilas_CapModule03.
+ * Verilog wrapper for sky130_hilas_pFETmirror.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9642,7 +8847,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_CapModule03 (
+module sky130_hilas_pFETmirror (
     VNB,
     VPB
 );
@@ -9656,7 +8861,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_CapModule03 (
+module sky130_hilas_pFETmirror (
     
 );
 endmodule
@@ -9666,18 +8871,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_CAPMODULE03
+`endif  // SKY130_HILAS_PFETMIRROR
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_PFETLARGEPART1
-`define SKY130_HILAS_PFETLARGEPART1
+`ifndef M12M3
+`define M12M3
 
 /**
- * sky130_hilas_pFETLargePart1: Part of the W/L=100 pFET transistor
+ * m12m3: 
  *
- * Verilog wrapper for sky130_hilas_pFETLargePart1.
+ * Verilog wrapper for m12m3.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9690,7 +8895,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETLargePart1 (
+module m12m3 (
     VNB,
     VPB
 );
@@ -9704,7 +8909,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_pFETLargePart1 (
+module m12m3 (
     
 );
 endmodule
@@ -9714,18 +8919,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_PFETLARGEPART1
+`endif  // M12M3
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_VINJNOR3
-`define SKY130_HILAS_VINJNOR3
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01A
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01A
 
 /**
- * sky130_hilas_VinjNOR3: 3-input NOR gate capable of VING voltage
+ * sky130_hilas_DAC6TransistorStack01a: None
  *
- * Verilog wrapper for sky130_hilas_VinjNOR3.
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01a.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9738,7 +8943,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjNOR3 (
+module sky130_hilas_DAC6TransistorStack01a (
     VNB,
     VPB
 );
@@ -9752,7 +8957,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjNOR3 (
+module sky130_hilas_DAC6TransistorStack01a (
     
 );
 endmodule
@@ -9762,18 +8967,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_VINJNOR3
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01A
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_NFETLARGEPART1
-`define SKY130_HILAS_NFETLARGEPART1
+`ifndef SKY130_HILAS_DECOUP_CAP_00
+`define SKY130_HILAS_DECOUP_CAP_00
 
 /**
- * sky130_hilas_nFETLargePart1: None
+ * sky130_hilas_decoup_cap_00: decoupling cap (intended as fill)
  *
- * Verilog wrapper for sky130_hilas_nFETLargePart1.
+ * Verilog wrapper for sky130_hilas_decoup_cap_00.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9786,7 +8991,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFETLargePart1 (
+module sky130_hilas_decoup_cap_00 (
     VNB,
     VPB
 );
@@ -9800,7 +9005,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_nFETLargePart1 (
+module sky130_hilas_decoup_cap_00 (
     
 );
 endmodule
@@ -9810,18 +9015,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_NFETLARGEPART1
+`endif  // SKY130_HILAS_DECOUP_CAP_00
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_DAC6BIT01
-`define SKY130_HILAS_DAC6BIT01
+`ifndef SKY130_HILAS_M12M2
+`define SKY130_HILAS_M12M2
 
 /**
- * sky130_hilas_DAC6bit01: None
+ * sky130_hilas_m12m2: m1 to m2 contact
  *
- * Verilog wrapper for sky130_hilas_DAC6bit01.
+ * Verilog wrapper for sky130_hilas_m12m2.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9834,7 +9039,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6bit01 (
+module sky130_hilas_m12m2 (
     VNB,
     VPB
 );
@@ -9848,7 +9053,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_DAC6bit01 (
+module sky130_hilas_m12m2 (
     
 );
 endmodule
@@ -9858,7 +9063,103 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_DAC6BIT01
+`endif  // SKY130_HILAS_M12M2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01E
+`define SKY130_HILAS_PFETDEVICE01E
+
+/**
+ * sky130_hilas_pFETdevice01e: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01e.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01e (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01e (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01E
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATEDOUBLE01
+`define SKY130_HILAS_TGATEDOUBLE01
+
+/**
+ * sky130_hilas_TgateDouble01: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateDouble01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateDouble01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateDouble01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATEDOUBLE01
 
 
 //--------EOF---------
@@ -9911,13 +9212,13 @@
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_VINJDIODEPROTECT01
-`define SKY130_HILAS_VINJDIODEPROTECT01
+`ifndef SKY130_HILAS_DECOUP_CAP_01
+`define SKY130_HILAS_DECOUP_CAP_01
 
 /**
- * sky130_hilas_VinjDiodeProtect01: protective ESD diode for VINJ line
+ * sky130_hilas_decoup_cap_01: decoupling cap (intended as fill), variant
  *
- * Verilog wrapper for sky130_hilas_VinjDiodeProtect01.
+ * Verilog wrapper for sky130_hilas_decoup_cap_01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9930,15 +9231,452 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjDiodeProtect01 (
-    VINJ,
-    INPUT,
+module sky130_hilas_decoup_cap_01 (
+    VPWR,
+    VNB,
+    VPB
+);
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DECOUP_CAP_01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_MCAP2M4
+`define SKY130_HILAS_MCAP2M4
+
+/**
+ * sky130_hilas_mcap2m4: metal capacitor layer contact to m4
+ *
+ * Verilog wrapper for sky130_hilas_mcap2m4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_mcap2m4 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_mcap2m4 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_MCAP2M4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NMIRROR03
+`define SKY130_HILAS_NMIRROR03
+
+/**
+ * sky130_hilas_nMirror03: None
+ *
+ * Verilog wrapper for sky130_hilas_nMirror03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nMirror03 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nMirror03 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NMIRROR03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TUNCAP01
+`define SKY130_HILAS_TUNCAP01
+
+/**
+ * sky130_hilas_TunCap01: None
+ *
+ * Verilog wrapper for sky130_hilas_TunCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunCap01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunCap01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TUNCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETLARGEPART1
+`define SKY130_HILAS_NFETLARGEPART1
+
+/**
+ * sky130_hilas_nFETLargePart1: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETLargePart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLargePart1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLargePart1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFETLARGEPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01
+`define SKY130_HILAS_TGATESINGLE01
+
+/**
+ * sky130_hilas_TgateSingle01: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TGATESINGLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFET03
+`define SKY130_HILAS_NFET03
+
+/**
+ * sky130_hilas_nFET03: None
+ *
+ * Verilog wrapper for sky130_hilas_nFET03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_NFET03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE01
+`define SKY130_HILAS_CAPACITORSIZE01
+
+/**
+ * sky130_hilas_capacitorSize01: smallest cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize01 (
+    CAPTERM02,
+    CAPTERM01,
+    VNB,
+    VPB
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize01 (
+    CAPTERM02,
+    CAPTERM01
+);
+        inout CAPTERM02;
+        inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_CAPACITORSIZE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01B
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01B
+
+/**
+ * sky130_hilas_DAC6TransistorStack01b: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01b.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01b (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01b (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01B
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUPVINJ01
+`define SKY130_HILAS_DECOUPVINJ01
+
+/**
+ * sky130_hilas_DecoupVinj01: 
+ *
+ * Verilog wrapper for sky130_hilas_DecoupVinj01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DecoupVinj01 (
     VGND,
     VNB,
     VPB
 );
-        inout VINJ;
-        inout INPUT;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -9950,12 +9688,9 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_VinjDiodeProtect01 (
-    VINJ,
-    INPUT
+module sky130_hilas_DecoupVinj01 (
+    
 );
-        inout VINJ;
-        inout INPUT;
 endmodule
 `endcelldefine
 
@@ -9963,18 +9698,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_VINJDIODEPROTECT01
+`endif  // SKY130_HILAS_DECOUPVINJ01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_WTA4STAGE01
-`define SKY130_HILAS_WTA4STAGE01
+`ifndef SKY130_HILAS_PFETDEVICE01B
+`define SKY130_HILAS_PFETDEVICE01B
 
 /**
- * sky130_hilas_WTA4Stage01: 4-input winner-take-all circuit. Connects directly to array of swc4x2cell. Can array vertically. Needs one nFET transistor current source.
+ * sky130_hilas_pFETdevice01b: pFET transistor used in DAC block
  *
- * Verilog wrapper for sky130_hilas_WTA4Stage01.
+ * Verilog wrapper for sky130_hilas_pFETdevice01b.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -9987,45 +9722,318 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_WTA4Stage01 (
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
+module sky130_hilas_pFETdevice01b (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01b (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PFETDEVICE01B
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PTRANSISTORVERT01
+`define SKY130_HILAS_PTRANSISTORVERT01
+
+/**
+ * sky130_hilas_pTransistorVert01: None
+ *
+ * Verilog wrapper for sky130_hilas_pTransistorVert01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorVert01 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorVert01 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_PTRANSISTORVERT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2SIGNALBIASCELL
+`define SKY130_HILAS_TA2SIGNALBIASCELL
+
+/**
+ * sky130_hilas_TA2SignalBiasCell: None
+ *
+ * Verilog wrapper for sky130_hilas_TA2SignalBiasCell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2SignalBiasCell (
+    VOUT_AMP2,
+    VOUT_AMP1,
+    VIN22,
+    VIN21,
+    VIN11,
+    VIN12,
+    VBIAS2,
+    VBIAS1,
+    VGND,
+    VPWR,
+    VNB,
+    VPB
+);
+        inout VOUT_AMP2;
+        inout VOUT_AMP1;
+        inout VIN22;
+        inout VIN21;
+        inout VIN11;
+        inout VIN12;
+        inout VBIAS2;
+        inout VBIAS1;
+        inout VGND;
+        inout VPWR;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2SignalBiasCell (
+    VOUT_AMP2,
+    VOUT_AMP1,
+    VIN22,
+    VIN21,
+    VIN11,
+    VIN12,
+    VBIAS2,
+    VBIAS1
+);
+        inout VOUT_AMP2;
+        inout VOUT_AMP1;
+        inout VIN22;
+        inout VIN21;
+        inout VIN11;
+        inout VIN12;
+        inout VBIAS2;
+        inout VBIAS1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_TA2SIGNALBIASCELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_STEPUPDIGITALPART1
+`define SKY130_HILAS_STEPUPDIGITALPART1
+
+/**
+ * sky130_hilas_StepUpDigitalPart1: step-up level shifter part
+ *
+ * Verilog wrapper for sky130_hilas_StepUpDigitalPart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigitalPart1 (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigitalPart1 (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_STEPUPDIGITALPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_STEPUPDIGITAL
+`define SKY130_HILAS_STEPUPDIGITAL
+
+/**
+ * sky130_hilas_StepUpDigital: a single level shifter
+ *
+ * Verilog wrapper for sky130_hilas_StepUpDigital.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigital (
+    VNB,
+    VPB
+);
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigital (
+    
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_STEPUPDIGITAL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATE4DOUBLE01
+`define SKY130_HILAS_TGATE4DOUBLE01
+
+/**
+ * sky130_hilas_Tgate4Double01: 4 double-throw transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_Tgate4Double01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Double01 (
+    INPUT1_1,
+    SELECT1,
+    SELECT2,
+    INPUT2_2,
+    INPUT1_2,
+    SELECT3,
+    INPUT2_3,
+    SELECT4,
+    INPUT2_4,
+    INPUT1_4,
     OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4,
-    DRAIN1,
-    GATE1,
-    VTUN,
-    WTAMIDDLENODE,
-    COLSEL1,
-    VINJ,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4,
+    OUTPUT3,
+    OUTPUT2,
+    OUTPUT1,
+    INPUT2_1,
+    INPUT1_3,
     VGND,
     VNB,
     VPB
 );
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
+        inout INPUT1_1;
+        inout SELECT1;
+        inout SELECT2;
+        inout INPUT2_2;
+        inout INPUT1_2;
+        inout SELECT3;
+        inout INPUT2_3;
+        inout SELECT4;
+        inout INPUT2_4;
+        inout INPUT1_4;
         inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-        inout DRAIN1;
-        inout GATE1;
-        inout VTUN;
-        inout WTAMIDDLENODE;
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
+        inout OUTPUT3;
+        inout OUTPUT2;
+        inout OUTPUT1;
+        inout INPUT2_1;
+        inout INPUT1_3;
         inout VGND;
         inout VNB;
         inout VPB;
@@ -10037,42 +10045,40 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_WTA4Stage01 (
-    OUTPUT1,
-    OUTPUT2,
-    OUTPUT3,
+module sky130_hilas_Tgate4Double01 (
+    INPUT1_1,
+    SELECT1,
+    SELECT2,
+    INPUT2_2,
+    INPUT1_2,
+    SELECT3,
+    INPUT2_3,
+    SELECT4,
+    INPUT2_4,
+    INPUT1_4,
     OUTPUT4,
-    INPUT1,
-    INPUT2,
-    INPUT3,
-    INPUT4,
-    DRAIN1,
-    GATE1,
-    VTUN,
-    WTAMIDDLENODE,
-    COLSEL1,
-    VINJ,
-    DRAIN2,
-    DRAIN3,
-    DRAIN4
+    OUTPUT3,
+    OUTPUT2,
+    OUTPUT1,
+    INPUT2_1,
+    INPUT1_3
 );
-        inout OUTPUT1;
-        inout OUTPUT2;
-        inout OUTPUT3;
+        inout INPUT1_1;
+        inout SELECT1;
+        inout SELECT2;
+        inout INPUT2_2;
+        inout INPUT1_2;
+        inout SELECT3;
+        inout INPUT2_3;
+        inout SELECT4;
+        inout INPUT2_4;
+        inout INPUT1_4;
         inout OUTPUT4;
-        inout INPUT1;
-        inout INPUT2;
-        inout INPUT3;
-        inout INPUT4;
-        inout DRAIN1;
-        inout GATE1;
-        inout VTUN;
-        inout WTAMIDDLENODE;
-        inout COLSEL1;
-        inout VINJ;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout DRAIN4;
+        inout OUTPUT3;
+        inout OUTPUT2;
+        inout OUTPUT1;
+        inout INPUT2_1;
+        inout INPUT1_3;
 endmodule
 `endcelldefine
 
@@ -10080,18 +10086,18 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_WTA4STAGE01
+`endif  // SKY130_HILAS_TGATE4DOUBLE01
 
 
 //--------EOF---------
 
-`ifndef SKY130_HILAS_SWC4X2CELLOVERLAP
-`define SKY130_HILAS_SWC4X2CELLOVERLAP
+`ifndef SKY130_HILAS_HORIZTRANSCELL01
+`define SKY130_HILAS_HORIZTRANSCELL01
 
 /**
- * sky130_hilas_swc4x2cellOverlap: Core switch cell, built with overlap capacitor
+ * sky130_hilas_horizTransCell01: None
  *
- * Verilog wrapper for sky130_hilas_swc4x2cellOverlap.
+ * Verilog wrapper for sky130_hilas_horizTransCell01.
  *
  * WARNING: This file is autogenerated, do not modify directly!
  */
@@ -10104,42 +10110,10 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_swc4x2cellOverlap (
-    VERT1,
-    HORIZ1,
-    DRAIN1,
-    HORIZ2,
-    DRAIN2,
-    DRAIN3,
-    HORIZ3,
-    HORIZ4,
-    DRAIN4,
-    VINJ,
-    GATESELECT1,
-    VERT2,
-    GATESELECT2,
-    GATE2,
-    GATE1,
-    VTUN,
+module sky130_hilas_horizTransCell01 (
     VNB,
     VPB
 );
-        inout VERT1;
-        inout HORIZ1;
-        inout DRAIN1;
-        inout HORIZ2;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout HORIZ3;
-        inout HORIZ4;
-        inout DRAIN4;
-        inout VINJ;
-        inout GATESELECT1;
-        inout VERT2;
-        inout GATESELECT2;
-        inout GATE2;
-        inout GATE1;
-        inout VTUN;
         inout VNB;
         inout VPB;
 endmodule
@@ -10150,40 +10124,9 @@
 /*********************************************************/
 
 `celldefine
-module sky130_hilas_swc4x2cellOverlap (
-    VERT1,
-    HORIZ1,
-    DRAIN1,
-    HORIZ2,
-    DRAIN2,
-    DRAIN3,
-    HORIZ3,
-    HORIZ4,
-    DRAIN4,
-    VINJ,
-    GATESELECT1,
-    VERT2,
-    GATESELECT2,
-    GATE2,
-    GATE1,
-    VTUN
+module sky130_hilas_horizTransCell01 (
+    
 );
-        inout VERT1;
-        inout HORIZ1;
-        inout DRAIN1;
-        inout HORIZ2;
-        inout DRAIN2;
-        inout DRAIN3;
-        inout HORIZ3;
-        inout HORIZ4;
-        inout DRAIN4;
-        inout VINJ;
-        inout GATESELECT1;
-        inout VERT2;
-        inout GATESELECT2;
-        inout GATE2;
-        inout GATE1;
-        inout VTUN;
 endmodule
 `endcelldefine
 
@@ -10191,7 +10134,64 @@
 `endif // USE_POWER_PINS
 
 `default_nettype wire
-`endif  // SKY130_HILAS_SWC4X2CELLOVERLAP
+`endif  // SKY130_HILAS_HORIZTRANSCELL01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_RESISTOR01
+`define SKY130_HILAS_RESISTOR01
+
+/**
+ * sky130_hilas_resistor01: 
+ *
+ * Verilog wrapper for sky130_hilas_resistor01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_resistor01 (
+    TERM1,
+    TERM2,
+    VGND,
+    VNB,
+    VPB
+);
+        inout TERM1;
+        inout TERM2;
+        inout VGND;
+        inout VNB;
+        inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_resistor01 (
+    TERM1,
+    TERM2
+);
+        inout TERM1;
+        inout TERM2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_HILAS_RESISTOR01
 
 
 //--------EOF---------
\ No newline at end of file