Update

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index ac8085a..aa790d5 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -31,6 +31,7 @@
     //`include "../gl/user_proj_example.v"
    
   // for rtl verification
+    `include "user_project_wrapper.v"
     `include "user_proj_example.v"
     `include "BrqRV_EB1/BrqRV_EB1.v"