Update

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b8ae917..b03a01f 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v

@@ -144,8 +144,8 @@
    //=========================================================================-
 eb1_brqrv_wrapper brqrv_top (
 `ifdef USE_POWER_PINS
-    .VPWR		     ( vccd1	      ),
-    .VGND                   ( vssd1         ),
+    .vccd1		     ( vccd1	      ),
+    .vssd1                   ( vssd1         ),
 `endif
     .rst_l                  ( rst           ),
     .dbg_rst_l              ( ~wb_rst_i     ),