Added Project Files

verilog/rtl/BrqRV_EB1/design/Defines/common_defines.vh

diff --git a/verilog/rtl/BrqRV_EB1/design/Defines/common_defines.vh b/verilog/rtl/BrqRV_EB1/design/Defines/common_defines.vh
index 2c9f8c5..9e581ff 100644
--- a/verilog/rtl/BrqRV_EB1/design/Defines/common_defines.vh
+++ b/verilog/rtl/BrqRV_EB1/design/Defines/common_defines.vh
@@ -104,7 +104,7 @@
 `define RV_ICCM_INDEX_BITS 8
 `define RV_ICCM_NUM_BANKS 4
 `define RV_ICCM_NUM_BANKS_4 
-//`define TEC_RV_ICG clockhdr
+`define TEC_RV_ICG clockhdr
 `define RV_LSU2DMA 0
 `define RV_LSU_NUM_NBLOAD_WIDTH 2
 `define RV_ICCM_ONLY 1

verilog/rtl/BrqRV_EB1/design/common_defines.vh

diff --git a/verilog/rtl/BrqRV_EB1/design/common_defines.vh b/verilog/rtl/BrqRV_EB1/design/common_defines.vh
index 2c9f8c5..9e581ff 100644
--- a/verilog/rtl/BrqRV_EB1/design/common_defines.vh
+++ b/verilog/rtl/BrqRV_EB1/design/common_defines.vh
@@ -104,7 +104,7 @@
 `define RV_ICCM_INDEX_BITS 8
 `define RV_ICCM_NUM_BANKS 4
 `define RV_ICCM_NUM_BANKS_4 
-//`define TEC_RV_ICG clockhdr
+`define TEC_RV_ICG clockhdr
 `define RV_LSU2DMA 0
 `define RV_LSU_NUM_NBLOAD_WIDTH 2
 `define RV_ICCM_ONLY 1