Update
diff --git a/README.md b/README.md index 4a8aab4..0761c19 100644 --- a/README.md +++ b/README.md
@@ -1,6 +1,6 @@ # BrqRV EB1 RISC-V Core 1.0 from MERL -This repository contains the brqrv eb1 Core design RTL. Brqrv Eb1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline +This repository contains the BrqRV EB1 Core design RTL. BrqRV EB1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline ## Block Diagram  @@ -61,4 +61,4 @@ 4. run the make commad for RTL simulation 5. run the SIM=GL make command for netlist simulation -Note: Dont forget to add 0x00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes. +Note: Dont forget to add 00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.
diff --git a/info.yaml b/info.yaml index fd4a6a9..87a7136 100644 --- a/info.yaml +++ b/info.yaml
@@ -1,6 +1,6 @@ --- project: - description: "A template SoC for Google sponsored Open MPW shuttles for SKY130." + description: "A Small SoC for Google sponsored Open MPW shuttles for SKY130." foundry: "SkyWater" git_url: "https://github.com/HamzaShabbir517/caravel_BrqRV_EB1.git" organization: "Micro Electronics Research Lab (MERL)"
diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v index 742022e..5c88d59 100644 --- a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v +++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
@@ -11832,13 +11832,15 @@ found = 1'b0; begin : sv2v_autoblock_42 reg signed [31:0] i; - for (i = 0; (i < 32) && (found == 0); i = i + 1) - if (bitmanip_lzd_os[31] == 1'b0) begin - bitmanip_dw_lzd_enc[5:0] = bitmanip_dw_lzd_enc[5:0] + 6'b000001; - bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1; + for (i = 0; (i < 32); i = i + 1) + if(found == 0) begin + if (bitmanip_lzd_os[31] == 1'b0) begin + bitmanip_dw_lzd_enc[5:0] = bitmanip_dw_lzd_enc[5:0] + 6'b000001; + bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1; + end + else + found = 1'b1; end - else - found = 1'b1; end end assign bitmanip_clz_ctz_result[5:0] = {6 {bitmanip_clz_ctz_sel}} & {bitmanip_dw_lzd_enc[5], {5 {~bitmanip_dw_lzd_enc[5]}} & bitmanip_dw_lzd_enc[4:0]}; @@ -14873,7 +14875,7 @@ begin : sv2v_autoblock_43 reg signed [31:0] j; for (j = 0; j < LRU_SIZE; j = j + 1) - if (btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]] == sv2v_cast_C4842_signed(j)) begin + if (btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]] == j[6:0]) begin btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH]; btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH]; end @@ -14881,7 +14883,7 @@ begin : sv2v_autoblock_44 reg signed [31:0] j; for (j = 0; j < LRU_SIZE; j = j + 1) - if (btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]] == sv2v_cast_C4842_signed(j)) begin + if (btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]] == j[6:0]) begin btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH]; btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH]; end