Update

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index a08394e..ce8c498 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,8 +25,8 @@
     `include "gl/user_proj_example.v"
 `else
     `include "user_project_wrapper.v"
-    `include "powered_netlist.v"
-    //`include "user_proj_example.v"
-    //`include "BrqRV_EB1/BrqRV_EB1.v"
+    //`include "powered_netlist.v"
+    `include "user_proj_example.v"
+    `include "BrqRV_EB1/BrqRV_EB1.v"
     `include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 `endif

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 5ed2484..b258650 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -100,7 +100,7 @@
     wire [63:0]	lsu_axi_wdata;
     wire [7:0]         lsu_axi_wstrb;
     reg		lsu_axi_bvalid;
-    reg  [2:0]	        lsu_axi_bid;
+    //reg  [2:0]	        lsu_axi_bid;
 
 
     // WB MI A
@@ -119,7 +119,7 @@
     
     always @(posedge wb_clk_i) begin
     	lsu_axi_bvalid = (lsu_axi_wvalid) ? 1'b1 : 1'b0;
-    	lsu_axi_bid    = (| lsu_axi_wstrb[3:0]) ? 3'b000 : (| lsu_axi_wstrb[7:4]) ? 3'b001 : 3'b000;
+    	//lsu_axi_bid    = (| lsu_axi_wstrb[3:0]) ? 3'b000 : (| lsu_axi_wstrb[7:4]) ? 3'b001 : 3'b000;
     end
     // IRQ
     assign irq = 3'b000;	// Unused
@@ -245,7 +245,7 @@
     .lsu_axi_bvalid         (lsu_axi_bvalid),
     .lsu_axi_bready         (),
     .lsu_axi_bresp          (2'b00),
-    .lsu_axi_bid            (lsu_axi_bid),
+    .lsu_axi_bid            (3'b000),
 
 
     .lsu_axi_arvalid        (),