Update

diff --git a/README.md b/README.md
index da4da77..4a8aab4 100644
--- a/README.md
+++ b/README.md

@@ -16,6 +16,8 @@
     
     ├── verlog                               #   User verilog Directory
     │   ├── rtl                              #   RTL
+    |       ├── user_project_wrapper.v       #   User Project Wrapper source file
+    |       ├── user_proj_example.v          #   User Project Example source file
     |       ├── Brqrv_EB1                    #   BrqRV_EB1 folder
     |           ├── Brqrv_EB1.v                                     #   BrqRV_EB1 source file
     |           ├── sky130_sram_1kbyte_1rw1r_32x256_8.v             #   1KB sram
@@ -32,18 +34,21 @@
   
     ├── verlog                               #   User verilog Directory
     │   ├── gl                               #   Gate Level Netlis
-    │       ├── BrqRV_EB1                    #   User Design Netlist
+    │       ├── user_project_wrapper.v       #   User Project Wrapper Netlist
+    │       ├── user_proj_example.v          #   User Project Example Netlist
     
  # The hardened macros are placed here:
 
     ├── def                                 #    def Directory
-    │   ├── BrqRV_EB1                       #    User Design def
+    │   ├── user_project_wrapper.def        #    User Project Wrapper def file
     
     ├── lef                                 #    lef Directory
-    │   ├── BrqRV_EB1                       #    User Design lef
+    │   ├── user_project_wrapper.lef        #    User Project Wrapper lef file
+    │   ├── user_proj_example.lef           #    User Project Example lef file
     
     ├── gds                                 #    gds Directory
-    │   ├── BrqRV_EB1                       #    User Design gds
+    │   ├── user_project_wrapper.gdz.gz     #    User Project Wrapper gds
+    │   ├── user_proj_example.gdz.gz        #    User Project Example gds
 
 
 ### Testing of Design

diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv
index 5698e70..e7eb84c 100644
--- a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv
+++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv

@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
 // performance monitor stuff
 //`ifndef eb1_DEF_SV
 //`define eb1_DEF_SV