Added Project Files
diff --git a/verilog/rtl/BrqRV_EB1/design/eb1_brqrv_wrapper.sv b/verilog/rtl/BrqRV_EB1/design/eb1_brqrv_wrapper.sv index 8c40946..d5f9a69 100644 --- a/verilog/rtl/BrqRV_EB1/design/eb1_brqrv_wrapper.sv +++ b/verilog/rtl/BrqRV_EB1/design/eb1_brqrv_wrapper.sv
@@ -707,7 +707,7 @@ eb1_mem #(.pt(pt)) mem ( .clk(active_l2clk), .rst_l(rst_l), - .iccm_rw_addr((core_rst) ? iccm_rw_addr : iccm_instr_addr), + .iccm_rw_addr((core_rst) ? iccm_rw_addr : iccm_instr_addr[10:0]), .iccm_wren((core_rst) ? iccm_wren : iccm_instr_we), .iccm_wr_data((core_rst) ? iccm_wr_data : {7'h0,iccm_instr_wdata,7'h0,iccm_instr_wdata}), .iccm_wr_size((core_rst) ? iccm_wr_size : 3'b010),
diff --git a/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv index 9c3f77a..e91f6c5 100644 --- a/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv +++ b/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv
@@ -24,8 +24,10 @@ #( `include "eb1_param.vh" )( + `ifdef USE_POWER_PINS input logic vccd1, input logic vssd1, + `endif input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic rst_l, // reset, active low @@ -232,9 +234,9 @@ .csb0(~iccm_clken[i]), .web0(~wren_bank[i]), .wmask0(4'hf), - .addr0(addr_bank[i]), - .din0(iccm_bank_wr_data[i]), - .dout0(iccm_bank_dout[i]), + .addr0(addr_bank[i][7:0]), + .din0(iccm_bank_wr_data[i][31:0]), + .dout0(iccm_bank_dout[i][31:0]), .clk1(clk), .csb1(1'b1), .addr1(10'h000),
diff --git a/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv index d23079c..9613df1 100644 --- a/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv +++ b/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv
@@ -44,8 +44,10 @@ #( `include "eb1_param.vh" )( +`ifdef USE_POWER_PINS input logic vccd1, input logic vssd1, + `endif input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic rst_l, // reset, active low @@ -310,9 +312,9 @@ .csb0(~dccm_clken[i]), .web0(~wren_bank[i]), .wmask0(4'hf), - .addr0(addr_bank[i]), - .din0(wr_data_bank[i]), - .dout0(dccm_bank_dout[i]), + .addr0(addr_bank[i][7:0]), + .din0(wr_data_bank[i][31:0]), + .dout0(dccm_bank_dout[i][31:0]), .clk1(clk), .csb1(1'b1), .addr1(10'h000),
diff --git a/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv index 9c3f77a..e91f6c5 100644 --- a/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv +++ b/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv
@@ -24,8 +24,10 @@ #( `include "eb1_param.vh" )( + `ifdef USE_POWER_PINS input logic vccd1, input logic vssd1, + `endif input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic rst_l, // reset, active low @@ -232,9 +234,9 @@ .csb0(~iccm_clken[i]), .web0(~wren_bank[i]), .wmask0(4'hf), - .addr0(addr_bank[i]), - .din0(iccm_bank_wr_data[i]), - .dout0(iccm_bank_dout[i]), + .addr0(addr_bank[i][7:0]), + .din0(iccm_bank_wr_data[i][31:0]), + .dout0(iccm_bank_dout[i][31:0]), .clk1(clk), .csb1(1'b1), .addr1(10'h000),
diff --git a/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv index d23079c..9613df1 100644 --- a/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv +++ b/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv
@@ -44,8 +44,10 @@ #( `include "eb1_param.vh" )( +`ifdef USE_POWER_PINS input logic vccd1, input logic vssd1, + `endif input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic rst_l, // reset, active low @@ -310,9 +312,9 @@ .csb0(~dccm_clken[i]), .web0(~wren_bank[i]), .wmask0(4'hf), - .addr0(addr_bank[i]), - .din0(wr_data_bank[i]), - .dout0(dccm_bank_dout[i]), + .addr0(addr_bank[i][7:0]), + .din0(wr_data_bank[i][31:0]), + .dout0(dccm_bank_dout[i][31:0]), .clk1(clk), .csb1(1'b1), .addr1(10'h000),