Update

verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v

diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index e529863..f48916d 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -83,13 +83,13 @@
             wait(mprj_io_0 == 28'd13);
             */
             // Observe Output pins [35:8] for multliplication_table
-            wait(mprj_io_0 == 28'd5);
+            /*wait(mprj_io_0 == 28'd5);
             wait(mprj_io_0 == 28'd10);
             wait(mprj_io_0 == 28'd15);
             wait(mprj_io_0 == 28'd20);
             wait(mprj_io_0 == 28'd25);
             wait(mprj_io_0 == 28'd30);
-            
+            */
             // Observe Output pins [35:8] for mean & Determinant
             //wait(mprj_io_0 == 28'd5);
             
@@ -100,9 +100,9 @@
             //wait(mprj_io_0 == 28'd4889874);
             
             // Observe Output pins [35:8] for Queue 
-           // wait(mprj_io_0 == 28'd5);
-           // wait(mprj_io_0 == 28'd6);
-           // wait(mprj_io_0 == 28'd7);
+            wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd7);
             
             // Observe Output pins [35:8] for perfect square
             //wait(mprj_io_0 == 28'd5);
@@ -125,7 +125,7 @@
             //wait(mprj_io_0 == 28'd2);
             //wait(mprj_io_0 == 28'd1);
             //wait(mprj_io_0 == 28'd0);
-            $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[35:8],$time);  
+            $display("MPRJ-IO state = %d", mprj_io[35:8]);  
 		
 		`ifdef GL
 	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
@@ -161,7 +161,7 @@
 	end
 	
 	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %d ", mprj_io[35:8]);
+		#1 $display("MPRJ-IO state = %d, at time = %0t  ", mprj_io[35:8], $time);
 	end
 	
 	wire flash_csb;

verilog/dv/hex/uart.hex

diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index 5509980..5a3b56e 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,6 +1,12 @@
 @00000000

-B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92

-44 99 44 15 03 B7 43 01 0E 37 F0 04 03 05 D0 58

-02 64 02 B3 00 53 A0 23 00 5E 20 23 0E 11 03 91

-FE 93 17 E3 D0 58 01 B7 0F F0 02 93 00 51 80 23

-FE 00 0A E3 00 01 00 01 00 00 0F FF 

+B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92

+04 93 F0 04 09 13 00 50 09 93 00 60 0A 13 00 70

+02 93 00 30 03 13 00 00 03 93 00 10 0E 13 00 20

+00 EF 00 30 A0 0D 00 60 87 63 02 85 87 63 00 62

+88 63 00 72 80 82 01 C2 B7 FD C0 04 01 24 22 23

+24 23 B7 E5 B7 CD 01 34 00 04 22 83 00 44 23 03

+00 84 23 83 D0 58 0B 37 00 5B 20 23 00 01 0B 11

+00 01 00 01 20 23 00 01 0B 11 00 6B 00 01 00 01

+20 23 00 01 00 01 00 7B 00 01 00 01 D0 58 01 B7

+0F F0 02 93 00 51 80 23 FE 00 0A E3 00 01 00 01

+00 00 0F FF