Update

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index ee85a1f..ac8085a 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -24,9 +24,14 @@
     `include "gl/user_project_wrapper.v"
     `include "gl/user_proj_example.v"
 `else
-    `include "user_project_wrapper.v"
-    `include "../gl/user_proj_example.v"
-    //`include "user_proj_example.v"
-    //`include "BrqRV_EB1/BrqRV_EB1.v"
     `include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+   
+   // for netlist verification
+    //`include "../gl/user_project_wrapper.v"
+    //`include "../gl/user_proj_example.v"
+   
+  // for rtl verification
+    `include "user_proj_example.v"
+    `include "BrqRV_EB1/BrqRV_EB1.v"
+    
 `endif