Update

verilog/rtl/BrqRV_EB1/BrqRV_EB1.v

diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
index 6915c6a..fcb6478 100644
--- a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
+++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
@@ -15308,7 +15308,7 @@
 					.dout0(iccm_bank_dout[(i * 39) + 31-:32]),
 					.clk1(clk),
 					.csb1(1'b1),
-					.addr1(10'h000),
+					.addr1(8'h00),
 					.dout1()
 				);
 			end
@@ -15347,7 +15347,7 @@
 					.dout0(iccm_bank_dout[i * 39+:39]),
 					.clk1(clk),
 					.csb1(1'b1),
-					.addr1(10'h000),
+					.addr1(8'h00),
 					.dout1()
 				);
 			end
@@ -20828,7 +20828,7 @@
 					.dout0(dccm_bank_dout[i * pt[1360-:10]+:pt[1360-:10]]),
 					.clk1(clk),
 					.csb1(1'b1),
-					.addr1(10'h000),
+					.addr1(8'h00),
 					.dout1()
 				);
 			end
@@ -20868,7 +20868,7 @@
 					.dout0(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
 					.clk1(clk),
 					.csb1(1'b1),
-					.addr1(10'h000),
+					.addr1(8'h00),
 					.dout1()
 				);
 			end
@@ -22972,6 +22972,8 @@
 	wire SE;
 	assign SE = 0;
 	sky130_fd_sc_hd__dlclkp_1 clkhdr(
+		.VPWR(1'b1),
+		.VGND(1'b0),
 		.CLK(clk),
 		.GCLK(l1clk),
 		.GATE(en)
@@ -22990,6 +22992,8 @@
 	wire SE;
 	assign SE = 0;
 	sky130_fd_sc_hd__dlclkp_1 clkhdr(
+		.VPWR(1'b1),
+		.VGND(1'b0),
 		.CLK(clk),
 		.GCLK(l1clk),
 		.GATE(en)

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index a836eed..0bab84b 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -39,14 +39,14 @@
     parameter BITS = 32
 )(
 `ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
+    //inout vdda1,	// User area 1 3.3V supply
+    //inout vdda2,	// User area 2 3.3V supply
+    //inout vssa1,	// User area 1 analog ground
+    //inout vssa2,	// User area 2 analog ground
     inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
+    //inout vccd2,	// User area 2 1.8v supply
     inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
+    //inout vssd2,	// User area 2 digital ground
 `endif
 
     // Wishbone Slave ports (WB MI A)

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2a3462b..2e0e44b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -84,14 +84,14 @@
 
 user_proj_example mprj (
     `ifdef USE_POWER_PINS
-	.vdda1(vdda1),	// User area 1 3.3V power
-	.vdda2(vdda2),	// User area 2 3.3V power
-	.vssa1(vssa1),	// User area 1 analog ground
-	.vssa2(vssa2),	// User area 2 analog ground
+	//.vdda1(vdda1),	// User area 1 3.3V power
+	//.vdda2(vdda2),	// User area 2 3.3V power
+	//.vssa1(vssa1),	// User area 1 analog ground
+	//.vssa2(vssa2),	// User area 2 analog ground
 	.vccd1(vccd1),	// User area 1 1.8V power
-	.vccd2(vccd2),	// User area 2 1.8V power
+	//.vccd2(vccd2),	// User area 2 1.8V power
 	.vssd1(vssd1),	// User area 1 digital ground
-	.vssd2(vssd2),	// User area 2 digital ground
+	//.vssd2(vssd2),	// User area 2 digital ground
     `endif
 
     .wb_clk_i(wb_clk_i),