Added Project Files

verilog/rtl/BrqRV_EB1/design/iccm_controller.v

diff --git a/verilog/rtl/BrqRV_EB1/design/iccm_controller.v b/verilog/rtl/BrqRV_EB1/design/iccm_controller.v
index 611396f..c28bc9d 100644
--- a/verilog/rtl/BrqRV_EB1/design/iccm_controller.v
+++ b/verilog/rtl/BrqRV_EB1/design/iccm_controller.v
@@ -82,7 +82,7 @@
 	always @(posedge clk_i or negedge rst_ni)
 		if (!rst_ni) begin
 			we_q <= 1'b0;
-			addr_q <= 13'b0000000000000;
+			addr_q <= 14'b00000000000000;
 			rx_byte_q0 <= 8'b00000000;
 			rx_byte_q1 <= 8'b00000000;
 			rx_byte_q2 <= 8'b00000000;

verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v

diff --git a/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v b/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v
index 611396f..c28bc9d 100644
--- a/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v
+++ b/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v
@@ -82,7 +82,7 @@
 	always @(posedge clk_i or negedge rst_ni)
 		if (!rst_ni) begin
 			we_q <= 1'b0;
-			addr_q <= 13'b0000000000000;
+			addr_q <= 14'b00000000000000;
 			rx_byte_q0 <= 8'b00000000;
 			rx_byte_q1 <= 8'b00000000;
 			rx_byte_q2 <= 8'b00000000;