Update

verilog/dv/BrqRV_EB1/BrqRV_EB1.c

diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
index 58183c3..2422d93 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
@@ -56,7 +56,7 @@
   reg_la1_oenb = reg_la1_iena =  0x00000000;
   reg_la1_data = 0x00000015C; // Clk_per_bit
   
-  reg_la0_oenb = reg_la0_iena = 0x00000000;
+  reg_la0_oenb = reg_la0_iena = 0x00000002;
   reg_la0_data = 0x00000000;
   reg_mprj_datah = 0x20;
 

verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v

diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 26c66ad..086010a 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -81,6 +81,7 @@
     	    wait(mprj_io_0 == 28'd7);
 	    wait(mprj_io_0 == 28'd11);
             wait(mprj_io_0 == 28'd13);*/
+            
             // Observe Output pins [35:8] for multliplication_table
             wait(mprj_io_0 == 28'd5);
             wait(mprj_io_0 == 28'd10);
@@ -88,6 +89,11 @@
             wait(mprj_io_0 == 28'd20);
             wait(mprj_io_0 == 28'd25);
             wait(mprj_io_0 == 28'd30);
+            
+            // Observe Output pins [35:8] for Quadratic_eq
+            //wait(mprj_io_0 == 28'd8);
+            //wait(mprj_io_0 == 28'd7);
+            
             $display("MPRJ-IO state = %d ", mprj_io[35:8]);  
 		
 		`ifdef GL

verilog/dv/hex/roots_of_quadratic_eq.hex

diff --git a/verilog/dv/hex/roots_of_quadratic_eq.hex b/verilog/dv/hex/roots_of_quadratic_eq.hex
new file mode 100755
index 0000000..3fb6e08
--- /dev/null
+++ b/verilog/dv/hex/roots_of_quadratic_eq.hex
@@ -0,0 +1,11 @@
+@00000000

+@00000000

+B0 20 10 73 B8 20 10 73 10 73 42 11 44 05 7F 92

+09 13 54 C5 4E 91 03 80 09 93 4F 01 82 B3 0C 80

+03 33 02 94 03 33 03 24 83 B3 03 D3 C3 63 40 62

+0F 05 05 E9 03 EF 0F B3 FE 7F CB E3 82 B3 4E 81

+83 33 40 9E 83 B3 01 E2 4A 09 41 E2 02 8A 0E B3

+03 D3 44 33 03 D3 C4 B3 F0 04 0A B7 00 8A A0 23

+A0 23 0A 91 0A B7 00 9A A0 23 D0 58 0A 91 00 8A

+00 9A A0 23 D0 58 01 B7 0F F0 02 93 00 51 80 23

+FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 806da28..a836eed 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -117,7 +117,7 @@
     assign clk = (~la_oenb[65]) ? la_data_in[65] :  wb_clk_i;
     //assign clk = wb_clk_i;
     assign rst = (~la_oenb[64]) ? la_data_in[64] : ~wb_rst_i;
-    assign rx_i = io_in[5];
+    assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];
     assign reset_vector = 32'haffff000;
     assign jtag_id[31:28] = 4'b1;
     assign jtag_id[27:12] = {16{1'b0}};