Sram
diff --git a/verilog/rtl/sram/common_pdn.tcl b/verilog/rtl/sram/common_pdn.tcl new file mode 100755 index 0000000..5ed194b --- /dev/null +++ b/verilog/rtl/sram/common_pdn.tcl
@@ -0,0 +1,105 @@ +# Power nets + +if { ! [info exists ::env(VDD_NET)] } { + set ::env(VDD_NET) $::env(VDD_PIN) +} + +if { ! [info exists ::env(GND_NET)] } { + set ::env(GND_NET) $::env(GND_PIN) +} + +set ::power_nets $::env(VDD_NET) +set ::ground_nets $::env(GND_NET) + +if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } { + if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } { + # to parameterize -- needs a PDNGEN fix + set pdngen::global_connections { + VPWR { + {inst_name .* pin_name VPWR} + {inst_name .* pin_name VPB} + } + VGND { + {inst_name .* pin_name VGND} + {inst_name .* pin_name VNB} + } + } + } +} + +# Used if the design is the core of the chip +set stdcell_core { + name grid + straps { + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}} +} + +# Used if the design is a macro in the core +set stdcell_macro { + name grid + straps { + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + } + connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}} +} + +# Assesses whether the deisgn is the core of the chip or not based on the value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section +if { [info exists ::env(DESIGN_IS_CORE)] } { + if { $::env(DESIGN_IS_CORE) == 1 } { + set stdcell $stdcell_core + } else { + set stdcell $stdcell_macro + } +} else { + set stdcell $stdcell_core +} + +# Adds the core ring if enabled. +if { [info exists ::env(FP_PDN_CORE_RING)] } { + if { $::env(FP_PDN_CORE_RING) == 1 } { + dict append stdcell core_ring { + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)} + $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_CORE_RING_HWIDTH) spacing $::env(FP_PDN_CORE_RING_HSPACING) core_offset $::env(FP_PDN_CORE_RING_HOFFSET)} + } + } +} + +# Adds the core ring if enabled. +if { [info exists ::env(FP_PDN_ENABLE_RAILS)] } { + if { $::env(FP_PDN_ENABLE_RAILS) == 1 } { + dict append stdcell rails { + $::env(FP_PDN_RAILS_LAYER) {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)} + } + dict update stdcell connect current_connect { + append current_connect { {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}} + } + } else { + dict append stdcell rails {} + } +} + +pdngen::specify_grid stdcell [subst $stdcell] + +# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs +# TODO: generate automatically per instance: +set macro { + orient {R0 R180 MX MY R90 R270 MXR90 MYR90 + }power_pins vccd1 + ground_pins vssd1 + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}} +} +#pdngen::specify_grid macro [subst $macro] + +set ::halo [expr min($::env(FP_HORIZONTAL_HALO), $::env(FP_VERTICAL_HALO))] + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/verilog/rtl/sram/config.tcl b/verilog/rtl/sram/config.tcl new file mode 100755 index 0000000..04428b0 --- /dev/null +++ b/verilog/rtl/sram/config.tcl
@@ -0,0 +1,57 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set script_dir [file dirname [file normalize [info script]]] + +source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl + +set ::env(DESIGN_NAME) user_project_wrapper +#section end + +# User Configurations + +## Source Verilog Files +set ::env(VERILOG_FILES) "\ + $script_dir/../../caravel/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/user_project_wrapper.v \ + $script_dir/../../verilog/rtl/user_proj_example.v \ + $script_dir/../../verilog/rtl/BrqRV_EB1/BrqRV_EB1.v " +#blackbox setup +set ::env(VERILOG_FILES_BLACKBOX) "\ + $script_dir/../../caravel/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v " +set ::env(EXTRA_LEFS) $PDK_ROOT/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef +set ::env(EXTRA_GDS_FILES) $PDK_ROOT/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds + +set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_PERIOD) "40" + +set ::env(GLB_RT_ALLOW_CONGESTION) 1 +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_MINLAYER) 2 +set ::env(GLB_RT_ADJUSTMENT) 0.45 +set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1 +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(SYNTH_STRATEGY) "DELAY 0" + +#pin order and pdn path +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(PDN_CFG) $script_dir/common_pdn.tcl + + + + + +
diff --git a/verilog/rtl/sram/interactive.tcl.orig b/verilog/rtl/sram/interactive.tcl.orig new file mode 100755 index 0000000..629f097 --- /dev/null +++ b/verilog/rtl/sram/interactive.tcl.orig
@@ -0,0 +1,51 @@ +package require openlane +set script_dir [file dirname [file normalize [info script]]] + +prep -design $script_dir -tag user_project_wrapper -overwrite +set save_path $script_dir/../.. + +run_synthesis +init_floorplan +add_macro_placement mprj.brqrv_top.mem.Gen_dccm_enable.dccm.mem_bank\[0\].dccm.sram 150 150 N +add_macro_placement mprj.brqrv_top.mem.Gen_dccm_enable.dccm.mem_bank\[1\].dccm.sram 775 150 N +add_macro_placement mprj.brqrv_top.mem.Gen_dccm_enable.dccm.mem_bank\[2\].dccm.sram 1400 150 N +add_macro_placement mprj.brqrv_top.mem.Gen_dccm_enable.dccm.mem_bank\[3\].dccm.sram 2650 150 N + +add_macro_placement mprj.brqrv_top.mem.iccm.iccm.mem_bank\[0\].iccm.sram 150 2975 N +add_macro_placement mprj.brqrv_top.mem.iccm.iccm.mem_bank\[1\].iccm.sram 775 2975 N +add_macro_placement mprj.brqrv_top.mem.iccm.iccm.mem_bank\[2\].iccm.sram 1400 2975 N +add_macro_placement mprj.brqrv_top.mem.iccm.iccm.mem_bank\[3\].iccm.sram 2650 2975 N + +manual_macro_placement f + +place_io_ol +tap_decap_or +run_power_grid_generation +set ::env(YOSYS_REWRITE_VERILOG) 1 +global_placement_or +detailed_placement_or +run_cts +run_routing +write_powered_verilog -power vccd1 -ground vssd1 +set_netlist $::env(lvs_result_file_tag).powered.v +run_magic +run_magic_drc +run_magic_spice_export + +save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(tritonRoute_result_file_tag).def \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -maglef_path $::env(magic_result_file_tag).lef.mag \ + -spice_path $::env(magic_result_file_tag).spice \ + -verilog_path $::env(CURRENT_NETLIST)\ + -save_path $save_path \ + -tag $::env(RUN_TAG) + +run_lvs +run_antenna_check +calc_total_runtime +generate_final_summary_report +puts_success "Flow Completed Without Fatal Errors." + +
diff --git a/verilog/rtl/sram/pin_order.cfg b/verilog/rtl/sram/pin_order.cfg new file mode 100644 index 0000000..90cde69 --- /dev/null +++ b/verilog/rtl/sram/pin_order.cfg
@@ -0,0 +1,156 @@ +#BUS_SORT +#NR +analog_io\[8\] +io_in\[15\] +io_out\[15\] +io_oeb\[15\] +analog_io\[9\] +io_in\[16\] +io_out\[16\] +io_oeb\[16\] +analog_io\[10\] +io_in\[17\] +io_out\[17\] +io_oeb\[17\] +analog_io\[11\] +io_in\[18\] +io_out\[18\] +io_oeb\[18\] +analog_io\[12\] +io_in\[19\] +io_out\[19\] +io_oeb\[19\] +analog_io\[13\] +io_in\[20\] +io_out\[20\] +io_oeb\[20\] +analog_io\[14\] +io_in\[21\] +io_out\[21\] +io_oeb\[21\] +analog_io\[15\] +io_in\[22\] +io_out\[22\] +io_oeb\[22\] +analog_io\[16\] +io_in\[23\] +io_out\[23\] +io_oeb\[23\] + +#S +wb_.* +wbs_.* +la_.* +user_clock2 +user_irq.* + +#E +io_in\[0\] +io_out\[0\] +io_oeb\[0\] +io_in\[1\] +io_out\[1\] +io_oeb\[1\] +io_in\[2\] +io_out\[2\] +io_oeb\[2\] +io_in\[3\] +io_out\[3\] +io_oeb\[3\] +io_in\[4\] +io_out\[4\] +io_oeb\[4\] +io_in\[5\] +io_out\[5\] +io_oeb\[5\] +io_in\[6\] +io_out\[6\] +io_oeb\[6\] +analog_io\[0\] +io_in\[7\] +io_out\[7\] +io_oeb\[7\] +analog_io\[1\] +io_in\[8\] +io_out\[8\] +io_oeb\[8\] +analog_io\[2\] +io_in\[9\] +io_out\[9\] +io_oeb\[9\] +analog_io\[3\] +io_in\[10\] +io_out\[10\] +io_oeb\[10\] +analog_io\[4\] +io_in\[11\] +io_out\[11\] +io_oeb\[11\] +analog_io\[5\] +io_in\[12\] +io_out\[12\] +io_oeb\[12\] +analog_io\[6\] +io_in\[13\] +io_out\[13\] +io_oeb\[13\] +analog_io\[7\] +io_in\[14\] +io_out\[14\] +io_oeb\[14\] + +#WR +analog_io\[17\] +io_in\[24\] +io_out\[24\] +io_oeb\[24\] +analog_io\[18\] +io_in\[25\] +io_out\[25\] +io_oeb\[25\] +analog_io\[19\] +io_in\[26\] +io_out\[26\] +io_oeb\[26\] +analog_io\[20\] +io_in\[27\] +io_out\[27\] +io_oeb\[27\] +analog_io\[21\] +io_in\[28\] +io_out\[28\] +io_oeb\[28\] +analog_io\[22\] +io_in\[29\] +io_out\[29\] +io_oeb\[29\] +analog_io\[23\] +io_in\[30\] +io_out\[30\] +io_oeb\[30\] +analog_io\[24\] +io_in\[31\] +io_out\[31\] +io_oeb\[31\] +analog_io\[25\] +io_in\[32\] +io_out\[32\] +io_oeb\[32\] +analog_io\[26\] +io_in\[33\] +io_out\[33\] +io_oeb\[33\] +analog_io\[27\] +io_in\[34\] +io_out\[34\] +io_oeb\[34\] +analog_io\[28\] +io_in\[35\] +io_out\[35\] +io_oeb\[35\] +io_in\[36\] +io_out\[36\] +io_oeb\[36\] +io_in\[37\] +io_out\[37\] +io_oeb\[37\]