Update

verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v

diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 900ef3b..e31e678 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -63,7 +63,7 @@
 	initial begin
 	    wait(mprj_ready == 1'b1)
 	    // Observe Output pins [35:8] for factorial
-	    /*wait(mprj_io_0 == 28'h0000001);
+	    wait(mprj_io_0 == 28'h0000001);
 	    wait(mprj_io_0 == 28'h0000002);
 	    wait(mprj_io_0 == 28'h0000006);
     	    wait(mprj_io_0 == 28'h0000018);
@@ -73,23 +73,23 @@
             wait(mprj_io_0 == 28'h0009D80);
 	    wait(mprj_io_0 == 28'h0058980);
             wait(mprj_io_0 == 28'h0375F00);
-            */
+            
             // Observe Output pins [35:8] for prime_num
 	    /*wait(mprj_io_0 == 28'd1);
 	    wait(mprj_io_0 == 28'd3);
 	    wait(mprj_io_0 == 28'd5);
     	    wait(mprj_io_0 == 28'd7);
 	    wait(mprj_io_0 == 28'd11);
-            wait(mprj_io_0 == 28'd13);*/
-            
+            wait(mprj_io_0 == 28'd13);
+            */
             // Observe Output pins [35:8] for multliplication_table
-            wait(mprj_io_0 == 28'd5);
+            /*wait(mprj_io_0 == 28'd5);
             wait(mprj_io_0 == 28'd10);
             wait(mprj_io_0 == 28'd15);
             wait(mprj_io_0 == 28'd20);
             wait(mprj_io_0 == 28'd25);
             wait(mprj_io_0 == 28'd30);
-            
+            */
             // Observe Output pins [35:8] for mean & Determinant
             //wait(mprj_io_0 == 28'd5);
             

verilog/dv/hex/uart.hex

diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index 729fbe7..6a24372 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,6 +1,9 @@
 @00000000

-B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92

-42 81 44 3D F0 04 03 37 02 93 4E 05 03 B7 00 04

-20 23 D0 58 A0 23 00 53 03 91 00 53 85 63 03 11

-82 B3 00 02 B7 F5 41 C2 D0 58 01 B7 0F F0 02 93

-00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF 

+B0 20 10 73 B8 20 10 73 90 73 40 91 04 37 7F 90

+01 B7 F0 04 46 85 D0 58 00 A0 04 93 00 00 03 13

+00 10 05 93 00 10 06 13 02 B3 00 01 20 23 00 60

+03 05 00 54 9A E3 04 11 04 37 FE 64 A8 29 F0 04

+04 11 C0 0C 00 B1 A0 23 8D 63 01 91 06 85 00 96

+00 10 05 93 00 10 06 13 02 C5 85 B3 FE D6 02 E3

+BF DD 06 05 D0 58 01 B7 0F F0 02 93 00 51 80 23

+FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index ce8c498..d84ad9e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,8 +25,8 @@
     `include "gl/user_proj_example.v"
 `else
     `include "user_project_wrapper.v"
-    //`include "powered_netlist.v"
-    `include "user_proj_example.v"
-    `include "BrqRV_EB1/BrqRV_EB1.v"
+    `include "power.v"
+    //`include "user_proj_example.v"
+    //`include "BrqRV_EB1/BrqRV_EB1.v"
     `include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 `endif

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b258650..b8ae917 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -82,7 +82,7 @@
     input   user_clock2,
     
     // IRQ
-    output [2:0] irq
+    output [2:0] user_irq
 );
     wire clk;
     wire rst;
@@ -122,7 +122,7 @@
     	//lsu_axi_bid    = (| lsu_axi_wstrb[3:0]) ? 3'b000 : (| lsu_axi_wstrb[7:4]) ? 3'b001 : 3'b000;
     end
     // IRQ
-    assign irq = 3'b000;	// Unused
+    assign user_irq = 3'b000;	// Unused
 
     // LA
     assign la_data_out = (| lsu_axi_wstrb[3:0]) ? {{(127-BITS){1'b0}}, lsu_axi_wdata[31:0]} : (| lsu_axi_wstrb[7:4]) ? {{(127-BITS){1'b0}}, lsu_axi_wdata[63:32]} : {128{1'b0}};