gpio output fixed
diff --git a/verilog/rtl/registers.sv b/verilog/rtl/registers.sv index 51bd760..12c99b9 100644 --- a/verilog/rtl/registers.sv +++ b/verilog/rtl/registers.sv
@@ -15,7 +15,8 @@ output wire [31:0] opC, output wire [2:0] frm, - output wire [12:0] op_valids + output wire [12:0] op_valids, + output wire [31:0] result ); localparam base_addr = 32'h3000_0000; @@ -80,7 +81,6 @@ wire addr_result; wire wr_result; wire [31:0] result_ns; - wire [31:0] result; assign addr_result = (addr[31:0] == RESULT); assign wr_result = fpu_result_valid;
diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv index 0956d0d..3389db7 100644 --- a/verilog/rtl/user_proj_example.sv +++ b/verilog/rtl/user_proj_example.sv
@@ -88,12 +88,14 @@ wire wb_valid_f; wire wb_valid_ns; + wire [31:0] fpu_result; + assign la_write_en = |la_write; assign addr = la_write_en ? la_addr : rdwraddr; fpu_registers csrs ( .clk (clk ), .rst_l (rst_l ), - .fpu_result (out ), + .fpu_result (fpu_result ), .fpu_valids ({valid_out, op_out} ), .addr (addr ), .wren (wb_valid ), @@ -105,7 +107,8 @@ .opC (c ), .frm (round_mode ), .op_valids ({valid_in, op_in} ), - .ack (ack )); + .ack (ack ), + .result (out )); f_class #(8,24) fpu_fclass ( .in (a ), .result (fclass_out ) ); @@ -197,7 +200,7 @@ rvdff #(1) wb_valid_ff (.clk(clk), .rst_l(rst_l), .din(wb_valid_ns), .dout(wb_valid_f)); // return output data according to module enable - assign {out, exceptions} = ({37{illegal_op}} & {32'b0 ,5'b0 }) | + assign {fpu_result, exceptions} = ({37{illegal_op}} & {32'b0 ,5'b0 }) | ({37{sqrt_valid_out & wb_valid_f}} & {sqrt_out ,sqrt_exceptions }) | ({37{div_valid_out & wb_valid_f}} & {div_out ,div_exceptions }) | ({37{valid_in[8] & wb_valid_f}} & {mac_out ,mac_exceptions }) |