Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-035
/
9077811ebd859c710ab9c0beab27d41e7ee4cf0f
commit
9077811ebd859c710ab9c0beab27d41e7ee4cf0f
[
log
]
[
tgz
]
author
aghaalizeb-lm <agha.ali@lampromellon.com>
Thu May 27 12:10:36 2021 +0500
committer
aghaalizeb-lm <agha.ali@lampromellon.com>
Thu May 27 12:10:36 2021 +0500
tree
095a9e3172a156de3aeefecfa3c11013da7fd6c1
parent
bd3d52d089a460dbf1f6f97f9151b01cdd3ee35f
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diff
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ack logic update
verilog/rtl/fpu.sv
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diff
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verilog/rtl/registers.sv
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diff
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verilog/rtl/user_proj_example.sv
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diff
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3 files changed
tree: 095a9e3172a156de3aeefecfa3c11013da7fd6c1
.github/
caravel/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.