)]}'
{
  "commit": "9077811ebd859c710ab9c0beab27d41e7ee4cf0f",
  "tree": "095a9e3172a156de3aeefecfa3c11013da7fd6c1",
  "parents": [
    "bd3d52d089a460dbf1f6f97f9151b01cdd3ee35f"
  ],
  "author": {
    "name": "aghaalizeb-lm",
    "email": "agha.ali@lampromellon.com",
    "time": "Thu May 27 12:10:36 2021 +0500"
  },
  "committer": {
    "name": "aghaalizeb-lm",
    "email": "agha.ali@lampromellon.com",
    "time": "Thu May 27 12:10:36 2021 +0500"
  },
  "message": "ack logic update\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c6c5b011b5a03d7ea584a95e8a387e96f73db759",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpu.sv",
      "new_id": "04326bb33bade20a60212d5f8db6bd8bcefc7a95",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpu.sv"
    },
    {
      "type": "modify",
      "old_id": "bbfaa17bcef47b2f0bdf0745e84b65451f7dccfc",
      "old_mode": 33188,
      "old_path": "verilog/rtl/registers.sv",
      "new_id": "f2bfb43faad4321ab2a08b67b1deb9dcddf198ec",
      "new_mode": 33188,
      "new_path": "verilog/rtl/registers.sv"
    },
    {
      "type": "modify",
      "old_id": "a85198d1674db86fcf9b84b56f1ea6af1fcdcec8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.sv",
      "new_id": "569ae4f3ac6d81117f08fcb9ff35cde56398bb06",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.sv"
    }
  ]
}