commit	81c787caef7767b9a96c5dbed48cd7db1cdd6499	[log] [tgz]
author	hamzakhan1-lm <hamza.khan@lampromellon.com>	Wed Jun 16 16:37:17 2021 +0500
committer	hamzakhan1-lm <hamza.khan@lampromellon.com>	Wed Jun 16 16:37:17 2021 +0500
tree	f93c13ab0a14b94ec36289f8106bede65123ed4f
parent	40b8cad60d3e30c45c16abf985d3fb31fa86e9f6 [diff]

dv files updated

verilog/dv/Makefile[diff]
verilog/dv/README.md[diff]
verilog/dv/dv_defs.h[Added - diff]
verilog/dv/fpu_test_add_sub/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_add_sub/fpu_test_add_sub.c[Added - diff]
verilog/dv/fpu_test_add_sub/fpu_test_add_sub_tb.v[Added - diff]
verilog/dv/fpu_test_comp/Makefile[Renamed from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_comp/fpu_test_comp.c[Added - diff]
verilog/dv/fpu_test_comp/fpu_test_comp_tb.v[Added - diff]
verilog/dv/fpu_test_div/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_div/fpu_test_div.c[Added - diff]
verilog/dv/fpu_test_div/fpu_test_div_tb.v[Added - diff]
verilog/dv/fpu_test_f2i/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_f2i/fpu_test_f2i.c[Added - diff]
verilog/dv/fpu_test_f2i/fpu_test_f2i_tb.v[Added - diff]
verilog/dv/fpu_test_fclass/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_fclass/fpu_test_fclass.c[Added - diff]
verilog/dv/fpu_test_fclass/fpu_test_fclass_tb.v[Added - diff]
verilog/dv/fpu_test_fma/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_fma/fpu_test_fma.c[Added - diff]
verilog/dv/fpu_test_fma/fpu_test_fma_tb.v[Added - diff]
verilog/dv/fpu_test_i2f/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_i2f/fpu_test_i2f.c[Added - diff]
verilog/dv/fpu_test_i2f/fpu_test_i2f_tb.v[Added - diff]
verilog/dv/fpu_test_min_max/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_min_max/fpu_test_min_max.c[Added - diff]
verilog/dv/fpu_test_min_max/fpu_test_min_max_tb.v[Added - diff]
verilog/dv/fpu_test_multiply/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_multiply/fpu_test_multiply.c[Added - diff]
verilog/dv/fpu_test_multiply/fpu_test_multiply_tb.v[Added - diff]
verilog/dv/fpu_test_sign_inject/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject.c[Added - diff]
verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject_tb.v[Added - diff]
verilog/dv/fpu_test_sqrt/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/fpu_test_sqrt/fpu_test_sqrt.c[Added - diff]
verilog/dv/fpu_test_sqrt/fpu_test_sqrt_tb.v[Added - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports_fpu_test/Makefile[Renamed from verilog/dv/io_ports/Makefile - diff]
verilog/dv/io_ports_fpu_test/io_ports.c[Added - diff]
verilog/dv/io_ports_fpu_test/io_ports_tb.v[Renamed from verilog/dv/io_ports/io_ports_tb.v - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2_fpu/Makefile[Renamed from verilog/dv/la_test2/Makefile - diff]
verilog/dv/la_test2_fpu/la_test2.c[Renamed from verilog/dv/la_test2/la_test2.c - diff]
verilog/dv/la_test2_fpu/la_test2_tb.v[Renamed from verilog/dv/la_test2/la_test2_tb.v - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]

51 files changed

tree: f93c13ab0a14b94ec36289f8106bede65123ed4f

README.md

Table of contents

Caravel FPU

Caravel FPU

Floating Point Unit

FPU Architecture

The default rounding mode for all the operations is RNE as highlighted by RISC-V and IEEE-754 spec.

FPU Exceptions

Integration of FPU as Memory Mapped Peripheral

Wishbone Interface

Logic Analyzer

GPIO

Result of FPU calculation also appers at the 32 GPIO pins.

CSRs for FPU

Instruction Flow