commit	820812fed461fe4bffd84df6ea9906ac263ae61f	[log] [tgz]
author	komaljaved-lm <komal.javed@lampromellon.com>	Wed Jun 16 17:41:10 2021 +0500
committer	komaljaved-lm <komal.javed@lampromellon.com>	Wed Jun 16 17:41:10 2021 +0500
tree	c22ebdf3bf91c0fc5102d4266dedccef832bb065
parent	81c787caef7767b9a96c5dbed48cd7db1cdd6499 [diff]

updated repo with GDS and openlane config files

gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]

6 files changed

tree: c22ebdf3bf91c0fc5102d4266dedccef832bb065

README.md

Table of contents

Caravel FPU

Caravel FPU

Floating Point Unit

FPU Architecture

The default rounding mode for all the operations is RNE as highlighted by RISC-V and IEEE-754 spec.

FPU Exceptions

Integration of FPU as Memory Mapped Peripheral

Wishbone Interface

Logic Analyzer

GPIO

Result of FPU calculation also appers at the 32 GPIO pins.

CSRs for FPU

Instruction Flow