logic analyzer write bug fixed

verilog/rtl/user_proj_example.sv

diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index 3389db7..f5dbf40 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -92,6 +92,7 @@
 
   assign la_write_en              = |la_write;
   assign addr                     = la_write_en ? la_addr : rdwraddr;
+  assign data                     = la_write_en ? la_data : wrdata
              		    		
   fpu_registers csrs             ( .clk             (clk                      ),
                                    .rst_l           (rst_l                    ),
@@ -99,7 +100,7 @@
                                    .fpu_valids      ({valid_out, op_out}      ),
                                    .addr            (addr                     ),
                                    .wren            (wb_valid                 ),
-                                   .wrdata          (wrdata                   ),
+                                   .wrdata          (data                     ),
                                    .exceptions      (exceptions               ),
                                    .rddata          (int_rddata               ),
                                    .opA             (a                        ),