Update user_proj_example.sv

verilog/rtl/user_proj_example.sv

diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index f5dbf40..0d00ab2 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -92,7 +92,7 @@
 
   assign la_write_en              = |la_write;
   assign addr                     = la_write_en ? la_addr : rdwraddr;
-  assign data                     = la_write_en ? la_data : wrdata
+  assign data                     = la_write_en ? la_data : wrdata;
              		    		
   fpu_registers csrs             ( .clk             (clk                      ),
                                    .rst_l           (rst_l                    ),