operation csr logic fix

verilog/rtl/registers.sv

diff --git a/verilog/rtl/registers.sv b/verilog/rtl/registers.sv
index 582db3b..018094e 100644
--- a/verilog/rtl/registers.sv
+++ b/verilog/rtl/registers.sv
@@ -138,8 +138,8 @@
    wire [12:0] op_ns;
 
    assign addr_op = (addr[31:0] == OPERATION);
-   assign wr_op   = addr_op && wren;
-   assign op_ns   = wrdata;
+   assign wr_op   = |op_valids | (addr_op && wren);
+   assign op_ns   = |op_valids ? 13'b0 : wrdata;
 
    rvdffe #(13) op_ff (.clk(clk), .rst_l(rst_l), .en(wr_op), .din(op_ns), .dout(op_valids));