| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/ren_conv_top,ren_conv_top,ren_conv_top,Flow_completed,0h20m22s,0h12m52s,49187.555555555555,0.5625,24593.777777777777,33,836.8,13834,0,0,0,0,0,0,0,42,0,-1,-1,896320,135012,-6.85,-6.85,-0.31,-2.12,-1.3,-336.93,-336.93,-4.11,-4.11,-77.76,628865943,0.0,34.95,34.83,0.62,-1,-1,13810,13906,3985,4081,0,0,0,13834,181,88,125,76,556,449,143,4010,3990,3937,22,534,7530,0,8064,88.49557522123894,11.3,10,AREA 0,5,50,1,153.6,153.18,0.35,0,sky130_fd_sc_hd,4,3 |
