local precheck completed
diff --git a/README.md b/README.md
index 3706438..cddeef1 100644
--- a/README.md
+++ b/README.md
@@ -1,11 +1,21 @@
-# Caravel User Project
+# Bandgap Reference Design
-[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
+Please refer to this git repo for detailed design information[link](https://github.com/vsdip/avsdbgp_3v3_sky130_v1)
-| :exclamation: Important Note |
-|-----------------------------------------|
+A simple bandgap topology is evaluated with a set of simulations and then implemented in open-source EDA tools.
-## Please fill in your project documentation in this README.md file
+# Bandgap Performance Characteristics
+
+| Parameter| Description| Min | Type | Max | Unit | Condition |
+| :---: | :-: | :-: | :-: | :---: | :-: | :-: |
+|Technology| 130 nm CMOS Process |
+|RL|Load resistance at Vbgp terminal | 100|||Mohm|VDD=3.3V, T=27C|
+|Vbgp|Output Reference voltage|1.197642|1.201057|1.212476|V|T=-40 to 140C, VDD=3.3V|
+|Vbgp|Output Reference voltage|1.178285|1.201057|1.211677|V|VDD=2.7V to VDD=3.6V, T=27C|
+|TC_vbgp|Temperature Coefficient of Vbgp||6.8717||ppm/C|T=-40 to 140C, VDD=3.3V|
+|VC_vbgp|Voltage Coefficient of Vbgp||2.7802||%/V|VDD=2.7V to 3.6, T=27C|
+|VDD|Supply Voltage|3.2|3.3|3.6|V|T=-40C to 140C|
+|IDD|Supply Current||3.954||uA|EN=1|
+|IDD|Supply Current||607.836||nA|EN=0|
-Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/gds/.magicrc b/gds/.magicrc
new file mode 100644
index 0000000..67cdbf8
--- /dev/null
+++ b/gds/.magicrc
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+ path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
deleted file mode 100644
index 7ed7685..0000000
--- a/gds/user_proj_example.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
new file mode 100644
index 0000000..03d675d
--- /dev/null
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
deleted file mode 100644
index 5e816f0..0000000
--- a/gds/user_project_wrapper.gds.gz
+++ /dev/null
Binary files differ
diff --git a/info.yaml b/info.yaml
index bdd53ba..d883e52 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,13 +1,13 @@
---
project:
- description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+ description: "A bandgap reference design with sky130"
foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel_project_example.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
+ git_url: "https://github.com/swarup-p/bandgap_caravel.git"
+ organization: "VLSI System Design Corporation"
+ organization_url: "http://vlsisystemdesign.com"
+ owner: "Swarup Pulujkar"
process: "SKY130"
- project_name: "Caravel"
+ project_name: "Bandgap"
project_id: "00000000"
tags:
- "Open MPW"
diff --git a/mag/avoid_lu_nmos.mag b/mag/avoid_lu_nmos.mag
new file mode 100644
index 0000000..f65ec5b
--- /dev/null
+++ b/mag/avoid_lu_nmos.mag
@@ -0,0 +1,25 @@
+magic
+tech sky130A
+timestamp 1621345663
+<< pwell >>
+rect -13 -13 61 61
+<< mvpsubdiff >>
+rect 0 32 48 48
+rect 0 15 15 32
+rect 32 15 48 32
+rect 0 0 48 15
+<< mvpsubdiffcont >>
+rect 15 15 32 32
+<< locali >>
+rect 0 32 48 48
+rect 0 15 15 32
+rect 32 15 48 32
+rect 0 0 48 15
+<< viali >>
+rect 15 15 32 32
+<< metal1 >>
+rect 0 32 48 48
+rect 0 15 15 32
+rect 32 15 48 32
+rect 0 0 48 15
+<< end >>
diff --git a/mag/avoid_lu_pmos.mag b/mag/avoid_lu_pmos.mag
new file mode 100644
index 0000000..588d4c7
--- /dev/null
+++ b/mag/avoid_lu_pmos.mag
@@ -0,0 +1,26 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1621345663
+<< nwell >>
+rect -66 -68 162 162
+<< mvnsubdiff >>
+rect 0 64 96 96
+rect 0 30 31 64
+rect 65 30 96 64
+rect 0 0 96 30
+<< mvnsubdiffcont >>
+rect 31 30 65 64
+<< locali >>
+rect 0 64 96 96
+rect 0 30 31 64
+rect 65 30 96 64
+rect 0 0 96 30
+<< viali >>
+rect 31 30 65 64
+<< metal1 >>
+rect 0 64 96 96
+rect 0 30 31 64
+rect 65 30 96 64
+rect 0 0 96 30
+<< end >>
diff --git a/mag/avsdbgp_3V3.mag b/mag/avsdbgp_3V3.mag
new file mode 100644
index 0000000..d619a83
--- /dev/null
+++ b/mag/avsdbgp_3V3.mag
@@ -0,0 +1,764 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1621849157
+<< nwell >>
+rect 0 14540 7636 14770
+rect 38 12728 344 14540
+rect 2136 13598 6460 14540
+rect 2386 13544 6460 13598
+rect 2136 10390 6460 13544
+<< mvpsubdiff >>
+rect 0 -18 100 16
+rect 134 -18 300 16
+rect 334 -18 500 16
+rect 534 -18 700 16
+rect 734 -18 900 16
+rect 934 -18 1100 16
+rect 1134 -18 1300 16
+rect 1334 -18 1500 16
+rect 1534 -18 1700 16
+rect 1734 -18 1900 16
+rect 1934 -18 2100 16
+rect 2134 -18 2300 16
+rect 2334 -18 2500 16
+rect 2534 -18 2700 16
+rect 2734 -18 2900 16
+rect 2934 -18 3100 16
+rect 3134 -18 3300 16
+rect 3334 -18 3500 16
+rect 3534 -18 3700 16
+rect 3734 -18 3900 16
+rect 3934 -18 4100 16
+rect 4134 -18 4300 16
+rect 4334 -18 4500 16
+rect 4534 -18 4700 16
+rect 4734 -18 4900 16
+rect 4934 -18 5100 16
+rect 5134 -18 5300 16
+rect 5334 -18 5500 16
+rect 5534 -18 5700 16
+rect 5734 -18 5900 16
+rect 5934 -18 6100 16
+rect 6134 -18 6300 16
+rect 6334 -18 6500 16
+rect 6534 -18 6700 16
+rect 6734 -18 6900 16
+rect 6934 -18 7100 16
+rect 7134 -18 7300 16
+rect 7334 -18 7500 16
+rect 7534 -18 7636 16
+<< mvnsubdiff >>
+rect 66 14670 100 14704
+rect 134 14670 300 14704
+rect 334 14670 500 14704
+rect 534 14670 700 14704
+rect 734 14670 900 14704
+rect 934 14670 1100 14704
+rect 1134 14670 1300 14704
+rect 1334 14670 1500 14704
+rect 1534 14670 1700 14704
+rect 1734 14670 1900 14704
+rect 1934 14670 2100 14704
+rect 2134 14670 2300 14704
+rect 2334 14670 2500 14704
+rect 2534 14670 2700 14704
+rect 2734 14670 2900 14704
+rect 2934 14670 3100 14704
+rect 3134 14670 3300 14704
+rect 3334 14670 3500 14704
+rect 3534 14670 3700 14704
+rect 3734 14670 3900 14704
+rect 3934 14670 4100 14704
+rect 4134 14670 4300 14704
+rect 4334 14670 4500 14704
+rect 4534 14670 4700 14704
+rect 4734 14670 4900 14704
+rect 4934 14670 5100 14704
+rect 5134 14670 5300 14704
+rect 5334 14670 5500 14704
+rect 5534 14670 5700 14704
+rect 5734 14670 5900 14704
+rect 5934 14670 6100 14704
+rect 6134 14670 6300 14704
+rect 6334 14670 6500 14704
+rect 6534 14670 6700 14704
+rect 6734 14670 6900 14704
+rect 6934 14670 7100 14704
+rect 7134 14670 7300 14704
+rect 7334 14670 7570 14704
+<< mvpsubdiffcont >>
+rect 100 -18 134 16
+rect 300 -18 334 16
+rect 500 -18 534 16
+rect 700 -18 734 16
+rect 900 -18 934 16
+rect 1100 -18 1134 16
+rect 1300 -18 1334 16
+rect 1500 -18 1534 16
+rect 1700 -18 1734 16
+rect 1900 -18 1934 16
+rect 2100 -18 2134 16
+rect 2300 -18 2334 16
+rect 2500 -18 2534 16
+rect 2700 -18 2734 16
+rect 2900 -18 2934 16
+rect 3100 -18 3134 16
+rect 3300 -18 3334 16
+rect 3500 -18 3534 16
+rect 3700 -18 3734 16
+rect 3900 -18 3934 16
+rect 4100 -18 4134 16
+rect 4300 -18 4334 16
+rect 4500 -18 4534 16
+rect 4700 -18 4734 16
+rect 4900 -18 4934 16
+rect 5100 -18 5134 16
+rect 5300 -18 5334 16
+rect 5500 -18 5534 16
+rect 5700 -18 5734 16
+rect 5900 -18 5934 16
+rect 6100 -18 6134 16
+rect 6300 -18 6334 16
+rect 6500 -18 6534 16
+rect 6700 -18 6734 16
+rect 6900 -18 6934 16
+rect 7100 -18 7134 16
+rect 7300 -18 7334 16
+rect 7500 -18 7534 16
+<< mvnsubdiffcont >>
+rect 100 14670 134 14704
+rect 300 14670 334 14704
+rect 500 14670 534 14704
+rect 700 14670 734 14704
+rect 900 14670 934 14704
+rect 1100 14670 1134 14704
+rect 1300 14670 1334 14704
+rect 1500 14670 1534 14704
+rect 1700 14670 1734 14704
+rect 1900 14670 1934 14704
+rect 2100 14670 2134 14704
+rect 2300 14670 2334 14704
+rect 2500 14670 2534 14704
+rect 2700 14670 2734 14704
+rect 2900 14670 2934 14704
+rect 3100 14670 3134 14704
+rect 3300 14670 3334 14704
+rect 3500 14670 3534 14704
+rect 3700 14670 3734 14704
+rect 3900 14670 3934 14704
+rect 4100 14670 4134 14704
+rect 4300 14670 4334 14704
+rect 4500 14670 4534 14704
+rect 4700 14670 4734 14704
+rect 4900 14670 4934 14704
+rect 5100 14670 5134 14704
+rect 5300 14670 5334 14704
+rect 5500 14670 5534 14704
+rect 5700 14670 5734 14704
+rect 5900 14670 5934 14704
+rect 6100 14670 6134 14704
+rect 6300 14670 6334 14704
+rect 6500 14670 6534 14704
+rect 6700 14670 6734 14704
+rect 6900 14670 6934 14704
+rect 7100 14670 7134 14704
+rect 7300 14670 7334 14704
+<< poly >>
+rect 3272 13944 3798 14510
+rect 3272 13910 3504 13944
+rect 3554 13910 3798 13944
+rect 3272 13570 3798 13910
+rect 3272 13520 3746 13570
+rect 3780 13520 3798 13570
+rect 3272 13510 3798 13520
+rect 4798 13510 5324 14510
+rect 3272 9614 3798 10180
+rect 3272 9580 3496 9614
+rect 3546 9580 3798 9614
+rect 3272 9180 3798 9580
+rect 3272 4880 3798 5880
+rect 4798 4880 5324 5880
+<< polycont >>
+rect 3504 13910 3554 13944
+rect 3746 13520 3780 13570
+rect 1702 10408 1770 10442
+rect 3496 9580 3546 9614
+rect 2292 9294 2342 9328
+rect 1128 9018 1328 9052
+rect 6236 5344 6286 5378
+rect 290 642 324 692
+<< xpolycontact >>
+rect 6960 10914 7030 11346
+rect 6642 4562 6712 4994
+rect 6642 2380 6712 2812
+rect 6960 2380 7030 2812
+rect 7278 10914 7348 11346
+rect 7278 2380 7348 2812
+<< xpolyres >>
+rect 6642 2812 6712 4562
+rect 6960 2812 7030 10914
+rect 7278 2812 7348 10914
+<< locali >>
+rect 0 14670 100 14704
+rect 134 14670 300 14704
+rect 334 14670 500 14704
+rect 534 14670 700 14704
+rect 734 14670 900 14704
+rect 934 14670 1100 14704
+rect 1134 14670 1300 14704
+rect 1334 14670 1500 14704
+rect 1534 14670 1700 14704
+rect 1734 14670 1900 14704
+rect 1934 14670 2100 14704
+rect 2134 14670 2300 14704
+rect 2334 14670 2500 14704
+rect 2534 14670 2700 14704
+rect 2734 14670 2900 14704
+rect 2934 14670 3100 14704
+rect 3134 14670 3300 14704
+rect 3334 14670 3500 14704
+rect 3534 14670 3700 14704
+rect 3734 14670 3900 14704
+rect 3934 14670 4100 14704
+rect 4134 14670 4300 14704
+rect 4334 14670 4500 14704
+rect 4534 14670 4700 14704
+rect 4734 14670 4900 14704
+rect 4934 14670 5100 14704
+rect 5134 14670 5300 14704
+rect 5334 14670 5500 14704
+rect 5534 14670 5700 14704
+rect 5734 14670 5900 14704
+rect 5934 14670 6100 14704
+rect 6134 14670 6300 14704
+rect 6334 14670 6500 14704
+rect 6534 14670 6700 14704
+rect 6734 14670 6900 14704
+rect 6934 14670 7100 14704
+rect 7134 14670 7300 14704
+rect 7334 14670 7500 14704
+rect 7534 14670 7636 14704
+rect 174 12648 208 14670
+rect 1584 13910 3144 13944
+rect 3194 13910 3210 13944
+rect 1584 11092 1618 13910
+rect 3290 13460 3324 14670
+rect 3380 13910 3396 13944
+rect 3446 13910 3504 13944
+rect 3554 13910 3578 13944
+rect 3746 13570 3780 13586
+rect 3746 13460 3780 13520
+rect 4816 13460 4850 14670
+rect 6342 13460 6376 14670
+rect 6958 11346 7032 11348
+rect 6958 10914 6960 11346
+rect 7030 11144 7032 11346
+rect 7276 11346 7350 11348
+rect 7276 11144 7278 11346
+rect 7030 11110 7278 11144
+rect 7030 10914 7032 11110
+rect 6958 10912 7032 10914
+rect 7276 10914 7278 11110
+rect 7348 10914 7350 11346
+rect 7276 10912 7350 10914
+rect 1854 10444 1888 10492
+rect 412 10408 1702 10442
+rect 1770 10408 1786 10442
+rect 1854 10410 2034 10444
+rect 290 692 324 708
+rect 174 494 208 544
+rect 290 494 324 642
+rect 412 494 446 10408
+rect 2000 9914 2034 10410
+rect 2220 10436 2254 10460
+rect 2220 10380 2254 10386
+rect 3746 10436 3780 10460
+rect 3746 10380 3780 10386
+rect 5272 10436 5306 10460
+rect 5272 10380 5306 10386
+rect 2000 9852 2034 9864
+rect 1216 9580 3496 9614
+rect 3546 9580 3562 9614
+rect 1216 9052 1250 9580
+rect 2220 9294 2292 9328
+rect 2342 9294 2358 9328
+rect 2000 9250 2034 9258
+rect 1112 9018 1128 9052
+rect 1328 9018 1344 9052
+rect 584 494 618 562
+rect 174 460 618 494
+rect 1854 494 1888 562
+rect 2000 494 2034 9200
+rect 2220 9202 2254 9294
+rect 2220 9130 2254 9152
+rect 3746 9202 3780 9290
+rect 3746 9130 3780 9152
+rect 3290 6106 3324 6130
+rect 3290 6050 3324 6056
+rect 4816 6106 4850 6130
+rect 4816 6050 4850 6056
+rect 6220 5344 6236 5378
+rect 6286 5344 6324 5378
+rect 3746 4996 6714 5030
+rect 3290 4904 3324 4910
+rect 3290 4830 3324 4854
+rect 3746 4830 3780 4996
+rect 6640 4994 6714 4996
+rect 4816 4904 4850 4910
+rect 4816 4830 4850 4854
+rect 5272 4904 5306 4910
+rect 5272 4830 5306 4854
+rect 6640 4562 6642 4994
+rect 6712 4562 6714 4994
+rect 6640 4560 6714 4562
+rect 6640 2812 6714 2814
+rect 2220 2406 2254 2430
+rect 2220 2350 2254 2356
+rect 6342 2362 6376 2430
+rect 6342 2300 6376 2312
+rect 6640 2380 6642 2812
+rect 6712 2380 6714 2812
+rect 6640 2272 6714 2380
+rect 6958 2812 7032 2814
+rect 6958 2380 6960 2812
+rect 7030 2380 7032 2812
+rect 6958 2362 7032 2380
+rect 6958 2312 6978 2362
+rect 7012 2312 7032 2362
+rect 6958 2300 7032 2312
+rect 7276 2812 7350 2814
+rect 7276 2380 7278 2812
+rect 7348 2380 7350 2812
+rect 7276 2360 7350 2380
+rect 7276 2310 7296 2360
+rect 7330 2310 7350 2360
+rect 7276 2300 7350 2310
+rect 6640 2222 6660 2272
+rect 6694 2222 6714 2272
+rect 6640 2212 6714 2222
+rect 2538 1376 2610 1440
+rect 3336 1376 3408 1440
+rect 4134 1376 4206 1440
+rect 4932 1376 5004 1440
+rect 5730 1376 5802 1440
+rect 2202 1260 6138 1276
+rect 2202 1226 6286 1260
+rect 2202 1204 6138 1226
+rect 2538 560 2610 624
+rect 3336 560 3408 624
+rect 4134 560 4206 624
+rect 4932 560 5004 624
+rect 5730 560 5802 624
+rect 1854 460 2034 494
+rect 2000 16 2034 460
+rect 6252 16 6286 1226
+rect 0 -18 100 16
+rect 134 -18 300 16
+rect 334 -18 500 16
+rect 534 -18 700 16
+rect 734 -18 900 16
+rect 934 -18 1100 16
+rect 1134 -18 1300 16
+rect 1334 -18 1500 16
+rect 1534 -18 1700 16
+rect 1734 -18 1900 16
+rect 1934 -18 2100 16
+rect 2134 -18 2300 16
+rect 2334 -18 2500 16
+rect 2534 -18 2700 16
+rect 2734 -18 2900 16
+rect 2934 -18 3100 16
+rect 3134 -18 3300 16
+rect 3334 -18 3500 16
+rect 3534 -18 3700 16
+rect 3734 -18 3900 16
+rect 3934 -18 4100 16
+rect 4134 -18 4300 16
+rect 4334 -18 4500 16
+rect 4534 -18 4700 16
+rect 4734 -18 4900 16
+rect 4934 -18 5100 16
+rect 5134 -18 5300 16
+rect 5334 -18 5500 16
+rect 5534 -18 5700 16
+rect 5734 -18 5900 16
+rect 5934 -18 6100 16
+rect 6134 -18 6300 16
+rect 6334 -18 6500 16
+rect 6534 -18 6700 16
+rect 6734 -18 6900 16
+rect 6934 -18 7100 16
+rect 7134 -18 7300 16
+rect 7334 -18 7500 16
+rect 7534 -18 7636 16
+<< viali >>
+rect 100 14670 134 14704
+rect 300 14670 334 14704
+rect 500 14670 534 14704
+rect 700 14670 734 14704
+rect 900 14670 934 14704
+rect 1100 14670 1134 14704
+rect 1300 14670 1334 14704
+rect 1500 14670 1534 14704
+rect 1700 14670 1734 14704
+rect 1900 14670 1934 14704
+rect 2100 14670 2134 14704
+rect 2300 14670 2334 14704
+rect 2500 14670 2534 14704
+rect 2700 14670 2734 14704
+rect 2900 14670 2934 14704
+rect 3100 14670 3134 14704
+rect 3300 14670 3334 14704
+rect 3500 14670 3534 14704
+rect 3700 14670 3734 14704
+rect 3900 14670 3934 14704
+rect 4100 14670 4134 14704
+rect 4300 14670 4334 14704
+rect 4500 14670 4534 14704
+rect 4700 14670 4734 14704
+rect 4900 14670 4934 14704
+rect 5100 14670 5134 14704
+rect 5300 14670 5334 14704
+rect 5500 14670 5534 14704
+rect 5700 14670 5734 14704
+rect 5900 14670 5934 14704
+rect 6100 14670 6134 14704
+rect 6300 14670 6334 14704
+rect 6500 14670 6534 14704
+rect 6700 14670 6734 14704
+rect 6900 14670 6934 14704
+rect 7100 14670 7134 14704
+rect 7300 14670 7334 14704
+rect 7500 14670 7534 14704
+rect 3144 13910 3194 13944
+rect 3396 13910 3446 13944
+rect 2220 10386 2254 10436
+rect 3746 10386 3780 10436
+rect 5272 10386 5306 10436
+rect 2000 9864 2034 9914
+rect 2000 9200 2034 9250
+rect 2220 9152 2254 9202
+rect 3746 9152 3780 9202
+rect 3290 6056 3324 6106
+rect 4816 6056 4850 6106
+rect 3290 4854 3324 4904
+rect 4816 4854 4850 4904
+rect 5272 4854 5306 4904
+rect 2220 2356 2254 2406
+rect 6342 2312 6376 2362
+rect 6978 2312 7012 2362
+rect 7296 2310 7330 2360
+rect 6660 2222 6694 2272
+rect 100 -18 134 16
+rect 300 -18 334 16
+rect 500 -18 534 16
+rect 700 -18 734 16
+rect 900 -18 934 16
+rect 1100 -18 1134 16
+rect 1300 -18 1334 16
+rect 1500 -18 1534 16
+rect 1700 -18 1734 16
+rect 1900 -18 1934 16
+rect 2100 -18 2134 16
+rect 2300 -18 2334 16
+rect 2500 -18 2534 16
+rect 2700 -18 2734 16
+rect 2900 -18 2934 16
+rect 3100 -18 3134 16
+rect 3300 -18 3334 16
+rect 3500 -18 3534 16
+rect 3700 -18 3734 16
+rect 3900 -18 3934 16
+rect 4100 -18 4134 16
+rect 4300 -18 4334 16
+rect 4500 -18 4534 16
+rect 4700 -18 4734 16
+rect 4900 -18 4934 16
+rect 5100 -18 5134 16
+rect 5300 -18 5334 16
+rect 5500 -18 5534 16
+rect 5700 -18 5734 16
+rect 5900 -18 5934 16
+rect 6100 -18 6134 16
+rect 6300 -18 6334 16
+rect 6500 -18 6534 16
+rect 6700 -18 6734 16
+rect 6900 -18 6934 16
+rect 7100 -18 7134 16
+rect 7300 -18 7334 16
+rect 7500 -18 7534 16
+<< metal1 >>
+rect 0 14704 7636 14736
+rect 0 14670 100 14704
+rect 134 14670 300 14704
+rect 334 14670 500 14704
+rect 534 14670 700 14704
+rect 734 14670 900 14704
+rect 934 14670 1100 14704
+rect 1134 14670 1300 14704
+rect 1334 14670 1500 14704
+rect 1534 14670 1700 14704
+rect 1734 14670 1900 14704
+rect 1934 14670 2100 14704
+rect 2134 14670 2300 14704
+rect 2334 14670 2500 14704
+rect 2534 14670 2700 14704
+rect 2734 14670 2900 14704
+rect 2934 14670 3100 14704
+rect 3134 14670 3300 14704
+rect 3334 14670 3500 14704
+rect 3534 14670 3700 14704
+rect 3734 14670 3900 14704
+rect 3934 14670 4100 14704
+rect 4134 14670 4300 14704
+rect 4334 14670 4500 14704
+rect 4534 14670 4700 14704
+rect 4734 14670 4900 14704
+rect 4934 14670 5100 14704
+rect 5134 14670 5300 14704
+rect 5334 14670 5500 14704
+rect 5534 14670 5700 14704
+rect 5734 14670 5900 14704
+rect 5934 14670 6100 14704
+rect 6134 14670 6300 14704
+rect 6334 14670 6500 14704
+rect 6534 14670 6700 14704
+rect 6734 14670 6900 14704
+rect 6934 14670 7100 14704
+rect 7134 14670 7300 14704
+rect 7334 14670 7500 14704
+rect 7534 14670 7636 14704
+rect 0 14640 7636 14670
+rect 3100 13944 3458 13958
+rect 3100 13910 3144 13944
+rect 3194 13910 3396 13944
+rect 3446 13910 3458 13944
+rect 3100 13898 3458 13910
+rect 2206 10436 2266 10450
+rect 2206 10386 2220 10436
+rect 2254 10386 2266 10436
+rect 1988 9914 2048 9928
+rect 1988 9864 2000 9914
+rect 2034 9864 2048 9914
+rect 1988 9250 2048 9864
+rect 1988 9200 2000 9250
+rect 2034 9200 2048 9250
+rect 1988 9186 2048 9200
+rect 2206 9202 2266 10386
+rect 2206 9152 2220 9202
+rect 2254 9152 2266 9202
+rect 2206 9140 2266 9152
+rect 3732 10436 3792 10450
+rect 3732 10386 3746 10436
+rect 3780 10386 3792 10436
+rect 3732 9202 3792 10386
+rect 3732 9152 3746 9202
+rect 3780 9152 3792 9202
+rect 3732 9140 3792 9152
+rect 5258 10436 5318 10450
+rect 5258 10386 5272 10436
+rect 5306 10386 5318 10436
+rect 3278 6106 3338 6120
+rect 3278 6056 3290 6106
+rect 3324 6056 3338 6106
+rect 3278 4904 3338 6056
+rect 3278 4854 3290 4904
+rect 3324 4854 3338 4904
+rect 3278 4840 3338 4854
+rect 4804 6106 4864 6120
+rect 4804 6056 4816 6106
+rect 4850 6056 4864 6106
+rect 4804 4904 4864 6056
+rect 4804 4854 4816 4904
+rect 4850 4854 4864 4904
+rect 4804 4840 4864 4854
+rect 5258 4904 5318 10386
+rect 5258 4854 5272 4904
+rect 5306 4854 5318 4904
+rect 5258 4840 5318 4854
+rect 2206 2406 2266 2420
+rect 2206 2356 2220 2406
+rect 2254 2356 2266 2406
+rect 2206 2226 2266 2356
+rect 6330 2362 7024 2368
+rect 6330 2312 6342 2362
+rect 6376 2312 6978 2362
+rect 7012 2312 7024 2362
+rect 6330 2306 7024 2312
+rect 7282 2360 7342 2372
+rect 7282 2310 7296 2360
+rect 7330 2310 7342 2360
+rect 4140 2272 6714 2278
+rect 2206 2166 2604 2226
+rect 2544 1730 2604 2166
+rect 4140 2222 6660 2272
+rect 6694 2222 6714 2272
+rect 4140 2216 6714 2222
+rect 4140 2130 4200 2216
+rect 2916 2070 5796 2130
+rect 2916 862 2976 2070
+rect 3342 1730 3402 2070
+rect 3714 862 3774 2070
+rect 4140 1730 4200 2070
+rect 4512 862 4572 2070
+rect 4938 1730 4998 2070
+rect 5310 862 5370 2070
+rect 5736 1730 5796 2070
+rect 7282 862 7342 2310
+rect 2656 802 2976 862
+rect 3454 802 3774 862
+rect 4252 802 4572 862
+rect 5050 802 5370 862
+rect 5848 802 7342 862
+rect 0 16 7636 48
+rect 0 -18 100 16
+rect 134 -18 300 16
+rect 334 -18 500 16
+rect 534 -18 700 16
+rect 734 -18 900 16
+rect 934 -18 1100 16
+rect 1134 -18 1300 16
+rect 1334 -18 1500 16
+rect 1534 -18 1700 16
+rect 1734 -18 1900 16
+rect 1934 -18 2100 16
+rect 2134 -18 2300 16
+rect 2334 -18 2500 16
+rect 2534 -18 2700 16
+rect 2734 -18 2900 16
+rect 2934 -18 3100 16
+rect 3134 -18 3300 16
+rect 3334 -18 3500 16
+rect 3534 -18 3700 16
+rect 3734 -18 3900 16
+rect 3934 -18 4100 16
+rect 4134 -18 4300 16
+rect 4334 -18 4500 16
+rect 4534 -18 4700 16
+rect 4734 -18 4900 16
+rect 4934 -18 5100 16
+rect 5134 -18 5300 16
+rect 5334 -18 5500 16
+rect 5534 -18 5700 16
+rect 5734 -18 5900 16
+rect 5934 -18 6100 16
+rect 6134 -18 6300 16
+rect 6334 -18 6500 16
+rect 6534 -18 6700 16
+rect 6734 -18 6900 16
+rect 6934 -18 7100 16
+rect 7134 -18 7300 16
+rect 7334 -18 7500 16
+rect 7534 -18 7636 16
+rect 0 -48 7636 -18
+use sc_pmos sc_pmos_0
+timestamp 1616540248
+transform 1 0 -360 0 1 -2468
+box 400 2928 700 15200
+use sc_nmos_426 sc_nmos_426_0
+timestamp 1616700505
+transform 1 0 186 0 1 -640
+box 380 1100 1720 9704
+use sc_nmos_31 sc_nmos_31_0
+timestamp 1616174596
+transform 1 0 1186 0 1 9290
+box 380 1100 720 1904
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_0
+timestamp 1615375237
+transform 1 0 2176 0 1 1250
+box 26 26 770 795
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_2
+timestamp 1615375237
+transform 1 0 2176 0 1 434
+box 26 26 770 795
+use cm_nmos cm_nmos_1
+timestamp 1616067151
+transform 1 0 2272 0 1 6080
+box -70 0 1070 4100
+use en_nmos en_nmos_0
+timestamp 1616065709
+transform 1 0 2272 0 1 2380
+box -70 0 1070 3500
+use cm_pmos cm_pmos_0
+timestamp 1616078161
+transform 1 0 2272 0 1 10410
+box -136 -20 1136 4100
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_1
+timestamp 1615375237
+transform 1 0 2974 0 1 1250
+box 26 26 770 795
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_3
+timestamp 1615375237
+transform 1 0 2974 0 1 434
+box 26 26 770 795
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_6
+timestamp 1615375237
+transform 1 0 3772 0 1 1250
+box 26 26 770 795
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_5
+timestamp 1615375237
+transform 1 0 3772 0 1 434
+box 26 26 770 795
+use en_nmos en_nmos_1
+timestamp 1616065709
+transform 1 0 3798 0 1 2380
+box -70 0 1070 3500
+use cm_nmos cm_nmos_0
+timestamp 1616067151
+transform 1 0 3798 0 1 6080
+box -70 0 1070 4100
+use cm_pmos cm_pmos_1
+timestamp 1616078161
+transform 1 0 3798 0 1 10410
+box -136 -20 1136 4100
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_7
+timestamp 1615375237
+transform 1 0 4570 0 1 1250
+box 26 26 770 795
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_4
+timestamp 1615375237
+transform 1 0 4570 0 1 434
+box 26 26 770 795
+use en_nmos en_nmos_2
+timestamp 1616065709
+transform 1 0 5324 0 1 2380
+box -70 0 1070 3500
+use cm_pmos cm_pmos_2
+timestamp 1616078161
+transform 1 0 5324 0 1 10410
+box -136 -20 1136 4100
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_8
+timestamp 1615375237
+transform 1 0 5368 0 1 1250
+box 26 26 770 795
+use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_9
+timestamp 1615375237
+transform 1 0 5368 0 1 434
+box 26 26 770 795
+<< labels >>
+flabel metal1 s 6496 2226 6496 2226 0 FreeSans 400 0 0 0 A
+flabel locali s 6500 5002 6500 5002 0 FreeSans 400 0 0 0 B
+flabel metal1 s 4816 5982 4816 5982 0 FreeSans 400 0 0 0 C
+flabel metal1 s 3768 10296 3768 10296 0 FreeSans 400 0 0 0 D
+flabel metal1 s 5294 10280 5294 10280 0 FreeSans 400 0 0 0 E
+flabel metal1 s 2246 2316 2246 2316 0 FreeSans 400 0 0 0 F
+flabel metal1 s 3304 6000 3304 6000 0 FreeSans 400 0 0 0 G
+flabel locali s 7134 11126 7134 11126 0 FreeSans 400 0 0 0 H
+flabel metal1 s 7302 2132 7302 2132 0 FreeSans 400 0 0 0 J
+flabel locali s 416 464 416 464 0 FreeSans 800 0 0 0 I
+flabel locali s 1312 9596 1312 9596 0 FreeSans 800 0 0 0 VbiasN
+flabel locali s 1628 13930 1628 13930 0 FreeSans 800 0 0 0 VbiasP
+flabel locali s 404 14692 404 14692 0 FreeSans 320 0 0 0 VDD
+port 0 nsew power bidirectional
+flabel locali s 400 2 400 2 0 FreeSans 320 0 0 0 GND
+port 1 nsew ground bidirectional
+flabel locali s 7028 2336 7028 2336 0 FreeSans 320 0 0 0 Vbgp
+port 2 nsew signal output
+flabel locali s 6304 5360 6304 5360 0 FreeSans 320 0 0 0 en
+port 3 nsew signal input
+<< properties >>
+string LEFsite unithd
+string LEFclass CORE
+string FIXED_BBOX 0 0 7636 14736
+<< end >>
diff --git a/mag/cm_nmos.mag b/mag/cm_nmos.mag
new file mode 100644
index 0000000..95d7bdd
--- /dev/null
+++ b/mag/cm_nmos.mag
@@ -0,0 +1,136 @@
+magic
+tech sky130A
+timestamp 1616067151
+<< mvnmos >>
+rect 0 25 500 1525
+<< mvndiff >>
+rect -35 1485 0 1525
+rect -35 1385 -26 1485
+rect -9 1385 0 1485
+rect -35 1365 0 1385
+rect -35 1265 -26 1365
+rect -9 1265 0 1365
+rect -35 1245 0 1265
+rect -35 1145 -26 1245
+rect -9 1145 0 1245
+rect -35 1125 0 1145
+rect -35 1025 -26 1125
+rect -9 1025 0 1125
+rect -35 1005 0 1025
+rect -35 905 -26 1005
+rect -9 905 0 1005
+rect -35 885 0 905
+rect -35 785 -26 885
+rect -9 785 0 885
+rect -35 765 0 785
+rect -35 665 -26 765
+rect -9 665 0 765
+rect -35 645 0 665
+rect -35 545 -26 645
+rect -9 545 0 645
+rect -35 525 0 545
+rect -35 425 -26 525
+rect -9 425 0 525
+rect -35 405 0 425
+rect -35 305 -26 405
+rect -9 305 0 405
+rect -35 285 0 305
+rect -35 185 -26 285
+rect -9 185 0 285
+rect -35 165 0 185
+rect -35 65 -26 165
+rect -9 65 0 165
+rect -35 25 0 65
+rect 500 1485 535 1525
+rect 500 1385 509 1485
+rect 526 1385 535 1485
+rect 500 1365 535 1385
+rect 500 1265 509 1365
+rect 526 1265 535 1365
+rect 500 1245 535 1265
+rect 500 1145 509 1245
+rect 526 1145 535 1245
+rect 500 1125 535 1145
+rect 500 1025 509 1125
+rect 526 1025 535 1125
+rect 500 1005 535 1025
+rect 500 905 509 1005
+rect 526 905 535 1005
+rect 500 885 535 905
+rect 500 785 509 885
+rect 526 785 535 885
+rect 500 765 535 785
+rect 500 665 509 765
+rect 526 665 535 765
+rect 500 645 535 665
+rect 500 545 509 645
+rect 526 545 535 645
+rect 500 525 535 545
+rect 500 425 509 525
+rect 526 425 535 525
+rect 500 405 535 425
+rect 500 305 509 405
+rect 526 305 535 405
+rect 500 285 535 305
+rect 500 185 509 285
+rect 526 185 535 285
+rect 500 165 535 185
+rect 500 65 509 165
+rect 526 65 535 165
+rect 500 25 535 65
+<< mvndiffc >>
+rect -26 1385 -9 1485
+rect -26 1265 -9 1365
+rect -26 1145 -9 1245
+rect -26 1025 -9 1125
+rect -26 905 -9 1005
+rect -26 785 -9 885
+rect -26 665 -9 765
+rect -26 545 -9 645
+rect -26 425 -9 525
+rect -26 305 -9 405
+rect -26 185 -9 285
+rect -26 65 -9 165
+rect 509 1385 526 1485
+rect 509 1265 526 1365
+rect 509 1145 526 1245
+rect 509 1025 526 1125
+rect 509 905 526 1005
+rect 509 785 526 885
+rect 509 665 526 765
+rect 509 545 526 645
+rect 509 425 526 525
+rect 509 305 526 405
+rect 509 185 526 285
+rect 509 65 526 165
+<< poly >>
+rect 0 1525 500 2050
+rect 0 0 500 25
+<< locali >>
+rect -26 1485 -9 1525
+rect -26 1365 -9 1385
+rect -26 1245 -9 1265
+rect -26 1125 -9 1145
+rect -26 1005 -9 1025
+rect -26 885 -9 905
+rect -26 765 -9 785
+rect -26 645 -9 665
+rect -26 525 -9 545
+rect -26 405 -9 425
+rect -26 285 -9 305
+rect -26 165 -9 185
+rect -26 25 -9 65
+rect 509 1485 526 1525
+rect 509 1365 526 1385
+rect 509 1245 526 1265
+rect 509 1125 526 1145
+rect 509 1005 526 1025
+rect 509 885 526 905
+rect 509 765 526 785
+rect 509 645 526 665
+rect 509 525 526 545
+rect 509 405 526 425
+rect 509 285 526 305
+rect 509 165 526 185
+rect 509 25 526 65
+<< end >>
diff --git a/mag/cm_pmos.mag b/mag/cm_pmos.mag
new file mode 100644
index 0000000..060b8c5
--- /dev/null
+++ b/mag/cm_pmos.mag
@@ -0,0 +1,138 @@
+magic
+tech sky130A
+timestamp 1616078161
+<< nwell >>
+rect -68 -10 568 2050
+<< mvpmos >>
+rect 0 25 500 1525
+<< mvpdiff >>
+rect -35 1485 0 1525
+rect -35 1385 -26 1485
+rect -9 1385 0 1485
+rect -35 1365 0 1385
+rect -35 1265 -26 1365
+rect -9 1265 0 1365
+rect -35 1245 0 1265
+rect -35 1145 -26 1245
+rect -9 1145 0 1245
+rect -35 1125 0 1145
+rect -35 1025 -26 1125
+rect -9 1025 0 1125
+rect -35 1005 0 1025
+rect -35 905 -26 1005
+rect -9 905 0 1005
+rect -35 885 0 905
+rect -35 785 -26 885
+rect -9 785 0 885
+rect -35 765 0 785
+rect -35 665 -26 765
+rect -9 665 0 765
+rect -35 645 0 665
+rect -35 545 -26 645
+rect -9 545 0 645
+rect -35 525 0 545
+rect -35 425 -26 525
+rect -9 425 0 525
+rect -35 405 0 425
+rect -35 305 -26 405
+rect -9 305 0 405
+rect -35 285 0 305
+rect -35 185 -26 285
+rect -9 185 0 285
+rect -35 165 0 185
+rect -35 65 -26 165
+rect -9 65 0 165
+rect -35 25 0 65
+rect 500 1485 535 1525
+rect 500 1385 509 1485
+rect 526 1385 535 1485
+rect 500 1365 535 1385
+rect 500 1265 509 1365
+rect 526 1265 535 1365
+rect 500 1245 535 1265
+rect 500 1145 509 1245
+rect 526 1145 535 1245
+rect 500 1125 535 1145
+rect 500 1025 509 1125
+rect 526 1025 535 1125
+rect 500 1005 535 1025
+rect 500 905 509 1005
+rect 526 905 535 1005
+rect 500 885 535 905
+rect 500 785 509 885
+rect 526 785 535 885
+rect 500 765 535 785
+rect 500 665 509 765
+rect 526 665 535 765
+rect 500 645 535 665
+rect 500 545 509 645
+rect 526 545 535 645
+rect 500 525 535 545
+rect 500 425 509 525
+rect 526 425 535 525
+rect 500 405 535 425
+rect 500 305 509 405
+rect 526 305 535 405
+rect 500 285 535 305
+rect 500 185 509 285
+rect 526 185 535 285
+rect 500 165 535 185
+rect 500 65 509 165
+rect 526 65 535 165
+rect 500 25 535 65
+<< mvpdiffc >>
+rect -26 1385 -9 1485
+rect -26 1265 -9 1365
+rect -26 1145 -9 1245
+rect -26 1025 -9 1125
+rect -26 905 -9 1005
+rect -26 785 -9 885
+rect -26 665 -9 765
+rect -26 545 -9 645
+rect -26 425 -9 525
+rect -26 305 -9 405
+rect -26 185 -9 285
+rect -26 65 -9 165
+rect 509 1385 526 1485
+rect 509 1265 526 1365
+rect 509 1145 526 1245
+rect 509 1025 526 1125
+rect 509 905 526 1005
+rect 509 785 526 885
+rect 509 665 526 765
+rect 509 545 526 645
+rect 509 425 526 525
+rect 509 305 526 405
+rect 509 185 526 285
+rect 509 65 526 165
+<< poly >>
+rect 0 1525 500 2050
+rect 0 0 500 25
+<< locali >>
+rect -26 1485 -9 1525
+rect -26 1365 -9 1385
+rect -26 1245 -9 1265
+rect -26 1125 -9 1145
+rect -26 1005 -9 1025
+rect -26 885 -9 905
+rect -26 765 -9 785
+rect -26 645 -9 665
+rect -26 525 -9 545
+rect -26 405 -9 425
+rect -26 285 -9 305
+rect -26 165 -9 185
+rect -26 25 -9 65
+rect 509 1485 526 1525
+rect 509 1365 526 1385
+rect 509 1245 526 1265
+rect 509 1125 526 1145
+rect 509 1005 526 1025
+rect 509 885 526 905
+rect 509 765 526 785
+rect 509 645 526 665
+rect 509 525 526 545
+rect 509 405 526 425
+rect 509 285 526 305
+rect 509 165 526 185
+rect 509 25 526 65
+<< end >>
diff --git a/mag/en_nmos.mag b/mag/en_nmos.mag
new file mode 100644
index 0000000..62c9ff2
--- /dev/null
+++ b/mag/en_nmos.mag
@@ -0,0 +1,116 @@
+magic
+tech sky130A
+timestamp 1616065709
+<< mvnmos >>
+rect 0 25 500 1225
+<< mvndiff >>
+rect -35 1215 0 1225
+rect -35 1115 -26 1215
+rect -9 1115 0 1215
+rect -35 1095 0 1115
+rect -35 995 -26 1095
+rect -9 995 0 1095
+rect -35 975 0 995
+rect -35 875 -26 975
+rect -9 875 0 975
+rect -35 855 0 875
+rect -35 755 -26 855
+rect -9 755 0 855
+rect -35 735 0 755
+rect -35 635 -26 735
+rect -9 635 0 735
+rect -35 615 0 635
+rect -35 515 -26 615
+rect -9 515 0 615
+rect -35 495 0 515
+rect -35 395 -26 495
+rect -9 395 0 495
+rect -35 375 0 395
+rect -35 275 -26 375
+rect -9 275 0 375
+rect -35 255 0 275
+rect -35 155 -26 255
+rect -9 155 0 255
+rect -35 135 0 155
+rect -35 35 -26 135
+rect -9 35 0 135
+rect -35 25 0 35
+rect 500 1215 535 1225
+rect 500 1115 509 1215
+rect 526 1115 535 1215
+rect 500 1095 535 1115
+rect 500 995 509 1095
+rect 526 995 535 1095
+rect 500 975 535 995
+rect 500 875 509 975
+rect 526 875 535 975
+rect 500 855 535 875
+rect 500 755 509 855
+rect 526 755 535 855
+rect 500 735 535 755
+rect 500 635 509 735
+rect 526 635 535 735
+rect 500 615 535 635
+rect 500 515 509 615
+rect 526 515 535 615
+rect 500 495 535 515
+rect 500 395 509 495
+rect 526 395 535 495
+rect 500 375 535 395
+rect 500 275 509 375
+rect 526 275 535 375
+rect 500 255 535 275
+rect 500 155 509 255
+rect 526 155 535 255
+rect 500 135 535 155
+rect 500 35 509 135
+rect 526 35 535 135
+rect 500 25 535 35
+<< mvndiffc >>
+rect -26 1115 -9 1215
+rect -26 995 -9 1095
+rect -26 875 -9 975
+rect -26 755 -9 855
+rect -26 635 -9 735
+rect -26 515 -9 615
+rect -26 395 -9 495
+rect -26 275 -9 375
+rect -26 155 -9 255
+rect -26 35 -9 135
+rect 509 1115 526 1215
+rect 509 995 526 1095
+rect 509 875 526 975
+rect 509 755 526 855
+rect 509 635 526 735
+rect 509 515 526 615
+rect 509 395 526 495
+rect 509 275 526 375
+rect 509 155 526 255
+rect 509 35 526 135
+<< poly >>
+rect 0 1225 500 1750
+rect 0 0 500 25
+<< locali >>
+rect -26 1215 -9 1225
+rect -26 1095 -9 1115
+rect -26 975 -9 995
+rect -26 855 -9 875
+rect -26 735 -9 755
+rect -26 615 -9 635
+rect -26 495 -9 515
+rect -26 375 -9 395
+rect -26 255 -9 275
+rect -26 135 -9 155
+rect -26 25 -9 35
+rect 509 1215 526 1225
+rect 509 1095 526 1115
+rect 509 975 526 995
+rect 509 855 526 875
+rect 509 735 526 755
+rect 509 615 526 635
+rect 509 495 526 515
+rect 509 375 526 395
+rect 509 255 526 275
+rect 509 135 526 155
+rect 509 25 526 35
+<< end >>
diff --git a/mag/sc_nmos_31.mag b/mag/sc_nmos_31.mag
new file mode 100644
index 0000000..8cb10f1
--- /dev/null
+++ b/mag/sc_nmos_31.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+timestamp 1616174596
+<< mvnmos >>
+rect 225 601 325 901
+<< mvndiff >>
+rect 190 892 225 901
+rect 190 801 199 892
+rect 216 801 225 892
+rect 190 701 225 801
+rect 190 610 199 701
+rect 216 610 225 701
+rect 190 601 225 610
+rect 325 892 360 901
+rect 325 801 334 892
+rect 351 801 360 892
+rect 325 701 360 801
+rect 325 610 334 701
+rect 351 610 360 701
+rect 325 601 360 610
+<< mvndiffc >>
+rect 199 801 216 892
+rect 199 610 216 701
+rect 334 801 351 892
+rect 334 610 351 701
+<< poly >>
+rect 225 901 325 952
+rect 225 550 325 601
+<< locali >>
+rect 199 892 216 901
+rect 199 701 216 801
+rect 199 601 216 610
+rect 334 892 351 901
+rect 334 701 351 801
+rect 334 601 351 610
+<< end >>
diff --git a/mag/sc_nmos_426.mag b/mag/sc_nmos_426.mag
new file mode 100644
index 0000000..cb86688
--- /dev/null
+++ b/mag/sc_nmos_426.mag
@@ -0,0 +1,1176 @@
+magic
+tech sky130A
+timestamp 1616700505
+<< mvnmos >>
+rect 225 601 825 4801
+<< mvndiff >>
+rect 190 4768 225 4801
+rect 190 4750 199 4768
+rect 216 4750 225 4768
+rect 190 4732 225 4750
+rect 190 4714 199 4732
+rect 216 4714 225 4732
+rect 190 4696 225 4714
+rect 190 4678 199 4696
+rect 216 4678 225 4696
+rect 190 4660 225 4678
+rect 190 4642 199 4660
+rect 216 4642 225 4660
+rect 190 4624 225 4642
+rect 190 4606 199 4624
+rect 216 4606 225 4624
+rect 190 4588 225 4606
+rect 190 4570 199 4588
+rect 216 4570 225 4588
+rect 190 4552 225 4570
+rect 190 4534 199 4552
+rect 216 4534 225 4552
+rect 190 4516 225 4534
+rect 190 4498 199 4516
+rect 216 4498 225 4516
+rect 190 4480 225 4498
+rect 190 4462 199 4480
+rect 216 4462 225 4480
+rect 190 4444 225 4462
+rect 190 4426 199 4444
+rect 216 4426 225 4444
+rect 190 4408 225 4426
+rect 190 4390 199 4408
+rect 216 4390 225 4408
+rect 190 4372 225 4390
+rect 190 4354 199 4372
+rect 216 4354 225 4372
+rect 190 4336 225 4354
+rect 190 4318 199 4336
+rect 216 4318 225 4336
+rect 190 4300 225 4318
+rect 190 4282 199 4300
+rect 216 4282 225 4300
+rect 190 4264 225 4282
+rect 190 4246 199 4264
+rect 216 4246 225 4264
+rect 190 4228 225 4246
+rect 190 4210 199 4228
+rect 216 4210 225 4228
+rect 190 4192 225 4210
+rect 190 4174 199 4192
+rect 216 4174 225 4192
+rect 190 4156 225 4174
+rect 190 4138 199 4156
+rect 216 4138 225 4156
+rect 190 4120 225 4138
+rect 190 4102 199 4120
+rect 216 4102 225 4120
+rect 190 4084 225 4102
+rect 190 4066 199 4084
+rect 216 4066 225 4084
+rect 190 4048 225 4066
+rect 190 4030 199 4048
+rect 216 4030 225 4048
+rect 190 4012 225 4030
+rect 190 3994 199 4012
+rect 216 3994 225 4012
+rect 190 3976 225 3994
+rect 190 3958 199 3976
+rect 216 3958 225 3976
+rect 190 3940 225 3958
+rect 190 3922 199 3940
+rect 216 3922 225 3940
+rect 190 3904 225 3922
+rect 190 3886 199 3904
+rect 216 3886 225 3904
+rect 190 3868 225 3886
+rect 190 3850 199 3868
+rect 216 3850 225 3868
+rect 190 3832 225 3850
+rect 190 3814 199 3832
+rect 216 3814 225 3832
+rect 190 3796 225 3814
+rect 190 3778 199 3796
+rect 216 3778 225 3796
+rect 190 3760 225 3778
+rect 190 3742 199 3760
+rect 216 3742 225 3760
+rect 190 3724 225 3742
+rect 190 3706 199 3724
+rect 216 3706 225 3724
+rect 190 3688 225 3706
+rect 190 3670 199 3688
+rect 216 3670 225 3688
+rect 190 3652 225 3670
+rect 190 3634 199 3652
+rect 216 3634 225 3652
+rect 190 3616 225 3634
+rect 190 3598 199 3616
+rect 216 3598 225 3616
+rect 190 3580 225 3598
+rect 190 3562 199 3580
+rect 216 3562 225 3580
+rect 190 3544 225 3562
+rect 190 3526 199 3544
+rect 216 3526 225 3544
+rect 190 3508 225 3526
+rect 190 3490 199 3508
+rect 216 3490 225 3508
+rect 190 3472 225 3490
+rect 190 3454 199 3472
+rect 216 3454 225 3472
+rect 190 3436 225 3454
+rect 190 3418 199 3436
+rect 216 3418 225 3436
+rect 190 3400 225 3418
+rect 190 3382 199 3400
+rect 216 3382 225 3400
+rect 190 3364 225 3382
+rect 190 3346 199 3364
+rect 216 3346 225 3364
+rect 190 3328 225 3346
+rect 190 3310 199 3328
+rect 216 3310 225 3328
+rect 190 3292 225 3310
+rect 190 3274 199 3292
+rect 216 3274 225 3292
+rect 190 3256 225 3274
+rect 190 3238 199 3256
+rect 216 3238 225 3256
+rect 190 3220 225 3238
+rect 190 3202 199 3220
+rect 216 3202 225 3220
+rect 190 3184 225 3202
+rect 190 3166 199 3184
+rect 216 3166 225 3184
+rect 190 3148 225 3166
+rect 190 3130 199 3148
+rect 216 3130 225 3148
+rect 190 3112 225 3130
+rect 190 3094 199 3112
+rect 216 3094 225 3112
+rect 190 3076 225 3094
+rect 190 3058 199 3076
+rect 216 3058 225 3076
+rect 190 3040 225 3058
+rect 190 3022 199 3040
+rect 216 3022 225 3040
+rect 190 3004 225 3022
+rect 190 2986 199 3004
+rect 216 2986 225 3004
+rect 190 2968 225 2986
+rect 190 2950 199 2968
+rect 216 2950 225 2968
+rect 190 2932 225 2950
+rect 190 2914 199 2932
+rect 216 2914 225 2932
+rect 190 2896 225 2914
+rect 190 2878 199 2896
+rect 216 2878 225 2896
+rect 190 2860 225 2878
+rect 190 2842 199 2860
+rect 216 2842 225 2860
+rect 190 2824 225 2842
+rect 190 2806 199 2824
+rect 216 2806 225 2824
+rect 190 2788 225 2806
+rect 190 2770 199 2788
+rect 216 2770 225 2788
+rect 190 2752 225 2770
+rect 190 2734 199 2752
+rect 216 2734 225 2752
+rect 190 2716 225 2734
+rect 190 2698 199 2716
+rect 216 2698 225 2716
+rect 190 2680 225 2698
+rect 190 2662 199 2680
+rect 216 2662 225 2680
+rect 190 2644 225 2662
+rect 190 2626 199 2644
+rect 216 2626 225 2644
+rect 190 2608 225 2626
+rect 190 2590 199 2608
+rect 216 2590 225 2608
+rect 190 2572 225 2590
+rect 190 2554 199 2572
+rect 216 2554 225 2572
+rect 190 2536 225 2554
+rect 190 2518 199 2536
+rect 216 2518 225 2536
+rect 190 2500 225 2518
+rect 190 2482 199 2500
+rect 216 2482 225 2500
+rect 190 2464 225 2482
+rect 190 2446 199 2464
+rect 216 2446 225 2464
+rect 190 2428 225 2446
+rect 190 2410 199 2428
+rect 216 2410 225 2428
+rect 190 2392 225 2410
+rect 190 2374 199 2392
+rect 216 2374 225 2392
+rect 190 2356 225 2374
+rect 190 2338 199 2356
+rect 216 2338 225 2356
+rect 190 2320 225 2338
+rect 190 2302 199 2320
+rect 216 2302 225 2320
+rect 190 2284 225 2302
+rect 190 2266 199 2284
+rect 216 2266 225 2284
+rect 190 2248 225 2266
+rect 190 2230 199 2248
+rect 216 2230 225 2248
+rect 190 2212 225 2230
+rect 190 2194 199 2212
+rect 216 2194 225 2212
+rect 190 2176 225 2194
+rect 190 2158 199 2176
+rect 216 2158 225 2176
+rect 190 2140 225 2158
+rect 190 2122 199 2140
+rect 216 2122 225 2140
+rect 190 2104 225 2122
+rect 190 2086 199 2104
+rect 216 2086 225 2104
+rect 190 2068 225 2086
+rect 190 2050 199 2068
+rect 216 2050 225 2068
+rect 190 2032 225 2050
+rect 190 2014 199 2032
+rect 216 2014 225 2032
+rect 190 1996 225 2014
+rect 190 1978 199 1996
+rect 216 1978 225 1996
+rect 190 1960 225 1978
+rect 190 1942 199 1960
+rect 216 1942 225 1960
+rect 190 1924 225 1942
+rect 190 1906 199 1924
+rect 216 1906 225 1924
+rect 190 1888 225 1906
+rect 190 1870 199 1888
+rect 216 1870 225 1888
+rect 190 1852 225 1870
+rect 190 1834 199 1852
+rect 216 1834 225 1852
+rect 190 1816 225 1834
+rect 190 1798 199 1816
+rect 216 1798 225 1816
+rect 190 1780 225 1798
+rect 190 1762 199 1780
+rect 216 1762 225 1780
+rect 190 1744 225 1762
+rect 190 1726 199 1744
+rect 216 1726 225 1744
+rect 190 1708 225 1726
+rect 190 1690 199 1708
+rect 216 1690 225 1708
+rect 190 1672 225 1690
+rect 190 1654 199 1672
+rect 216 1654 225 1672
+rect 190 1636 225 1654
+rect 190 1618 199 1636
+rect 216 1618 225 1636
+rect 190 1600 225 1618
+rect 190 1582 199 1600
+rect 216 1582 225 1600
+rect 190 1564 225 1582
+rect 190 1546 199 1564
+rect 216 1546 225 1564
+rect 190 1528 225 1546
+rect 190 1510 199 1528
+rect 216 1510 225 1528
+rect 190 1492 225 1510
+rect 190 1474 199 1492
+rect 216 1474 225 1492
+rect 190 1456 225 1474
+rect 190 1438 199 1456
+rect 216 1438 225 1456
+rect 190 1420 225 1438
+rect 190 1402 199 1420
+rect 216 1402 225 1420
+rect 190 1384 225 1402
+rect 190 1366 199 1384
+rect 216 1366 225 1384
+rect 190 1348 225 1366
+rect 190 1330 199 1348
+rect 216 1330 225 1348
+rect 190 1312 225 1330
+rect 190 1294 199 1312
+rect 216 1294 225 1312
+rect 190 1276 225 1294
+rect 190 1258 199 1276
+rect 216 1258 225 1276
+rect 190 1240 225 1258
+rect 190 1222 199 1240
+rect 216 1222 225 1240
+rect 190 1204 225 1222
+rect 190 1186 199 1204
+rect 216 1186 225 1204
+rect 190 1168 225 1186
+rect 190 1150 199 1168
+rect 216 1150 225 1168
+rect 190 1132 225 1150
+rect 190 1114 199 1132
+rect 216 1114 225 1132
+rect 190 1096 225 1114
+rect 190 1078 199 1096
+rect 216 1078 225 1096
+rect 190 1060 225 1078
+rect 190 1042 199 1060
+rect 216 1042 225 1060
+rect 190 1024 225 1042
+rect 190 1006 199 1024
+rect 216 1006 225 1024
+rect 190 988 225 1006
+rect 190 970 199 988
+rect 216 970 225 988
+rect 190 952 225 970
+rect 190 934 199 952
+rect 216 934 225 952
+rect 190 916 225 934
+rect 190 898 199 916
+rect 216 898 225 916
+rect 190 880 225 898
+rect 190 862 199 880
+rect 216 862 225 880
+rect 190 844 225 862
+rect 190 826 199 844
+rect 216 826 225 844
+rect 190 808 225 826
+rect 190 790 199 808
+rect 216 790 225 808
+rect 190 772 225 790
+rect 190 754 199 772
+rect 216 754 225 772
+rect 190 736 225 754
+rect 190 718 199 736
+rect 216 718 225 736
+rect 190 700 225 718
+rect 190 682 199 700
+rect 216 682 225 700
+rect 190 664 225 682
+rect 190 646 199 664
+rect 216 646 225 664
+rect 190 628 225 646
+rect 190 610 199 628
+rect 216 610 225 628
+rect 190 601 225 610
+rect 825 4768 860 4801
+rect 825 4750 834 4768
+rect 851 4750 860 4768
+rect 825 4732 860 4750
+rect 825 4714 834 4732
+rect 851 4714 860 4732
+rect 825 4696 860 4714
+rect 825 4678 834 4696
+rect 851 4678 860 4696
+rect 825 4660 860 4678
+rect 825 4642 834 4660
+rect 851 4642 860 4660
+rect 825 4624 860 4642
+rect 825 4606 834 4624
+rect 851 4606 860 4624
+rect 825 4588 860 4606
+rect 825 4570 834 4588
+rect 851 4570 860 4588
+rect 825 4552 860 4570
+rect 825 4534 834 4552
+rect 851 4534 860 4552
+rect 825 4516 860 4534
+rect 825 4498 834 4516
+rect 851 4498 860 4516
+rect 825 4480 860 4498
+rect 825 4462 834 4480
+rect 851 4462 860 4480
+rect 825 4444 860 4462
+rect 825 4426 834 4444
+rect 851 4426 860 4444
+rect 825 4408 860 4426
+rect 825 4390 834 4408
+rect 851 4390 860 4408
+rect 825 4372 860 4390
+rect 825 4354 834 4372
+rect 851 4354 860 4372
+rect 825 4336 860 4354
+rect 825 4318 834 4336
+rect 851 4318 860 4336
+rect 825 4300 860 4318
+rect 825 4282 834 4300
+rect 851 4282 860 4300
+rect 825 4264 860 4282
+rect 825 4246 834 4264
+rect 851 4246 860 4264
+rect 825 4228 860 4246
+rect 825 4210 834 4228
+rect 851 4210 860 4228
+rect 825 4192 860 4210
+rect 825 4174 834 4192
+rect 851 4174 860 4192
+rect 825 4156 860 4174
+rect 825 4138 834 4156
+rect 851 4138 860 4156
+rect 825 4120 860 4138
+rect 825 4102 834 4120
+rect 851 4102 860 4120
+rect 825 4084 860 4102
+rect 825 4066 834 4084
+rect 851 4066 860 4084
+rect 825 4048 860 4066
+rect 825 4030 834 4048
+rect 851 4030 860 4048
+rect 825 4012 860 4030
+rect 825 3994 834 4012
+rect 851 3994 860 4012
+rect 825 3976 860 3994
+rect 825 3958 834 3976
+rect 851 3958 860 3976
+rect 825 3940 860 3958
+rect 825 3922 834 3940
+rect 851 3922 860 3940
+rect 825 3904 860 3922
+rect 825 3886 834 3904
+rect 851 3886 860 3904
+rect 825 3868 860 3886
+rect 825 3850 834 3868
+rect 851 3850 860 3868
+rect 825 3832 860 3850
+rect 825 3814 834 3832
+rect 851 3814 860 3832
+rect 825 3796 860 3814
+rect 825 3778 834 3796
+rect 851 3778 860 3796
+rect 825 3760 860 3778
+rect 825 3742 834 3760
+rect 851 3742 860 3760
+rect 825 3724 860 3742
+rect 825 3706 834 3724
+rect 851 3706 860 3724
+rect 825 3688 860 3706
+rect 825 3670 834 3688
+rect 851 3670 860 3688
+rect 825 3652 860 3670
+rect 825 3634 834 3652
+rect 851 3634 860 3652
+rect 825 3616 860 3634
+rect 825 3598 834 3616
+rect 851 3598 860 3616
+rect 825 3580 860 3598
+rect 825 3562 834 3580
+rect 851 3562 860 3580
+rect 825 3544 860 3562
+rect 825 3526 834 3544
+rect 851 3526 860 3544
+rect 825 3508 860 3526
+rect 825 3490 834 3508
+rect 851 3490 860 3508
+rect 825 3472 860 3490
+rect 825 3454 834 3472
+rect 851 3454 860 3472
+rect 825 3436 860 3454
+rect 825 3418 834 3436
+rect 851 3418 860 3436
+rect 825 3400 860 3418
+rect 825 3382 834 3400
+rect 851 3382 860 3400
+rect 825 3364 860 3382
+rect 825 3346 834 3364
+rect 851 3346 860 3364
+rect 825 3328 860 3346
+rect 825 3310 834 3328
+rect 851 3310 860 3328
+rect 825 3292 860 3310
+rect 825 3274 834 3292
+rect 851 3274 860 3292
+rect 825 3256 860 3274
+rect 825 3238 834 3256
+rect 851 3238 860 3256
+rect 825 3220 860 3238
+rect 825 3202 834 3220
+rect 851 3202 860 3220
+rect 825 3184 860 3202
+rect 825 3166 834 3184
+rect 851 3166 860 3184
+rect 825 3148 860 3166
+rect 825 3130 834 3148
+rect 851 3130 860 3148
+rect 825 3112 860 3130
+rect 825 3094 834 3112
+rect 851 3094 860 3112
+rect 825 3076 860 3094
+rect 825 3058 834 3076
+rect 851 3058 860 3076
+rect 825 3040 860 3058
+rect 825 3022 834 3040
+rect 851 3022 860 3040
+rect 825 3004 860 3022
+rect 825 2986 834 3004
+rect 851 2986 860 3004
+rect 825 2968 860 2986
+rect 825 2950 834 2968
+rect 851 2950 860 2968
+rect 825 2932 860 2950
+rect 825 2914 834 2932
+rect 851 2914 860 2932
+rect 825 2896 860 2914
+rect 825 2878 834 2896
+rect 851 2878 860 2896
+rect 825 2860 860 2878
+rect 825 2842 834 2860
+rect 851 2842 860 2860
+rect 825 2824 860 2842
+rect 825 2806 834 2824
+rect 851 2806 860 2824
+rect 825 2788 860 2806
+rect 825 2770 834 2788
+rect 851 2770 860 2788
+rect 825 2752 860 2770
+rect 825 2734 834 2752
+rect 851 2734 860 2752
+rect 825 2716 860 2734
+rect 825 2698 834 2716
+rect 851 2698 860 2716
+rect 825 2680 860 2698
+rect 825 2662 834 2680
+rect 851 2662 860 2680
+rect 825 2644 860 2662
+rect 825 2626 834 2644
+rect 851 2626 860 2644
+rect 825 2608 860 2626
+rect 825 2590 834 2608
+rect 851 2590 860 2608
+rect 825 2572 860 2590
+rect 825 2554 834 2572
+rect 851 2554 860 2572
+rect 825 2536 860 2554
+rect 825 2518 834 2536
+rect 851 2518 860 2536
+rect 825 2500 860 2518
+rect 825 2482 834 2500
+rect 851 2482 860 2500
+rect 825 2464 860 2482
+rect 825 2446 834 2464
+rect 851 2446 860 2464
+rect 825 2428 860 2446
+rect 825 2410 834 2428
+rect 851 2410 860 2428
+rect 825 2392 860 2410
+rect 825 2374 834 2392
+rect 851 2374 860 2392
+rect 825 2356 860 2374
+rect 825 2338 834 2356
+rect 851 2338 860 2356
+rect 825 2320 860 2338
+rect 825 2302 834 2320
+rect 851 2302 860 2320
+rect 825 2284 860 2302
+rect 825 2266 834 2284
+rect 851 2266 860 2284
+rect 825 2248 860 2266
+rect 825 2230 834 2248
+rect 851 2230 860 2248
+rect 825 2212 860 2230
+rect 825 2194 834 2212
+rect 851 2194 860 2212
+rect 825 2176 860 2194
+rect 825 2158 834 2176
+rect 851 2158 860 2176
+rect 825 2140 860 2158
+rect 825 2122 834 2140
+rect 851 2122 860 2140
+rect 825 2104 860 2122
+rect 825 2086 834 2104
+rect 851 2086 860 2104
+rect 825 2068 860 2086
+rect 825 2050 834 2068
+rect 851 2050 860 2068
+rect 825 2032 860 2050
+rect 825 2014 834 2032
+rect 851 2014 860 2032
+rect 825 1996 860 2014
+rect 825 1978 834 1996
+rect 851 1978 860 1996
+rect 825 1960 860 1978
+rect 825 1942 834 1960
+rect 851 1942 860 1960
+rect 825 1924 860 1942
+rect 825 1906 834 1924
+rect 851 1906 860 1924
+rect 825 1888 860 1906
+rect 825 1870 834 1888
+rect 851 1870 860 1888
+rect 825 1852 860 1870
+rect 825 1834 834 1852
+rect 851 1834 860 1852
+rect 825 1816 860 1834
+rect 825 1798 834 1816
+rect 851 1798 860 1816
+rect 825 1780 860 1798
+rect 825 1762 834 1780
+rect 851 1762 860 1780
+rect 825 1744 860 1762
+rect 825 1726 834 1744
+rect 851 1726 860 1744
+rect 825 1708 860 1726
+rect 825 1690 834 1708
+rect 851 1690 860 1708
+rect 825 1672 860 1690
+rect 825 1654 834 1672
+rect 851 1654 860 1672
+rect 825 1636 860 1654
+rect 825 1618 834 1636
+rect 851 1618 860 1636
+rect 825 1600 860 1618
+rect 825 1582 834 1600
+rect 851 1582 860 1600
+rect 825 1564 860 1582
+rect 825 1546 834 1564
+rect 851 1546 860 1564
+rect 825 1528 860 1546
+rect 825 1510 834 1528
+rect 851 1510 860 1528
+rect 825 1492 860 1510
+rect 825 1474 834 1492
+rect 851 1474 860 1492
+rect 825 1456 860 1474
+rect 825 1438 834 1456
+rect 851 1438 860 1456
+rect 825 1420 860 1438
+rect 825 1402 834 1420
+rect 851 1402 860 1420
+rect 825 1384 860 1402
+rect 825 1366 834 1384
+rect 851 1366 860 1384
+rect 825 1348 860 1366
+rect 825 1330 834 1348
+rect 851 1330 860 1348
+rect 825 1312 860 1330
+rect 825 1294 834 1312
+rect 851 1294 860 1312
+rect 825 1276 860 1294
+rect 825 1258 834 1276
+rect 851 1258 860 1276
+rect 825 1240 860 1258
+rect 825 1222 834 1240
+rect 851 1222 860 1240
+rect 825 1204 860 1222
+rect 825 1186 834 1204
+rect 851 1186 860 1204
+rect 825 1168 860 1186
+rect 825 1150 834 1168
+rect 851 1150 860 1168
+rect 825 1132 860 1150
+rect 825 1114 834 1132
+rect 851 1114 860 1132
+rect 825 1096 860 1114
+rect 825 1078 834 1096
+rect 851 1078 860 1096
+rect 825 1060 860 1078
+rect 825 1042 834 1060
+rect 851 1042 860 1060
+rect 825 1024 860 1042
+rect 825 1006 834 1024
+rect 851 1006 860 1024
+rect 825 988 860 1006
+rect 825 970 834 988
+rect 851 970 860 988
+rect 825 952 860 970
+rect 825 934 834 952
+rect 851 934 860 952
+rect 825 916 860 934
+rect 825 898 834 916
+rect 851 898 860 916
+rect 825 880 860 898
+rect 825 862 834 880
+rect 851 862 860 880
+rect 825 844 860 862
+rect 825 826 834 844
+rect 851 826 860 844
+rect 825 808 860 826
+rect 825 790 834 808
+rect 851 790 860 808
+rect 825 772 860 790
+rect 825 754 834 772
+rect 851 754 860 772
+rect 825 736 860 754
+rect 825 718 834 736
+rect 851 718 860 736
+rect 825 700 860 718
+rect 825 682 834 700
+rect 851 682 860 700
+rect 825 664 860 682
+rect 825 646 834 664
+rect 851 646 860 664
+rect 825 628 860 646
+rect 825 610 834 628
+rect 851 610 860 628
+rect 825 601 860 610
+<< mvndiffc >>
+rect 199 4750 216 4768
+rect 199 4714 216 4732
+rect 199 4678 216 4696
+rect 199 4642 216 4660
+rect 199 4606 216 4624
+rect 199 4570 216 4588
+rect 199 4534 216 4552
+rect 199 4498 216 4516
+rect 199 4462 216 4480
+rect 199 4426 216 4444
+rect 199 4390 216 4408
+rect 199 4354 216 4372
+rect 199 4318 216 4336
+rect 199 4282 216 4300
+rect 199 4246 216 4264
+rect 199 4210 216 4228
+rect 199 4174 216 4192
+rect 199 4138 216 4156
+rect 199 4102 216 4120
+rect 199 4066 216 4084
+rect 199 4030 216 4048
+rect 199 3994 216 4012
+rect 199 3958 216 3976
+rect 199 3922 216 3940
+rect 199 3886 216 3904
+rect 199 3850 216 3868
+rect 199 3814 216 3832
+rect 199 3778 216 3796
+rect 199 3742 216 3760
+rect 199 3706 216 3724
+rect 199 3670 216 3688
+rect 199 3634 216 3652
+rect 199 3598 216 3616
+rect 199 3562 216 3580
+rect 199 3526 216 3544
+rect 199 3490 216 3508
+rect 199 3454 216 3472
+rect 199 3418 216 3436
+rect 199 3382 216 3400
+rect 199 3346 216 3364
+rect 199 3310 216 3328
+rect 199 3274 216 3292
+rect 199 3238 216 3256
+rect 199 3202 216 3220
+rect 199 3166 216 3184
+rect 199 3130 216 3148
+rect 199 3094 216 3112
+rect 199 3058 216 3076
+rect 199 3022 216 3040
+rect 199 2986 216 3004
+rect 199 2950 216 2968
+rect 199 2914 216 2932
+rect 199 2878 216 2896
+rect 199 2842 216 2860
+rect 199 2806 216 2824
+rect 199 2770 216 2788
+rect 199 2734 216 2752
+rect 199 2698 216 2716
+rect 199 2662 216 2680
+rect 199 2626 216 2644
+rect 199 2590 216 2608
+rect 199 2554 216 2572
+rect 199 2518 216 2536
+rect 199 2482 216 2500
+rect 199 2446 216 2464
+rect 199 2410 216 2428
+rect 199 2374 216 2392
+rect 199 2338 216 2356
+rect 199 2302 216 2320
+rect 199 2266 216 2284
+rect 199 2230 216 2248
+rect 199 2194 216 2212
+rect 199 2158 216 2176
+rect 199 2122 216 2140
+rect 199 2086 216 2104
+rect 199 2050 216 2068
+rect 199 2014 216 2032
+rect 199 1978 216 1996
+rect 199 1942 216 1960
+rect 199 1906 216 1924
+rect 199 1870 216 1888
+rect 199 1834 216 1852
+rect 199 1798 216 1816
+rect 199 1762 216 1780
+rect 199 1726 216 1744
+rect 199 1690 216 1708
+rect 199 1654 216 1672
+rect 199 1618 216 1636
+rect 199 1582 216 1600
+rect 199 1546 216 1564
+rect 199 1510 216 1528
+rect 199 1474 216 1492
+rect 199 1438 216 1456
+rect 199 1402 216 1420
+rect 199 1366 216 1384
+rect 199 1330 216 1348
+rect 199 1294 216 1312
+rect 199 1258 216 1276
+rect 199 1222 216 1240
+rect 199 1186 216 1204
+rect 199 1150 216 1168
+rect 199 1114 216 1132
+rect 199 1078 216 1096
+rect 199 1042 216 1060
+rect 199 1006 216 1024
+rect 199 970 216 988
+rect 199 934 216 952
+rect 199 898 216 916
+rect 199 862 216 880
+rect 199 826 216 844
+rect 199 790 216 808
+rect 199 754 216 772
+rect 199 718 216 736
+rect 199 682 216 700
+rect 199 646 216 664
+rect 199 610 216 628
+rect 834 4750 851 4768
+rect 834 4714 851 4732
+rect 834 4678 851 4696
+rect 834 4642 851 4660
+rect 834 4606 851 4624
+rect 834 4570 851 4588
+rect 834 4534 851 4552
+rect 834 4498 851 4516
+rect 834 4462 851 4480
+rect 834 4426 851 4444
+rect 834 4390 851 4408
+rect 834 4354 851 4372
+rect 834 4318 851 4336
+rect 834 4282 851 4300
+rect 834 4246 851 4264
+rect 834 4210 851 4228
+rect 834 4174 851 4192
+rect 834 4138 851 4156
+rect 834 4102 851 4120
+rect 834 4066 851 4084
+rect 834 4030 851 4048
+rect 834 3994 851 4012
+rect 834 3958 851 3976
+rect 834 3922 851 3940
+rect 834 3886 851 3904
+rect 834 3850 851 3868
+rect 834 3814 851 3832
+rect 834 3778 851 3796
+rect 834 3742 851 3760
+rect 834 3706 851 3724
+rect 834 3670 851 3688
+rect 834 3634 851 3652
+rect 834 3598 851 3616
+rect 834 3562 851 3580
+rect 834 3526 851 3544
+rect 834 3490 851 3508
+rect 834 3454 851 3472
+rect 834 3418 851 3436
+rect 834 3382 851 3400
+rect 834 3346 851 3364
+rect 834 3310 851 3328
+rect 834 3274 851 3292
+rect 834 3238 851 3256
+rect 834 3202 851 3220
+rect 834 3166 851 3184
+rect 834 3130 851 3148
+rect 834 3094 851 3112
+rect 834 3058 851 3076
+rect 834 3022 851 3040
+rect 834 2986 851 3004
+rect 834 2950 851 2968
+rect 834 2914 851 2932
+rect 834 2878 851 2896
+rect 834 2842 851 2860
+rect 834 2806 851 2824
+rect 834 2770 851 2788
+rect 834 2734 851 2752
+rect 834 2698 851 2716
+rect 834 2662 851 2680
+rect 834 2626 851 2644
+rect 834 2590 851 2608
+rect 834 2554 851 2572
+rect 834 2518 851 2536
+rect 834 2482 851 2500
+rect 834 2446 851 2464
+rect 834 2410 851 2428
+rect 834 2374 851 2392
+rect 834 2338 851 2356
+rect 834 2302 851 2320
+rect 834 2266 851 2284
+rect 834 2230 851 2248
+rect 834 2194 851 2212
+rect 834 2158 851 2176
+rect 834 2122 851 2140
+rect 834 2086 851 2104
+rect 834 2050 851 2068
+rect 834 2014 851 2032
+rect 834 1978 851 1996
+rect 834 1942 851 1960
+rect 834 1906 851 1924
+rect 834 1870 851 1888
+rect 834 1834 851 1852
+rect 834 1798 851 1816
+rect 834 1762 851 1780
+rect 834 1726 851 1744
+rect 834 1690 851 1708
+rect 834 1654 851 1672
+rect 834 1618 851 1636
+rect 834 1582 851 1600
+rect 834 1546 851 1564
+rect 834 1510 851 1528
+rect 834 1474 851 1492
+rect 834 1438 851 1456
+rect 834 1402 851 1420
+rect 834 1366 851 1384
+rect 834 1330 851 1348
+rect 834 1294 851 1312
+rect 834 1258 851 1276
+rect 834 1222 851 1240
+rect 834 1186 851 1204
+rect 834 1150 851 1168
+rect 834 1114 851 1132
+rect 834 1078 851 1096
+rect 834 1042 851 1060
+rect 834 1006 851 1024
+rect 834 970 851 988
+rect 834 934 851 952
+rect 834 898 851 916
+rect 834 862 851 880
+rect 834 826 851 844
+rect 834 790 851 808
+rect 834 754 851 772
+rect 834 718 851 736
+rect 834 682 851 700
+rect 834 646 851 664
+rect 834 610 851 628
+<< poly >>
+rect 225 4801 825 4852
+rect 225 550 825 601
+<< locali >>
+rect 199 4768 216 4801
+rect 199 4732 216 4750
+rect 199 4696 216 4714
+rect 199 4660 216 4678
+rect 199 4624 216 4642
+rect 199 4588 216 4606
+rect 199 4552 216 4570
+rect 199 4516 216 4534
+rect 199 4480 216 4498
+rect 199 4444 216 4462
+rect 199 4408 216 4426
+rect 199 4372 216 4390
+rect 199 4336 216 4354
+rect 199 4300 216 4318
+rect 199 4264 216 4282
+rect 199 4228 216 4246
+rect 199 4192 216 4210
+rect 199 4156 216 4174
+rect 199 4120 216 4138
+rect 199 4084 216 4102
+rect 199 4048 216 4066
+rect 199 4012 216 4030
+rect 199 3976 216 3994
+rect 199 3940 216 3958
+rect 199 3904 216 3922
+rect 199 3868 216 3886
+rect 199 3832 216 3850
+rect 199 3796 216 3814
+rect 199 3760 216 3778
+rect 199 3724 216 3742
+rect 199 3688 216 3706
+rect 199 3652 216 3670
+rect 199 3616 216 3634
+rect 199 3580 216 3598
+rect 199 3544 216 3562
+rect 199 3508 216 3526
+rect 199 3472 216 3490
+rect 199 3436 216 3454
+rect 199 3400 216 3418
+rect 199 3364 216 3382
+rect 199 3328 216 3346
+rect 199 3292 216 3310
+rect 199 3256 216 3274
+rect 199 3220 216 3238
+rect 199 3184 216 3202
+rect 199 3148 216 3166
+rect 199 3112 216 3130
+rect 199 3076 216 3094
+rect 199 3040 216 3058
+rect 199 3004 216 3022
+rect 199 2968 216 2986
+rect 199 2932 216 2950
+rect 199 2896 216 2914
+rect 199 2860 216 2878
+rect 199 2824 216 2842
+rect 199 2788 216 2806
+rect 199 2752 216 2770
+rect 199 2716 216 2734
+rect 199 2680 216 2698
+rect 199 2644 216 2662
+rect 199 2608 216 2626
+rect 199 2572 216 2590
+rect 199 2536 216 2554
+rect 199 2500 216 2518
+rect 199 2464 216 2482
+rect 199 2428 216 2446
+rect 199 2392 216 2410
+rect 199 2356 216 2374
+rect 199 2320 216 2338
+rect 199 2284 216 2302
+rect 199 2248 216 2266
+rect 199 2212 216 2230
+rect 199 2176 216 2194
+rect 199 2140 216 2158
+rect 199 2104 216 2122
+rect 199 2068 216 2086
+rect 199 2032 216 2050
+rect 199 1996 216 2014
+rect 199 1960 216 1978
+rect 199 1924 216 1942
+rect 199 1888 216 1906
+rect 199 1852 216 1870
+rect 199 1816 216 1834
+rect 199 1780 216 1798
+rect 199 1744 216 1762
+rect 199 1708 216 1726
+rect 199 1672 216 1690
+rect 199 1636 216 1654
+rect 199 1600 216 1618
+rect 199 1564 216 1582
+rect 199 1528 216 1546
+rect 199 1492 216 1510
+rect 199 1456 216 1474
+rect 199 1420 216 1438
+rect 199 1384 216 1402
+rect 199 1348 216 1366
+rect 199 1312 216 1330
+rect 199 1276 216 1294
+rect 199 1240 216 1258
+rect 199 1204 216 1222
+rect 199 1168 216 1186
+rect 199 1132 216 1150
+rect 199 1096 216 1114
+rect 199 1060 216 1078
+rect 199 1024 216 1042
+rect 199 988 216 1006
+rect 199 952 216 970
+rect 199 916 216 934
+rect 199 880 216 898
+rect 199 844 216 862
+rect 199 808 216 826
+rect 199 772 216 790
+rect 199 736 216 754
+rect 199 700 216 718
+rect 199 664 216 682
+rect 199 628 216 646
+rect 199 601 216 610
+rect 834 4768 851 4801
+rect 834 4732 851 4750
+rect 834 4696 851 4714
+rect 834 4660 851 4678
+rect 834 4624 851 4642
+rect 834 4588 851 4606
+rect 834 4552 851 4570
+rect 834 4516 851 4534
+rect 834 4480 851 4498
+rect 834 4444 851 4462
+rect 834 4408 851 4426
+rect 834 4372 851 4390
+rect 834 4336 851 4354
+rect 834 4300 851 4318
+rect 834 4264 851 4282
+rect 834 4228 851 4246
+rect 834 4192 851 4210
+rect 834 4156 851 4174
+rect 834 4120 851 4138
+rect 834 4084 851 4102
+rect 834 4048 851 4066
+rect 834 4012 851 4030
+rect 834 3976 851 3994
+rect 834 3940 851 3958
+rect 834 3904 851 3922
+rect 834 3868 851 3886
+rect 834 3832 851 3850
+rect 834 3796 851 3814
+rect 834 3760 851 3778
+rect 834 3724 851 3742
+rect 834 3688 851 3706
+rect 834 3652 851 3670
+rect 834 3616 851 3634
+rect 834 3580 851 3598
+rect 834 3544 851 3562
+rect 834 3508 851 3526
+rect 834 3472 851 3490
+rect 834 3436 851 3454
+rect 834 3400 851 3418
+rect 834 3364 851 3382
+rect 834 3328 851 3346
+rect 834 3292 851 3310
+rect 834 3256 851 3274
+rect 834 3220 851 3238
+rect 834 3184 851 3202
+rect 834 3148 851 3166
+rect 834 3112 851 3130
+rect 834 3076 851 3094
+rect 834 3040 851 3058
+rect 834 3004 851 3022
+rect 834 2968 851 2986
+rect 834 2932 851 2950
+rect 834 2896 851 2914
+rect 834 2860 851 2878
+rect 834 2824 851 2842
+rect 834 2788 851 2806
+rect 834 2752 851 2770
+rect 834 2716 851 2734
+rect 834 2680 851 2698
+rect 834 2644 851 2662
+rect 834 2608 851 2626
+rect 834 2572 851 2590
+rect 834 2536 851 2554
+rect 834 2500 851 2518
+rect 834 2464 851 2482
+rect 834 2428 851 2446
+rect 834 2392 851 2410
+rect 834 2356 851 2374
+rect 834 2320 851 2338
+rect 834 2284 851 2302
+rect 834 2248 851 2266
+rect 834 2212 851 2230
+rect 834 2176 851 2194
+rect 834 2140 851 2158
+rect 834 2104 851 2122
+rect 834 2068 851 2086
+rect 834 2032 851 2050
+rect 834 1996 851 2014
+rect 834 1960 851 1978
+rect 834 1924 851 1942
+rect 834 1888 851 1906
+rect 834 1852 851 1870
+rect 834 1816 851 1834
+rect 834 1780 851 1798
+rect 834 1744 851 1762
+rect 834 1708 851 1726
+rect 834 1672 851 1690
+rect 834 1636 851 1654
+rect 834 1600 851 1618
+rect 834 1564 851 1582
+rect 834 1528 851 1546
+rect 834 1492 851 1510
+rect 834 1456 851 1474
+rect 834 1420 851 1438
+rect 834 1384 851 1402
+rect 834 1348 851 1366
+rect 834 1312 851 1330
+rect 834 1276 851 1294
+rect 834 1240 851 1258
+rect 834 1204 851 1222
+rect 834 1168 851 1186
+rect 834 1132 851 1150
+rect 834 1096 851 1114
+rect 834 1060 851 1078
+rect 834 1024 851 1042
+rect 834 988 851 1006
+rect 834 952 851 970
+rect 834 916 851 934
+rect 834 880 851 898
+rect 834 844 851 862
+rect 834 808 851 826
+rect 834 772 851 790
+rect 834 736 851 754
+rect 834 700 851 718
+rect 834 664 851 682
+rect 834 628 851 646
+rect 834 601 851 610
+<< end >>
diff --git a/mag/sc_nmos_426.tcl b/mag/sc_nmos_426.tcl
new file mode 100644
index 0000000..1902236
--- /dev/null
+++ b/mag/sc_nmos_426.tcl
@@ -0,0 +1,60 @@
+##Initiaze pointer##
+set x 0
+set y 0
+box position $x $y
+
+##Nmos layout starts here##
+#Create poly-strips#
+set sc_poly_width 600
+set sc_poly_height 4302
+set sc_box_position_x [expr $x+225]
+set sc_box_position_y [expr $y+550]
+box position $sc_box_position_x $sc_box_position_y
+box size $sc_poly_width $sc_poly_height
+paint poly
+
+#Create mvndiffusion area#
+set sc_mvndiff_width 670
+set sc_mvndiff_height 4200
+set sc_mvndiff_spacing 627
+set sc_box_position_x [expr $x+190]
+set sc_box_position_y [expr $y+601]
+box position $sc_box_position_x $sc_box_position_y
+box size $sc_mvndiff_width $sc_mvndiff_height
+paint mvndiff
+
+#Create local interconnect layer#
+#For source and drain terminals#
+set sc_li_width 17
+set sc_li_height 4200
+set sc_mos_terminals 2
+set sc_box_position_x [expr $x+199]
+set sc_box_position_y [expr $y+601]
+set sc_li_spacing_x 635
+set sc_li_spacing_y 627
+for {set i 1} {$i <= $sc_mos_terminals} {incr i} {
+ box position $sc_box_position_x $sc_box_position_y
+ box size $sc_li_width $sc_li_height
+ paint li
+ set sc_box_position_x [expr $sc_box_position_x+$sc_li_spacing_x]
+}
+
+#Create ndiffusioncontact area#
+set sc_mvndc_width 17
+set sc_mvndc_height 18
+set sc_mos_terminals 2
+set sc_mos_spacing 627
+set sc_box_position_x [expr $x+199]
+set sc_box_position_y [expr $y+610]
+set sc_mvndc_spacing_x 635
+set sc_mvndc_spacing_y 18
+for {set j 1} {$j <= $sc_mos_terminals} {incr j} {
+ for {set i 1} {$i <= [expr $sc_mvndiff_height/ [expr $sc_mvndc_height + $sc_mvndc_spacing_y]]} {incr i} {
+ box position $sc_box_position_x $sc_box_position_y
+ box size $sc_mvndc_width $sc_mvndc_height
+ paint mvndcontact
+ set sc_box_position_y [expr $sc_box_position_y+$sc_mvndc_spacing_y+$sc_mvndc_height]
+ }
+ set sc_box_position_x [expr $sc_box_position_x+$sc_mvndc_spacing_x]
+ set sc_box_position_y [expr $y+610]
+}
diff --git a/mag/sc_pmos.mag b/mag/sc_pmos.mag
new file mode 100644
index 0000000..628cf84
--- /dev/null
+++ b/mag/sc_pmos.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+timestamp 1616540248
+<< nwell >>
+rect 200 1464 350 7600
+<< mvpmos >>
+rect 250 1532 300 7532
+<< mvpdiff >>
+rect 250 7558 300 7567
+rect 250 7541 258 7558
+rect 292 7541 300 7558
+rect 250 7532 300 7541
+rect 250 1523 300 1532
+rect 250 1506 258 1523
+rect 292 1506 300 1523
+rect 250 1497 300 1506
+<< mvpdiffc >>
+rect 258 7541 292 7558
+rect 258 1506 292 1523
+<< poly >>
+rect 200 1532 250 7532
+rect 300 1532 350 7532
+<< locali >>
+rect 250 7541 258 7558
+rect 292 7541 300 7558
+rect 250 1506 258 1523
+rect 292 1506 300 1523
+<< end >>
diff --git a/mag/sky130A.tech b/mag/sky130A.tech
new file mode 100644
index 0000000..b276461
--- /dev/null
+++ b/mag/sky130A.tech
@@ -0,0 +1,5368 @@
+#------------------------------------------------------------------------
+# Copyright (c) 2020 R. Timothy Edwards
+# Revisions: See below
+#
+# This file is an Open Source foundry process describing
+# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
+# process. The file may be distributed under the terms
+# of the Apache 2.0 license agreement.
+#
+#------------------------------------------------------------------------
+tech
+ format 35
+ sky130A
+end
+
+version
+ version 1.0.180-0-gaac3d1a
+ description "SkyWater SKY130: Open Source rules and DRC"
+ requires magic-8.3.111
+end
+
+#------------------------------------------------------------------------
+# Status 7/10/20: Rev 1 (alpha):
+# First public release
+# Status 8/14/20: Rev 2 (alpha):
+# Started updating with new device/model naming convention
+# Status 1/3/21: Taking out of beta and declaring an official release.
+#------------------------------------------------------------------------
+
+#------------------------------------------------------------------------
+# Supported device types
+#------------------------------------------------------------------------
+# device name magic ID layer description
+#------------------------------------------------------------------------
+# sky130_fd_pr__nfet_01v8 nfet standard nFET
+# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
+# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
+# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
+# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
+# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
+# sky130_fd_pr__pfet_01v8 pfet standard pFET
+# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
+# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
+# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
+# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
+# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
+# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
+# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
+# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
+# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
+# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
+# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
+# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
+# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
+# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
+# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell
+# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
+# sky130_fd_pr__pnp_05v5 nbase PNP
+# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
+# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
+# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
+# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
+# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
+# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
+# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
+# sky130_fd_pr__res_generic_po npres n+ poly resistor
+# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
+# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
+# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
+# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
+# sky130_fd_pr__cap_var mvvaractor thickox varactor
+# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
+# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
+# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
+#
+# (*) Note that ppres may extract into some generic type called
+# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
+# allowed, and these are created from fixed layouts like the types below.
+#
+# (**) nFET and pFET in standard cells are the same as devices
+# outside of the standard cell except for the DRC rule for
+# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
+#
+#-------------------------------------------------------------
+# The following devices are not extracted but are represented
+# only by script-generated subcells in the PDK.
+#-------------------------------------------------------------
+# sky130_fd_pr__esd_nfet_01v8 ESD nFET
+# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
+# sky130_fd_pr__special_nfet_pass_flash flash nFET device
+# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
+# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
+# sky130_fd_pr__cap_vpp_* Vpp cap
+# sky130_fd_pr__ind_* inductor
+# sky130_fd_pr__fuse_m4 metal fuse device
+#--------------------------------------------------------------
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+ dwell,dw
+ well,w
+ active,a
+ locali,li1,li
+ metal1,m1
+ metal2,m2
+ metal3,m3
+ cap1,c1
+ metal4,m4
+ cap2,c2
+ metal5,m5
+ metali,mi
+ block,b
+ comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+ dwell dnwell,dnw
+ dwell isosubstrate,isosub
+
+# Wells
+ well nwell,nw
+ well pwell,pw
+ well rpw,rpwell
+ -well obswell
+ well pbase,npn
+ well nbase,pnp
+
+# Transistors
+ active nmos,ntransistor,nfet
+ -active scnmos,scntransistor,scnfet
+ -active npd,npdfet,sramnfet
+ -active npass,npassfet,srampassfet
+ active pmos,ptransistor,pfet
+ -active scpmos,scptransistor,scpfet
+ -active scpmoshvt,scpfethvt
+ -active ppu,ppufet,srampfet
+ active nnmos,nntransistor,nnfet
+ active mvnmos,mvntransistor,mvnfet
+ active mvpmos,mvptransistor,mvpfet
+ active mvnnmos,mvnntransistor,mvnnfet
+ -active mvnmosesd,mvntransistoresd,mvnfetesd
+ -active mvpmosesd,mvptransistoresd,mvpfetesd
+ active varactor,varact,var
+ active mvvaractor,mvvaract,mvvar
+
+ active pmoslvt,pfetlvt
+ active pmosmvt,pfetmvt
+ active pmoshvt,pfethvt
+ active nmoslvt,nfetlvt
+ active varactorhvt,varacthvt,varhvt
+ -active nsonos,sonos
+ -active sramnvar,corenvar,corenvaractor
+ -active srampvar,corepvar,corepvaractor
+
+# Diffusions
+ -active fomfill
+ active ndiff,ndiffusion,ndif
+ active pdiff,pdiffusion,pdif
+ active mvndiff,mvndiffusion,mvndif
+ active mvpdiff,mvpdiffusion,mvpdif
+ active ndiffc,ndcontact,ndc
+ active pdiffc,pdcontact,pdc
+ active mvndiffc,mvndcontact,mvndc
+ active mvpdiffc,mvpdcontact,mvpdc
+ active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
+ active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
+ active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
+ active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
+ active psubdiffcont,psubstratepcontact,psc,ptapc
+ active nsubdiffcont,nsubstratencontact,nsc,ntapc
+ active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
+ active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
+ -active obsactive
+ -active mvobsactive
+
+# Poly
+ active poly,p,polysilicon
+ active polycont,pc,pcontact,polycut,polyc
+ active xpolycontact,xpolyc,xpc
+ -active polyfill
+
+# Resistors
+ active npolyres,npres,mrp1
+ active ppolyres,ppres,xhrpoly
+ active xpolyres,xpres,xres,uhrpoly
+ active ndiffres,rnd,rdn,rndiff
+ active pdiffres,rpd,rdp,rpdiff
+ active mvndiffres,mvrnd,mvrdn,mvrndiff
+ active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+ active rmp
+
+# Diodes
+ active pdiode,pdi
+ active ndiode,ndi
+ active nndiode,nndi
+ active pdiodec,pdic
+ active ndiodec,ndic
+ active nndiodec,nndic
+ active mvpdiode,mvpdi
+ active mvndiode,mvndi
+ active mvpdiodec,mvpdic
+ active mvndiodec,mvndic
+ active pdiodelvt,pdilvt
+ active pdiodehvt,pdihvt
+ active ndiodelvt,ndilvt
+ active pdiodelvtc,pdilvtc
+ active pdiodehvtc,pdihvtc
+ active ndiodelvtc,ndilvtc
+
+# Local Interconnect
+ locali locali,li1,li
+ -locali corelocali,coreli1,coreli
+ locali rlocali,rli1,rli
+ locali viali,vial,mcon,m1c,v0
+ -locali obsli1,obsli
+ -locali obsli1c,obsmcon
+ -locali lifill
+
+# Metal 1
+ metal1 metal1,m1,met1
+ metal1 rmetal1,rm1,rmet1
+ metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+ metal1 padl
+ -metal1 m1fill
+
+# Metal 2
+ metal2 metal2,m2,met2
+ metal2 rmetal2,rm2,rmet2
+ metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+ -metal2 m2fill
+
+# Metal 3
+ metal3 metal3,m3,met3
+ metal3 rmetal3,rm3,rmet3
+ -metal3 obsm3
+ metal3 via3,v3
+ -metal3 m3fill
+
+ cap1 mimcap,mim,capm
+ cap1 mimcapcontact,mimcapc,mimcc,capmc
+
+# Metal 4
+ metal4 metal4,m4,met4
+ metal4 rmetal4,rm4,rmet4
+ -metal4 obsm4
+ metal4 via4,v4
+ -metal4 m4fill
+
+ cap2 mimcap2,mim2,capm2
+ cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
+
+# Metal 5
+ metal5 metal5,m5,met5
+ metal5 rm5,rmetal5,rmet5
+ -metal5 obsm5
+ -metal5 m5fill
+
+ metal5 mrdlcontact,mrdlc,pi1
+ metali metalrdl,mrdl,metrdl,rdl
+ -metali obsmrdl
+ metali pi2
+ block ubm
+
+# Miscellaneous
+ -block glass
+ -block fillblock,fillblock4
+ comment comment
+ -comment obscomment
+# fixed resistor width identifiers
+ -comment res0p35
+ -comment res0p69
+ -comment res1p41
+ -comment res2p85
+ -comment res5p73
+# fixed bipolar area identifiers
+ -comment pnp0p68
+ -comment pnp3p40
+ -comment npn1p00
+ -comment npn2p00
+ -comment npn11p0
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+ pc poly locali
+ ndc ndiff locali
+ pdc pdiff locali
+ nsc nsd locali
+ psc psd locali
+ ndic ndiode locali
+ ndilvtc ndiodelvt locali
+ nndic nndiode locali
+ pdic pdiode locali
+ pdilvtc pdiodelvt locali
+ pdihvtc pdiodehvt locali
+ xpc xpc locali
+
+ mvndc mvndiff locali
+ mvpdc mvpdiff locali
+ mvnsc mvnsd locali
+ mvpsc mvpsd locali
+ mvndic mvndiode locali
+ mvpdic mvpdiode locali
+
+ mcon locali metal1
+ obsmcon obsli metal1
+
+ via1 metal1 metal2
+ via2 metal2 metal3
+ via3 metal3 metal4
+ via4 metal4 metal5
+ stackable
+
+ # MiM cap contacts are not stackable!
+ mimcc mimcap metal4
+ mim2cc mimcap2 metal5
+
+ padl m1 m2 m3 m4 m5 glass
+
+ mrdlc metal5 mrdl
+ pi2 mrdl ubm
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+ allwellplane nwell
+ allnwell nwell,obswell,pnp
+
+ allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
+ allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
+ allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
+ allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
+ allfetsspecial scnfet,scpfet,scpfethvt
+ allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
+ allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
+
+ allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
+ allnactive allnactivenonfet,allnfets
+ allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
+ allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
+
+ allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
+ allpactive allpactivenonfet,allpfets
+ allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
+ allpactivetap *psd,*mvpsd,corepvar
+
+ allactivenonfet allnactivenonfet,allpactivenonfet
+ allactive allactivenonfet,allfets
+
+ allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+ allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
+ allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
+ alldifflv allndifflv,allpdifflv
+ allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
+ allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
+ alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
+
+ allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
+ allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
+ alldiffmv allndiffmv,allpdiffmv
+ allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
+ allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
+ alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
+ allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
+ allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+ alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
+
+ alldiffnonfet alldifflvnonfet,alldiffmvnonfet
+ alldiff alldifflv,alldiffmv,fomfill
+
+ allpolyres mrp1,xhrpoly,uhrpoly,rmp
+ allpolynonfet *poly,allpolyres,xpc
+ allpolynonres *poly,allfets,xpc
+
+ allpoly allpolynonfet,allfets
+ allpolynoncap *poly,xpc,allfets,allpolyres
+
+ allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
+ allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
+ allndiffcontmv mvndc,mvnsc,mvndic
+ allpdiffcontmv mvpdc,mvpsc,mvpdic
+ allndiffcont allndiffcontlv,allndiffcontmv
+ allpdiffcont allpdiffcontlv,allpdiffcontmv
+ alldiffcontlv allndiffcontlv,allpdiffcontlv
+ alldiffcontmv allndiffcontmv,allpdiffcontmv
+ alldiffcont alldiffcontlv,alldiffcontmv
+
+ allcont alldiffcont,pc
+
+ allres allpolyres,allactiveres
+
+ allli *locali,coreli,rli
+ allm1 *m1,rm1
+ allm2 *m2,rm2
+ allm3 *m3,rm3
+ allm4 *m4,rm4
+ allm5 *m5,rm5
+
+ allpad padl
+
+ psub pwell
+
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+ dnwell cwell
+ isosub subcircuit
+ nwell nwell
+ pwell pwell
+ rpwell pwell ptransistor_stripes
+ ndiff ndiffusion
+ fomfill ndiffusion
+ pdiff pdiffusion
+ nsd ndiff_in_nwell
+ psd pdiff_in_pwell
+ nfet ntransistor ntransistor_stripes
+ scnfet ntransistor ntransistor_stripes
+ npass ntransistor ntransistor_stripes
+ npd ntransistor ntransistor_stripes
+ pfet ptransistor ptransistor_stripes
+ scpfet ptransistor ptransistor_stripes
+ scpfethvt ptransistor ptransistor_stripes implant2
+ ppu ptransistor ptransistor_stripes
+ var polysilicon ndiff_in_nwell
+ ndc ndiffusion metal1 contact_X'es
+ pdc pdiffusion metal1 contact_X'es
+ nsc ndiff_in_nwell metal1 contact_X'es
+ psc pdiff_in_pwell metal1 contact_X'es
+ corenvar polysilicon ndiff_in_nwell
+ corepvar polysilicon pdiff_in_pwell
+
+ pnp nwell ntransistor_stripes
+ npn pwell ptransistor_stripes
+
+ pfetlvt ptransistor ptransistor_stripes implant1
+ pfetmvt ptransistor ptransistor_stripes implant3
+ pfethvt ptransistor ptransistor_stripes implant2
+ nfetlvt ntransistor ntransistor_stripes implant1
+ nsonos ntransistor implant3
+ varhvt polysilicon ndiff_in_nwell implant2
+ nnfet ntransistor ndiff_in_nwell
+
+ mvndiff ndiffusion hvndiff_mask
+ mvpdiff pdiffusion hvpdiff_mask
+ mvnsd ndiff_in_nwell hvndiff_mask
+ mvpsd pdiff_in_pwell hvpdiff_mask
+ mvnfet ntransistor ntransistor_stripes hvndiff_mask
+ mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
+ mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
+ mvpfet ptransistor ptransistor_stripes
+ mvpfetesd ptransistor ptransistor_stripes
+ mvvar polysilicon ndiff_in_nwell hvndiff_mask
+ mvndc ndiffusion metal1 contact_X'es hvndiff_mask
+ mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
+ mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
+ mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
+
+ poly polysilicon
+ polyfill polysilicon
+ pc polysilicon metal1 contact_X'es
+ npolyres polysilicon silicide_block nselect2
+ ppolyres polysilicon silicide_block pselect2
+ xpc polysilicon pselect2 metal1 contact_X'es
+ rmp polysilicon poly_resist_stripes
+
+ res0p35 implant1
+ res0p69 implant1
+ res1p41 implant1
+ res2p85 implant1
+ res5p73 implant1
+ pnp0p68 implant1
+ pnp3p40 implant1
+ npn1p00 implant1
+ npn2p00 implant1
+ npn11p0 implant1
+
+ pdiode pdiffusion pselect2
+ ndiode ndiffusion nselect2
+ pdiodec pdiffusion pselect2 metal1 contact_X'es
+ ndiodec ndiffusion nselect2 metal1 contact_X'es
+
+ nndiode ndiffusion nselect2 implant3
+ ndiodelvt ndiffusion nselect2 implant1
+ pdiodelvt pdiffusion pselect2 implant1
+ pdiodehvt pdiffusion pselect2 implant2
+ pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
+ pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
+ ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
+
+ mvpdiode pdiffusion pselect2 hvpdiff_mask
+ mvndiode ndiffusion nselect2 hvndiff_mask
+ mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
+ mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
+ nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+ locali metal1
+ lifill metal1
+ coreli metal1
+ rli metal1 poly_resist_stripes
+ mcon metal1 metal2 via1arrow
+ obsli metal1
+ obsmcon metal1 metal2 via1arrow
+
+ metal1 metal2
+ m1fill metal2
+ rm1 metal2 poly_resist_stripes
+ obsm1 metal2
+ m2c metal2 metal3 via2arrow
+ metal2 metal3
+ m2fill metal3
+ rm2 metal3 poly_resist_stripes
+ obsm2 metal3
+ m3c metal3 metal4 via3alt
+ metal3 metal4
+ m3fill metal4
+ rm3 metal4 poly_resist_stripes
+ obsm3 metal4
+ mimcap metal3 mems
+ mimcc metal3 contact_X'es mems
+ mimcap2 metal4 mems
+ mim2cc metal4 contact_X'es mems
+ via3 metal4 metal5 via4
+ metal4 metal5
+ m4fill metal5
+ rm4 metal5 poly_resist_stripes
+ obsm4 metal5
+ via4 metal5 metal6 via5
+ metal5 metal6
+ m5fill metal6
+ rm5 metal6 poly_resist_stripes
+ obsm5 metal6
+ mrdlc metal6 metal7 via6
+ metalrdl metal7
+ obsmrdl metal7
+ ubm metal8
+ pi2 metal7 metal8 via7
+
+ glass overglass
+ mrp1 poly_resist poly_resist_stripes
+ xhrpoly poly_resist silicide_block
+ uhrpoly poly_resist
+ ndiffres ndiffusion ndop_stripes
+ pdiffres pdiffusion pdop_stripes
+ mvndiffres ndiffusion hvndiff_mask ndop_stripes
+ mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
+ comment comment
+ error_p error_waffle
+ error_s error_waffle
+ error_ps error_waffle
+ fillblock cwell
+ fillblock4 cwell
+
+ obswell cwell
+ obsactive implant4
+
+ padl metal6 via6 overglass
+
+ magnet substrate_field_implant
+ rotate via3alt
+ fence via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+ compose nfet poly ndiff
+ compose pfet poly pdiff
+ compose var poly nsd
+
+ compose mvnfet poly mvndiff
+ compose mvpfet poly mvpdiff
+ compose mvvar poly mvnsd
+
+ paint obsmcon locali via1
+ paint obsmcon obsm1 obsli,obsm1
+
+ paint ndc nwell pdc
+ paint nfet nwell pfet
+ paint scnfet nwell scpfet
+ paint ndiff nwell pdiff
+ paint psd nwell nsd
+ paint psc nwell nsc
+ paint npd nwell ppu
+
+ paint pdc pwell ndc
+ paint pfet pwell nfet
+ paint scpfet pwell scnfet
+ paint pdiff pwell ndiff
+ paint nsd pwell psd
+ paint nsc pwell psc
+ paint ppu pwell npd
+
+ paint pdc coreli pdc
+ paint ndc coreli ndc
+ paint pc coreli pc
+ paint nsc coreli nsc
+ paint psc coreli psc
+ paint viali coreli viali
+
+ paint coreli pdc pdc
+ paint coreli ndc ndc
+ paint coreli pc pc
+ paint coreli nsc nsc
+ paint coreli psc psc
+ paint coreli viali viali
+
+ paint m4 obsm4 m4
+ paint m5 obsm5 m5
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+ *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
+ pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
+ *li,coreli,lifill *li,coreli,lifill
+ *m1,m1fill,obsmcon *m1,m1fill,obsmcon
+ *m2,m2fill *m2,m2fill
+ *m3,m3fill *m3,m3fill
+ *m4,m4fill *m4,m4fill
+ *m5,m5fill *m5,m5fill
+ *mimcap *mimcap
+ *mimcap2 *mimcap2
+ allnactivenonfet allnactivenonfet
+ allpactivenonfet allpactivenonfet
+ *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
+ # RDL connects to m5 (i.e., padl) through glass cut
+ *mrdl *mrdl
+ glass metrdl
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE: All values in this section MUST be multiples of 25
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#----------------------------------------------------------------
+style gdsii
+# NOTE: This section is used for actual GDS output
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Create a temp layer from the cell bounding box for use in
+# generating ID layers. Note that "boundary", unlike "bbox",
+# requires the FIXED_BBOX property (abutment box) in the cell.
+#----------------------------------------------------------------
+ templayer CELLBOUND
+ boundary
+
+#----------------------------------------------------------------
+# BOUND
+#----------------------------------------------------------------
+ layer BOUND CELLBOUND
+ calma 235 4
+
+#----------------------------------------------------------------
+# DNWELL
+#----------------------------------------------------------------
+
+ layer DNWELL dnwell,npn
+ calma 64 18
+
+ layer PWRES rpw
+ and dnwell
+ calma 64 13
+
+#----------------------------------------------------------------
+# NWELL
+#----------------------------------------------------------------
+
+ layer NWELL allnwell
+ bloat-all rpw dnwell
+ and-not rpw,pwell
+ calma 64 20
+
+ layer WELLTXT
+ labels allnwell noport
+ calma 64 5
+
+ layer WELLPIN
+ labels allnwell port
+ calma 64 16
+
+#----------------------------------------------------------------
+# SUB (text/port only)
+#----------------------------------------------------------------
+
+ layer SUBTXT
+ labels pwell noport
+ calma 64 59
+
+ layer SUBPIN
+ labels pwell port
+ calma 122 16
+
+#----------------------------------------------------------------
+# DIFF
+#----------------------------------------------------------------
+
+ layer DIFF allnactivenontap,allpactivenontap,allactiveres
+ calma 65 20
+
+ layer DIFFTXT
+ labels allnactivenontap,allpactivenontap noport
+ calma 65 6
+
+ layer DIFFPIN
+ labels allnactivenontap,allpactivenontap port
+ calma 65 16
+
+#----------------------------------------------------------------
+# TAP
+#----------------------------------------------------------------
+
+ layer TAP allnactivetap,allpactivetap
+ labels allnactivetap,allpactivetap port
+ calma 65 44
+
+ layer TAPTXT
+ labels allnactivetap,allpactivetap noport
+ calma 65 5
+
+#----------------------------------------------------------------
+# FOM
+#----------------------------------------------------------------
+
+ layer FOMFILL fomfill
+ labels fomfill
+ calma 23 28
+
+#----------------------------------------------------------------
+# PSDM, NSDM (PPLUS, NPLUS implants)
+#----------------------------------------------------------------
+
+ templayer basePSDM pdiffres,mvpdiffres
+ grow 15
+ or xhrpoly,uhrpoly,xpc
+ grow 110
+ bloat-or allpactivetap * 125 allnactivenontap 0
+ bloat-or allpactivenontap * 125 allnactivetap 0
+
+ templayer baseNSDM ndiffres,mvndiffres
+ grow 125
+ bloat-or allnactivetap * 125 allpactivenontap 0
+ bloat-or allnactivenontap * 125 allpactivetap 0
+
+ templayer extendPSDM basePSDM
+ bridge 380 380
+ and-not baseNSDM
+
+ layer PSDM basePSDM,extendPSDM
+ grow 185
+ shrink 185
+ close 265000
+ mask-hints PSDM
+ calma 94 20
+
+ templayer extendNSDM baseNSDM
+ bridge 380 380
+ and-not basePSDM
+
+ layer NSDM baseNSDM,extendNSDM
+ grow 185
+ shrink 185
+ close 265000
+ mask-hints NSDM
+ calma 93 44
+
+#----------------------------------------------------------------
+# LVID
+#----------------------------------------------------------------
+
+ layer LVID nnfet
+ grow 100
+ calma 81 60
+
+#----------------------------------------------------------------
+# LVTN
+#----------------------------------------------------------------
+
+ layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
+ grow 180
+ bridge 380 380
+ grow 185
+ shrink 185
+ close 265000
+ mask-hints LVTN
+ calma 125 44
+
+#----------------------------------------------------------------
+# HVTR
+#----------------------------------------------------------------
+
+ layer HVTR pfetmvt
+ grow 180
+ bridge 380 380
+ grow 185
+ shrink 185
+ close 265000
+ calma 18 20
+
+#----------------------------------------------------------------
+# HVTP
+#----------------------------------------------------------------
+
+ layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
+ grow 180
+ bridge 380 380
+ grow 185
+ shrink 185
+ close 265000
+ mask-hints HVTP
+ calma 78 44
+
+#----------------------------------------------------------------
+# SONOS
+#----------------------------------------------------------------
+
+ layer SONOS nsonos
+ grow 100
+ grow-min 410
+ bridge 500 410
+ grow 250
+ shrink 250
+ calma 80 20
+
+#----------------------------------------------------------------
+# SONOS requires COREID around area (areaid.ce). Also, the
+# coreli layer indicates a cell needing COREID. Also, devices
+# npd, npass, and ppu indicate a COREID cell.
+#----------------------------------------------------------------
+
+ layer COREID
+ bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
+ mask-hints COREID
+ calma 81 2
+
+#----------------------------------------------------------------
+# STDCELL applies to all cells containing scnfet or scpfet.
+#----------------------------------------------------------------
+
+ layer STDCELL scnfet
+ bloat-all scpfet,scpfethvt,scnfet CELLBOUND
+ mask-hints STDCELL
+ calma 81 4
+
+#----------------------------------------------------------------
+# ESDID is a marker layer for ESD devices in the padframe I/O.
+#----------------------------------------------------------------
+
+ layer ESDID
+ bloat-all mvnfetesd *mvndiff,*poly
+ bloat-all mvpfetesd *mvpdiff,*poly
+ grow 100
+ mask-hints ESDID
+ calma 81 19
+
+#----------------------------------------------------------------
+# NPNID and PNPID apply to bipolar transistors
+#----------------------------------------------------------------
+
+ layer NPNID
+ bloat-all npn dnwell
+ mask-hints NPNID
+ calma 82 20
+
+ templayer pnparea pnp
+ grow 400
+
+ layer PNPID
+ bloat-all pnparea *psd
+ or pnparea
+ mask-hints PNPID
+ calma 82 44
+
+#----------------------------------------------------------------
+# RPM
+#----------------------------------------------------------------
+
+ layer RPM
+ bloat-all xhrpoly xpc
+ grow 200
+ grow-min 1270
+ grow 420
+ shrink 420
+ calma 86 20
+
+#----------------------------------------------------------------
+# URPM (2kOhms/sq. poly implant)
+#----------------------------------------------------------------
+
+ layer URPM
+ bloat-all uhrpoly xpc
+ grow 200
+ grow-min 1270
+ grow 420
+ shrink 420
+ calma 79 20
+
+#----------------------------------------------------------------
+# LDNTM (Tip implant for SONOS FETs)
+#----------------------------------------------------------------
+
+ layer LDNTM
+ bloat-all nsonos *ndiff
+ grow 185
+ grow 345
+ shrink 345
+ calma 11 44
+
+#----------------------------------------------------------------
+# HVNTM (Tip implant for MV ndiff devices)
+#----------------------------------------------------------------
+
+ templayer hvntm_block *mvpsd
+ grow 185
+
+ layer HVNTM
+ bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+ bloat-all mvvaractor *mvnsd
+ and-not hvntm_block
+ grow 185
+ grow 345
+ shrink 345
+ and-not hvntm_block
+ calma 125 20
+
+#----------------------------------------------------------------
+# POLY
+#----------------------------------------------------------------
+
+ layer POLY allpoly
+ calma 66 20
+
+ layer POLYTXT
+ labels allpoly noport
+ calma 66 5
+
+ layer POLYPIN
+ labels allpoly port
+ calma 66 16
+
+ layer POLYFILL polyfill
+ labels polyfill
+ calma 28 28
+
+#----------------------------------------------------------------
+# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
+#----------------------------------------------------------------
+
+ templayer thkox_area alldiffmv,mvvar
+ grow 185
+ bloat-all alldiffmv nwell
+ grow 345
+ shrink 345
+
+ templayer large_ptap_mv thkox_area
+ shrink 420
+ grow 420
+
+ templayer small_ptap_mv thkox_area
+ and-not large_ptap_mv
+ # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
+ grow-min 840
+
+ layer HVI thkox_area,small_ptap_mv
+ bridge 700 600
+ grow 345
+ shrink 345
+ mask-hints HVI
+ calma 75 20
+
+#----------------------------------------------------------------
+# CONT (LICON)
+#----------------------------------------------------------------
+
+ layer CONT allcont
+ squares-grid 0 170 170
+ calma 66 44
+
+ # Contact for pres is different than other LICON contacts
+ # See rules LICON 1b, 1c (width/length) and 2b (spacing)
+ templayer xpc_horiz xpc
+ shrink 1007
+ grow 1007
+
+ layer CONT xpc
+ and-not xpc_horiz
+ # Force long edge vertical for contacts narrower than 2um
+ # Minimum space is 350 but 520 satisfies no. of contacts rule
+ slots 80 190 520 80 2000 350
+ calma 66 44
+
+ layer CONT xpc
+ and xpc_horiz
+ # Force long edge vertical for contacts wider than 2um
+ # Minimum space is 350 but 520 satisfies no. of contacts rule
+ slots 80 2000 350 80 190 520
+ calma 66 44
+
+#----------------------------------------------------------------
+# NPC (Nitride poly cut)
+# surrounds CONT (LICON) on poly only (i.e., pc)
+#----------------------------------------------------------------
+
+ # Avoids a common case of NPC bridges too close to other LICON shapes.
+ templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
+ grow 90
+
+ layer NPC pc
+ squares-grid 0 170 170
+ grow 100
+ bridge 270 270
+ and-not diffcutarea
+ bridge 270 270
+ grow 130
+ shrink 130
+ mask-hints NPC
+ calma 95 20
+
+ # NPC is also generated on xhrpoly and uhrpoly resistors
+
+ layer NPC xpc,xhrpoly,uhrpoly
+ # xpc surrounds precision_resistor by 0.095um
+ grow 95
+ grow 130
+ shrink 130
+ calma 95 20
+
+#----------------------------------------------------------------
+# Device markers
+#----------------------------------------------------------------
+
+ layer DIFFRES rdn,mvrdn,rdp,mvrdp
+ calma 65 13
+
+ layer POLYRES mrp1
+ calma 66 13
+
+ # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
+ layer POLYSHORT rmp
+ calma 66 15
+
+ # POLYRES extends to edge of contact cut
+ layer POLYRES xhrpoly,uhrpoly
+ grow 60
+ and xpc
+ or xhrpoly,uhrpoly
+ calma 66 13
+
+ layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
+ # To be done: Expand to include anode, cathode, and guard ring
+ calma 81 23
+
+#----------------------------------------------------------------
+# LI
+#----------------------------------------------------------------
+ layer LI allli
+ calma 67 20
+
+ layer LITXT
+ labels *locali,coreli noport
+ calma 67 5
+
+ layer LIPIN
+ labels *locali,coreli port
+ calma 67 16
+
+ layer LIRES rli
+ labels rli
+ calma 67 13
+
+ layer LIFILL lifill
+ labels lifill
+ calma 56 28
+
+#----------------------------------------------------------------
+# MCON
+#----------------------------------------------------------------
+ layer MCON mcon
+ squares-grid 0 170 190
+ calma 67 44
+
+#----------------------------------------------------------------
+# MET1
+#----------------------------------------------------------------
+ layer MET1 allm1
+ calma 68 20
+
+ layer MET1TXT
+ labels allm1 noport
+ calma 68 5
+
+ layer MET1PIN
+ labels allm1 port
+ calma 68 16
+
+ layer MET1RES rm1
+ labels rm1
+ calma 68 13
+
+ layer MET1FILL m1fill
+ labels m1fill
+ calma 36 28
+
+#----------------------------------------------------------------
+# VIA1
+#----------------------------------------------------------------
+ layer VIA1 via1
+ squares-grid 55 150 170
+ calma 68 44
+
+#----------------------------------------------------------------
+# MET2
+#----------------------------------------------------------------
+ layer MET2 allm2
+ calma 69 20
+
+ layer MET2TXT
+ labels allm2 noport
+ calma 69 5
+
+ layer MET2PIN
+ labels allm2 port
+ calma 69 16
+
+ layer MET2RES rm2
+ labels rm2
+ calma 69 13
+
+ layer MET2FILL m2fill
+ labels m2fill
+ calma 41 28
+
+#----------------------------------------------------------------
+# VIA2
+#----------------------------------------------------------------
+ layer VIA2 via2
+ squares-grid 40 200 200
+ calma 69 44
+
+#----------------------------------------------------------------
+# MET3
+#----------------------------------------------------------------
+ layer MET3 allm3
+ calma 70 20
+
+ layer MET3TXT
+ labels allm3 noport
+ calma 70 5
+
+ layer MET3PIN
+ labels allm3 port
+ calma 70 16
+
+ layer MET3RES rm3
+ labels rm3
+ calma 70 13
+
+ layer MET3FILL m3fill
+ labels m3fill
+ calma 34 28
+
+#----------------------------------------------------------------
+# VIA3
+#----------------------------------------------------------------
+ layer VIA3 via3
+ or mimcc
+ squares-grid 60 200 200
+ calma 70 44
+
+#----------------------------------------------------------------
+# MET4
+#----------------------------------------------------------------
+ layer MET4 allm4
+ calma 71 20
+
+ layer MET4TXT
+ labels allm4 noport
+ calma 71 5
+
+ layer MET4PIN
+ labels allm4 port
+ calma 71 16
+
+ layer MET4RES rm4
+ labels rm4
+ calma 71 13
+
+ layer MET4FILL m4fill
+ labels m4fill
+ calma 51 28
+
+#----------------------------------------------------------------
+# VIA4
+#----------------------------------------------------------------
+ layer VIA4 via4
+ or mim2cc
+ squares-grid 190 800 800
+ calma 71 44
+
+#----------------------------------------------------------------
+# MET5
+#----------------------------------------------------------------
+ layer MET5 allm5,m5fill
+ calma 72 20
+
+ layer MET5TXT
+ labels allm5 noport
+ calma 72 5
+
+ layer MET5PIN
+ labels allm5 port
+ calma 72 16
+
+ layer MET5RES rm5
+ labels rm5
+ calma 72 13
+
+ layer MET5FILL m5fill
+ labels m5fill
+ calma 59 28
+
+
+#----------------------------------------------------------------
+# RDL
+#----------------------------------------------------------------
+ layer RDL *metrdl
+ calma 74 20
+
+ layer RDLTXT
+ labels *metrdl noport
+ calma 74 5
+
+ layer RDLPIN
+ labels *metrdl port
+ calma 74 16
+
+ layer PI1 *metrdl
+ and padl,glass
+ # Test only---needs GDS layer number
+
+ layer UBM *metrdl
+ shrink 50000
+ grow 40000
+ # Test only---needs GDS layer number
+
+ layer PI2 *metrdl
+ shrink 50000
+ grow 25000
+ # Test only---needs GDS layer number
+
+
+#----------------------------------------------------------------
+# GLASS
+#----------------------------------------------------------------
+ layer GLASS glass
+ calma 76 20
+
+#----------------------------------------------------------------
+# CAPM
+#----------------------------------------------------------------
+ layer CAPM *mimcap
+ labels mimcap
+ calma 89 44
+
+ layer CAPM2 *mimcap2
+ labels mimcap2
+ calma 97 44
+
+#----------------------------------------------------------------
+# Chip top level marker for DRC latchup rules to check 15um
+# distance to taps (otherwise 6um is used)
+#----------------------------------------------------------------
+
+ layer LOWTAPDENSITY
+ bbox top
+ # Clear 200um for pads + 50um for required high tap density
+ # in critical area.
+ shrink 250000
+ calma 81 14
+
+#----------------------------------------------------------------
+# FILLBLOCK
+#----------------------------------------------------------------
+ layer FILLOBSFOM obsactive
+ calma 22 24
+
+ layer FILLOBSM1 fillblock,fillblock4
+ calma 62 24
+
+ layer FILLOBSM2 fillblock,fillblock4
+ calma 105 52
+
+ layer FILLOBSM3 fillblock,fillblock4
+ calma 107 24
+
+ layer FILLOBSM4 fillblock,fillblock4
+ calma 112 4
+
+ render DNWELL cwell -0.1 0.1
+ render NWELL nwell 0.0 0.2062
+ render DIFF ndiffusion 0.2062 0.12
+ render TAP pdiffusion 0.2062 0.12
+ render POLY polysilicon 0.3262 0.18
+ render CONT via 0.5062 0.43
+ render LI metal1 0.9361 0.10
+ render MCON via 1.0361 0.34
+ render MET1 metal2 1.3761 0.36
+ render VIA1 via 1.7361 0.27
+ render MET2 metal3 2.0061 0.36
+ render VIA2 via 2.3661 0.42
+ render MET3 metal4 2.7861 0.845
+ render VIA3 via 3.6311 0.39
+ render MET4 metal5 4.0211 0.845
+ render VIA4 via 4.8661 0.505
+ render MET5 metal6 5.3711 1.26
+ render CAPM metal8 2.4661 0.2
+ render CAPM2 metal9 3.7311 0.2
+ render RDL metal7 11.8834 4.0
+
+#----------------------------------------------------------------
+style drc
+#----------------------------------------------------------------
+# NOTE: This style is used for DRC only, not for GDS output
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+
+ # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
+ templayer dnwell_shrink dnwell
+ shrink 1030
+
+ templayer nwell_missing dnwell
+ grow 400
+ and-not dnwell_shrink
+ and-not nwell
+
+ templayer pwell_in_dnwell dnwell
+ and-not nwell
+
+ # SONOS nFET devices must be in deep nwell
+ templayer dnwell_missing nsonos
+ and-not dnwell
+
+ # SONOS nFET devices must be in cell with abutment box
+ templayer abutment_box
+ boundary
+
+ templayer bbox_missing nsonos
+ and-not abutment_box
+
+ # Make sure nwell covers varactor poly
+ templayer var_poly_no_nwell
+ bloat-all varactor,mvvaractor *poly
+ grow 150
+ and-not nwell
+
+ # Define MiM cap bottom plate for spacing rule
+ templayer mim_bottom
+ bloat-all *mimcap *metal3
+
+ # Define MiM2 cap bottom plate for spacing rule
+ templayer mim2_bottom
+ bloat-all *mimcap2 *metal4
+
+ # Define areas where mim2cc is inside the boundary of mimcc
+ # by more than the contact surround
+ templayer mim2_contact_overlap
+ bloat-all *mimcap2 mimcc
+ shrink 60
+ and-not *mimcap2
+
+ # Note that metal fill is performed by the foundry and so is not
+ # an option for a cifoutput style.
+
+ # Check latchup rule (15um minimum from tap LICON center to any
+ # non-tap diffusion. Note that to count as a tap, the diffusion
+ # must be contacted to LI
+
+ templayer ptap_reach psc,mvpsc
+ and-not dnwell
+ # grow total is 15um. grow in 0.84um increments to ensure that
+ # no nwell ring is crossed
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 635
+ and-not nwell,dnwell
+
+ templayer ptap_missing *ndiff,*mvndiff
+ and-not dnwell
+ and-not ptap_reach
+
+ templayer ntap_reach nsc,mvnsc
+ # grow total is 15um. grow in 1.27um increments to ensure that
+ # no nwell ring is crossed. There is no difference between
+ # ntaps in and out of deep nwell.
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 945
+ and nwell,pnp
+
+ templayer ntap_missing *pdiff,*mvpdiff
+ and-not pwell_in_dnwell
+ and-not ntap_reach
+
+ templayer dptap_reach psc,mvpsc
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 635
+ and-not nwell
+ and dnwell
+
+ templayer dptap_missing *ndiff,*mvndiff
+ and dnwell
+ and-not dptap_reach
+
+ templayer pdiff_crosses_dnwell dnwell
+ grow 20
+ and-not dnwell
+ and allpdifflv,allpdiffmv
+
+ # MV nwell must be 2um from any other nwell
+ templayer mvnwell
+ bloat-all alldiffmv nwell
+ grow-min 840
+ bridge 700 600
+
+ # Simple spacing checks to lvnwell must use CIF-DRC rule
+ # Note that HVI may *abut* lvnwell; this can only be handled
+ # with mask-hints layers.
+
+ templayer drawn_hvi
+ mask-hints HVI
+
+ templayer allmvdiffnowell *mvndiff,*mvpsd
+ and-not drawn_hvi
+
+ templayer nwell_or_hvi nwell,drawn_hvi
+
+ templayer lvnwell nwell
+ and-not mvnwell
+
+ templayer nwell_with_tap
+ bloat-all nsc,mvnsc nwell,pnp
+
+ templayer nwell_missing_tap nwell,pnp
+ and-not nwell_with_tap
+
+ templayer tap_with_licon
+ bloat-all psc,mvpsc psd,mvpsd
+ bloat-all nsc,mvnsc nsd,mvnsd
+
+ templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
+ and-not tap_with_licon
+
+ # Make sure varactor nwell contains no P diffusion
+ templayer pdiff_in_varactor_well
+ bloat-all varactor,mvvaractor nwell
+ and allpactive
+
+ # HVNTM spacing requires recreating HVNTM
+ templayer hvntm_block *mvpsd
+ grow 185
+
+ templayer hvntm_generate
+ bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+ bloat-all mvvaractor *mvnsd
+ and-not hvntm_block
+ grow 185
+ grow 345
+ shrink 345
+ and-not hvntm_block
+
+ # RPM spacing checks require recreating RPM
+ templayer rpm_generate
+ bloat-all xhrpoly,uhrpoly xpc
+ grow 200
+ grow-min 1270
+ grow 420
+ shrink 420
+
+ # Check distance RPM to NSDM
+ templayer rpm_nsd_check rpm_generate
+ grow 325
+ and allndifflv,allndiffmv
+
+ # Check distance RPM to (unrelated) POLY
+ templayer rpm_poly_check rpm_generate
+ grow 200
+ and-not xhrpoly,uhrpoly,xpc
+ and allpoly
+
+ # Check distance RPM to HVNTM
+ templayer rpm_hvntm_check rpm_generate
+ grow 385
+ and allndiffmvnontap
+
+ templayer m1_small_hole allm1,obsm1,obsmcon
+ close 140000
+
+ templayer m1_hole_empty m1_small_hole
+ and-not allm1,obsm1,obsmcon
+
+ templayer m2_small_hole allm2,obsm2
+ close 140000
+
+ templayer m2_hole_empty m2_small_hole
+ and-not allm2,obsm2
+
+ templayer m1_huge allm1
+ shrink 1500
+ grow 1500
+
+ templayer m1_large_halo m1_huge
+ grow 280
+ and-not m1_huge
+ and allm1
+
+ templayer m2_huge allm2
+ shrink 1500
+ grow 1500
+
+ templayer m2_large_halo m2_huge
+ grow 280
+ and-not m2_huge
+ and allm2
+
+ templayer m3_huge allm3
+ shrink 1500
+ grow 1500
+
+ templayer m3_large_halo m3_huge
+ grow 400
+ and-not m3_huge
+ and allm3
+
+ templayer m4_huge allm4
+ shrink 1500
+ grow 1500
+
+ templayer m4_large_halo m4_huge
+ grow 400
+ and-not m4_huge
+ and allm4
+
+
+#----------------------------------------------------------------
+style density
+#----------------------------------------------------------------
+# Style used by scripts to check for fill density
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+ templayer fom_all alldiff,fomfill
+
+ templayer poly_all allpoly,polyfill
+
+ templayer li_all allli,lifill
+
+ templayer m1_all allm1,m1fill
+
+ templayer m2_all allm2,m2fill
+
+ templayer m3_all allm3,m3fill
+
+ templayer m4_all allm4,m4fill
+
+ templayer m5_all allm5,m5fill
+
+#----------------------------------------------------------------
+style wafflefill variants (),(tiled)
+#----------------------------------------------------------------
+# Style used by scripts for automatically generating fill layers
+# NOTE: Be sure to generate output on flattened layout.
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Generate and retain a layer representing the bounding box.
+#
+# For variant ():
+# The bounding box is the full extent of geometry on the top level
+# cell.
+#
+# For variant (tiled):
+# Use with a script that breaks layout into flattened tiles and runs
+# fill individually on each. The tiles should be larger than the
+# step size, and each should draw a layer "comment" the size of the
+# step box.
+#----------------------------------------------------------------
+
+ variants ()
+ templayer topbox
+ bbox top
+
+ variants (tiled)
+ templayer topbox comment
+ # Each tile imposes the full keepout distance rule of
+ # 3um on all sides.
+ shrink 1500
+
+ variants *
+
+#----------------------------------------------------------------
+# Generate guard-band around nwells to keep FOM from crossing
+# Spacing from LV nwell = Diff/Tap 9 = 0.34um
+# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
+# Enclosure by nwell = Diff/Tap 8 = 0.18um
+#----------------------------------------------------------------
+
+ templayer mvnwell
+ bloat-all alldiffmv nwell
+
+ templayer lvnwell allnwell
+ and-not mvnwell
+
+ templayer well_shrink mvnwell
+ shrink 250
+ or lvnwell
+ shrink 180
+ templayer well_guardband allnwell
+ grow 340
+ and-not well_shrink
+
+#---------------------------------------------------
+# Diffusion and poly keep-out areas
+#---------------------------------------------------
+ templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
+ or rpw,pnp,npn
+ grow 500
+ or well_guardband
+
+ templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
+ or rpw,pnp,npn
+ grow 1000
+
+#---------------------------------------------------
+# FOM and POLY fill
+#---------------------------------------------------
+ templayer fomfill_pass1 topbox
+ # slots 0 4080 1320 0 4080 1320 1360 0
+ slots 0 4080 1600 0 4080 1600 1360 0
+ and-not obstruct_fom
+ and topbox
+ shrink 2035
+ grow 2035
+
+#---------------------------------------------------
+
+ templayer obstruct_poly_pass1 fomfill_pass1
+ grow 300
+ or obstruct_poly
+ templayer polyfill_pass1 topbox
+ slots 0 720 360 0 720 360 240 0
+ and-not obstruct_poly_pass1
+ and topbox
+ shrink 355
+ grow 355
+
+#---------------------------------------------------
+
+ templayer obstruct_fom_pass2 fomfill_pass1
+ grow 1290
+ or polyfill_pass1
+ grow 300
+ or obstruct_fom
+ templayer fomfill_pass2 topbox
+ slots 0 2500 1320 0 2500 1320 1360 0
+ and-not obstruct_fom_pass2
+ and topbox
+ shrink 1245
+ grow 1245
+
+#---------------------------------------------------
+
+ templayer obstruct_poly_coarse polyfill_pass1
+ grow 60
+ or fomfill_pass1,fomfill_pass2
+ grow 300
+ or obstruct_poly
+ templayer polyfill_coarse topbox
+ slots 0 720 360 0 720 360 240 120
+ and-not obstruct_poly_coarse
+ and topbox
+ shrink 355
+ grow 355
+
+#---------------------------------------------------
+ templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
+ grow 60
+ or fomfill_pass1,fomfill_pass2
+ grow 300
+ or obstruct_poly
+ templayer polyfill_medium topbox
+ slots 0 540 360 0 540 360 240 100
+ and-not obstruct_poly_medium
+ and topbox
+ shrink 265
+ grow 265
+
+#---------------------------------------------------
+ templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
+ grow 60
+ or fomfill_pass1,fomfill_pass2
+ grow 300
+ or obstruct_poly
+ templayer polyfill_fine topbox
+ slots 0 480 360 0 480 360 240 200
+ and-not obstruct_poly_fine
+ and topbox
+ shrink 235
+ grow 235
+
+#---------------------------------------------------
+
+ templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
+ grow 1290
+ or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
+ grow 300
+ or obstruct_fom
+ templayer fomfill_coarse topbox
+ slots 0 1500 1320 0 1500 1320 1360 0
+ and-not obstruct_fom_coarse
+ and topbox
+ shrink 745
+ grow 745
+
+#---------------------------------------------------
+
+ templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
+ grow 1290
+ or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
+ grow 300
+ or obstruct_fom
+ templayer fomfill_fine topbox
+ slots 0 500 400 0 500 400 160 0
+ and-not obstruct_fom_fine
+ and topbox
+ shrink 245
+ grow 245
+
+#---------------------------------------------------
+ layer FOMFILL fomfill_pass1
+ or fomfill_pass2
+ or fomfill_coarse
+ or fomfill_fine
+ calma 23 28
+
+ layer POLYFILL polyfill_pass1
+ or polyfill_coarse
+ or polyfill_medium
+ or polyfill_fine
+ calma 28 28
+
+#---------------------------------------------------------
+# LI fill
+# Note requirement that LI fill may not overlap (non-fill)
+# diff or poly.
+#---------------------------------------------------------
+
+ templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
+ grow 2800
+ or alldiff,allpoly
+ grow 200
+ templayer lifill_coarse topbox
+ # slots 0 3000 650 0 3000 650 700 0
+ slots 0 3000 900 0 3000 900 700 0
+ and-not obstruct_li_coarse
+ and topbox
+ shrink 1495
+ grow 1495
+
+ templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
+ grow 2500
+ or lifill_coarse
+ grow 300
+ or alldiff,allpoly
+ grow 200
+ templayer lifill_medium topbox
+ slots 0 1500 500 0 1500 500 700 0
+ and-not obstruct_li_medium
+ and topbox
+ shrink 745
+ grow 745
+
+ templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
+ or lifill_coarse,lifill_medium
+ grow 300
+ or alldiff,allpoly
+ grow 200
+ templayer lifill_fine topbox
+ slots 0 580 500 0 580 500 700 0
+ and-not obstruct_li_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ layer LIFILL lifill_coarse
+ or lifill_medium
+ or lifill_fine
+ calma 56 28
+
+#---------------------------------------------------
+# MET1 fill
+#---------------------------------------------------
+
+ templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+ grow 3000
+ templayer met1fill_coarse topbox
+ # slots 0 2000 200 0 2000 200 700 0
+ slots 0 2000 800 0 2000 800 700 350
+ and-not obstruct_m1_coarse
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+ grow 2800
+ or met1fill_coarse
+ grow 200
+ templayer met1fill_medium topbox
+ slots 0 1000 200 0 1000 200 700 0
+ and-not obstruct_m1_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+ grow 300
+ or met1fill_coarse,met1fill_medium
+ grow 200
+ templayer met1fill_fine topbox
+ slots 0 580 200 0 580 200 700 0
+ and-not obstruct_m1_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+ grow 100
+ or met1fill_coarse,met1fill_medium,met1fill_fine
+ grow 200
+ templayer met1fill_veryfine topbox
+ slots 0 300 200 0 300 200 100 50
+ and-not obstruct_m1_veryfine
+ and topbox
+ shrink 145
+ grow 145
+
+ layer MET1FILL met1fill_coarse
+ or met1fill_medium
+ or met1fill_fine
+ or met1fill_veryfine
+ calma 36 28
+
+#---------------------------------------------------
+# MET2 fill
+#---------------------------------------------------
+ templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+ grow 3000
+ templayer met2fill_coarse topbox
+ # slots 0 2000 200 0 2000 200 700 350
+ slots 0 2000 800 0 2000 800 700 350
+ and-not obstruct_m2
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+ grow 2800
+ or met2fill_coarse
+ grow 200
+ templayer met2fill_medium topbox
+ slots 0 1000 200 0 1000 200 700 350
+ and-not obstruct_m2_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+ grow 300
+ or met2fill_coarse,met2fill_medium
+ grow 200
+ templayer met2fill_fine topbox
+ slots 0 580 200 0 580 200 700 350
+ and-not obstruct_m2_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+ grow 100
+ or met2fill_coarse,met2fill_medium,met2fill_fine
+ grow 200
+ templayer met2fill_veryfine topbox
+ slots 0 300 200 0 300 200 100 100
+ and-not obstruct_m2_veryfine
+ and topbox
+ shrink 145
+ grow 145
+
+ layer MET2FILL met2fill_coarse
+ or met2fill_medium
+ or met2fill_fine
+ or met2fill_veryfine
+ calma 41 28
+
+#---------------------------------------------------
+# MET3 fill
+#---------------------------------------------------
+ templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+ grow 3000
+ templayer met3fill_coarse topbox
+ # slots 0 2000 300 0 2000 300 700 700
+ slots 0 2000 800 0 2000 800 700 350
+ and-not obstruct_m3
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+ grow 2700
+ or met3fill_coarse
+ grow 300
+ templayer met3fill_medium topbox
+ slots 0 1000 300 0 1000 300 700 700
+ and-not obstruct_m3_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+ grow 200
+ or met3fill_coarse,met3fill_medium
+ grow 300
+ templayer met3fill_fine topbox
+ slots 0 580 300 0 580 300 700 700
+ and-not obstruct_m3_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+ # Note: Adding 0.1 to waffle rule to clear wide spacing rule
+ grow 100
+ or met3fill_coarse,met3fill_medium,met3fill_fine
+ grow 300
+ templayer met3fill_veryfine topbox
+ slots 0 400 300 0 400 300 150 200
+ and-not obstruct_m3_veryfine
+ and topbox
+ shrink 195
+ grow 195
+
+ layer MET3FILL met3fill_coarse
+ or met3fill_medium
+ or met3fill_fine
+ or met3fill_veryfine
+ calma 34 28
+
+#---------------------------------------------------
+# MET4 fill
+#---------------------------------------------------
+ templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+ grow 3000
+ templayer met4fill_coarse topbox
+ # slots 0 2000 300 0 2000 300 700 1050
+ slots 0 2000 800 0 2000 800 700 350
+ and-not obstruct_m4
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+ grow 2700
+ or met4fill_coarse
+ grow 300
+ templayer met4fill_medium topbox
+ slots 0 1000 300 0 1000 300 700 1050
+ and-not obstruct_m4_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+ grow 200
+ or met4fill_coarse,met4fill_medium
+ grow 300
+ templayer met4fill_fine topbox
+ slots 0 580 300 0 580 300 700 1050
+ and-not obstruct_m4_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+ # Note: Adding 0.1 to waffle rule to clear wide spacing rule
+ grow 100
+ or met4fill_coarse,met4fill_medium,met4fill_fine
+ grow 300
+ templayer met4fill_veryfine topbox
+ slots 0 400 300 0 400 300 150 300
+ and-not obstruct_m4_veryfine
+ and topbox
+ shrink 195
+ grow 195
+
+ layer MET4FILL met4fill_coarse
+ or met4fill_medium
+ or met4fill_fine
+ or met4fill_veryfine
+ calma 51 28
+
+#---------------------------------------------------
+# MET5 fill
+#---------------------------------------------------
+ templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
+ grow 3000
+ templayer met5fill_coarse topbox
+ slots 0 5000 1600 0 5000 1600 1000 100
+ and-not obstruct_m5
+ and topbox
+ shrink 2495
+ grow 2495
+
+ templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
+ grow 1400
+ or met5fill_coarse
+ grow 1600
+ templayer met5fill_medium topbox
+ slots 0 3000 1600 0 3000 1600 1000 100
+ and-not obstruct_m5_medium
+ and topbox
+ shrink 1495
+ grow 1495
+
+ layer MET5FILL met5fill_coarse
+ or met5fill_medium
+ calma 59 28
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+# NOTE: All values in this section MUST be multiples of 25
+# or else magic will scale below the allowed layout grid size
+#-----------------------------------------------------------------------
+
+style sky130 variants (),(vendor)
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ ignore NPC
+ ignore SEALID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+ ignore FILLOBSPOLY
+ ignore OUTLINE
+
+ layer pnp NWELL,WELLTXT,WELLPIN
+ and PNPID
+ labels NWELL
+ variants (vendor)
+ labels WELLTXT port
+ variants ()
+ labels WELLTXT text
+ variants *
+ labels WELLPIN port
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ and-not PNPID
+ labels NWELL
+ variants (vendor)
+ labels WELLTXT port
+ variants ()
+ labels WELLTXT text
+ variants *
+ labels WELLPIN port
+
+ templayer nwellarea NWELL
+ copyup nwelcheck
+
+ # Copy nwell areas up for diffusion checks
+ templayer xnwelcheck nwelcheck
+ copyup nwelcheck
+
+ templayer hvarea HVI
+ copyup hvcheck
+
+ # Copy high-voltage (HVI) areas up for diffusion checks
+ templayer xhvcheck hvcheck
+ copyup hvcheck
+
+ # Always draw pwell under p-tap and n-diff. This is not always
+ # necessary but works better with deep nwell for correct extraction.
+ layer pwell TAP,DIFF
+ and-not NWELL,nwelcheck
+ grow 130
+ or SUBTXT,SUBPIN
+ grow 420
+ shrink 420
+ variants (vendor)
+ labels SUBTXT port
+ variants ()
+ labels SUBTXT text
+ variants *
+ labels SUBPIN port
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer npn DNWELL
+ and-not NWELL,nwelcheck
+ and NPNID
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and-not NWELL,nwelcheck
+ and-not PSDM
+ and-not DIODE
+ and-not DIFFRES
+ and-not HVI,hvcheck
+ and NSDM
+ and-not CORELI
+ copyup ndifcheck
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and-not NWELL,nwelcheck
+ and-not PSDM
+ and-not DIODE
+ and-not DIFFRES
+ and HVI,hvcheck
+ and NSDM
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF,barediff
+ and NSDM
+ and DIODE
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF,barediff
+ and NSDM
+ and DIODE
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NSDM
+ and-not HVI,hvcheck
+ and-not NWELL,nwelcheck
+ copyup DIODE,NSDM
+
+ layer ndiffres DIFFRES
+ and NSDM
+ and-not HVI,hvcheck
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and NWELL,nwelcheck
+ and-not NSDM
+ and-not DIODE
+ and-not HVI,hvcheck
+ and PSDM
+ copyup pdifcheck
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF,barediff
+ and NSDM
+ and DIODE
+ and HVI,hvcheck
+ and-not POLY
+ and-not PSDM
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF,barediff
+ and NSDM
+ and DIODE
+ and HVI,hvcheck
+ and-not POLY
+ and-not PSDM
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NSDM
+ and HVI,hvcheck
+ and-not NWELL,nwelcheck
+ copyup DIODE,NSDM
+
+ layer mvndiffres DIFFRES
+ and NSDM
+ and HVI,hvcheck
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and NWELL,nwelcheck
+ and-not NSDM
+ and HVI,hvcheck
+ and-not DIODE
+ and-not DIFFRES
+ and PSDM
+ copyup mvpdifcheck
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PSDM
+ and-not HVI,hvcheck
+ copyup DIODE,PSDM
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF,barediff
+ and POLY
+ or baretrans
+ and-not NSDM
+ and-not HVI,hvcheck
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfethvt pfetarea
+ and-not LVTN
+ and HVTP
+ and STDCELL
+ labels DIFF
+
+ layer ppu pfetarea
+ and-not LVTN
+ and HVTP
+ and COREID
+ # Shrink-grow operation eliminates the smaller parasitie device
+ # shrink 70
+ # grow 70
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfetmvt pfetarea
+ and HVTR
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ and-not COREID
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and HVI,hvcheck
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PSDM
+ and HVI,hvcheck
+ copyup DIODE,PSDM
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF,barediff
+ and POLY
+ or baretrans
+ and-not NSDM
+ and HVI,hvcheck
+
+ layer mvpfet mvpfetarea
+ and-not ESDID
+ labels DIFF
+
+ layer mvpfetesd mvpfetarea
+ and ESDID
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+ labels DIFF
+
+ layer nfet DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scnfet DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer npass DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and COREID
+ labels DIFF
+
+ layer npd DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and COREID
+ # Shrink-grow operation eliminates the smaller npass device
+ shrink 70
+ grow 70
+ labels DIFF
+
+ # Devices abutting tap under gate are officially npd, not npass
+ layer npd TAP
+ grow 100
+ and DIFF
+ and POLY
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and COREID
+ labels DIFF
+
+ layer nfetlvt DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and-not CORELI
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels TAP
+
+ layer nsd TAP,TAPTXT
+ and NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ layer corenvar TAP
+ and NSDM
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea TAP
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels TAP
+
+ layer psd TAP
+ and PSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ layer corepvar TAP
+ and PSDM
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not NSDM
+ and-not POLY
+ and HVI,hvcheck
+ and mvpfetexpand
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+ and-not mvrdpioedge
+ labels DIFF
+
+ templayer mvnfetarea DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not LVTN
+ and HVI,hvcheck
+ grow 350
+
+ templayer mvnnfetarea DIFF,TAP,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and LVTN
+ and HVI,hvcheck
+ and-not mvnfetarea
+
+ layer mvnfetesd DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and HVI,hvcheck
+ and ESDID
+ and-not mvnnfetarea
+ labels DIFF
+
+ layer mvnfet DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and HVI,hvcheck
+ and-not ESDID
+ and-not mvnnfetarea
+ labels DIFF
+
+ layer nnfet mvnnfetarea
+ and LVID
+ labels DIFF
+
+ layer mvnnfet mvnnfetarea
+ and-not LVID
+ labels DIFF
+
+ templayer mvnsdarea TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and HVI,hvcheck
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels TAP
+
+ layer mvnsd TAP,TAPTXT
+ and NSDM
+ and HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF,barediff
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not NSDM
+ and HVI,hvcheck
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPTXT
+ and PSDM
+ and HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ and nsdexpand
+
+ layer mvpsd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and HVI,hvcheck
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and HVI,hvcheck
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not HVI,hvcheck
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and HVI,hvcheck
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NSDM
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not HVTP
+ and-not NSDM
+ and STDCELL
+
+ layer scpfethvt POLY
+ and DIFF
+ and diffresarea
+ and HVTP
+ and-not NSDM
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY,POLYTXT,POLYPIN
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not TAP
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea
+ labels POLY
+ variants (vendor)
+ labels POLYTXT port
+ variants ()
+ labels POLYTXT text
+ variants *
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PSDM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and NSDM
+ and-not NWELL,nwelcheck
+ and-not HVI,hvcheck
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF,TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and pfetexpand
+ and-not HVI,hvcheck
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF,TAP
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not pfetexpand
+ and-not HVI,hvcheck
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ or barecont
+ and LI
+ or licont
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and NSDM
+ and-not NWELL,nwelcheck
+ and HVI,hvcheck
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF,TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and mvpfetexpand
+ and MET1
+ and HVI,hvcheck
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF,TAP
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not mvpfetexpand
+ and HVI,hvcheck
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and-not LVTN
+ and HVI,hvcheck
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and LVTN
+ and HVI,hvcheck
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ or barecont
+ and LI
+ or licont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and HVI,hvcheck
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer fomfill FOMFILL
+ labels FOMFILL
+
+ layer polyfill POLYFILL
+ labels POLYFILL
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ variants (vendor)
+ labels LITXT port
+ variants ()
+ labels LITXT text
+ variants *
+ labels LIPIN port
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ variants (vendor)
+ labels LITXT port
+ variants ()
+ labels LITXT text
+ variants *
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer lifill LIFILL
+ labels LIFILL
+
+ layer mcon MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ variants (vendor)
+ labels MET1TXT port
+ variants ()
+ labels MET1TXT text
+ variants *
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+ layer m1fill MET1FILL
+ labels MET1FILL
+
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+
+ templayer m2cbase VIA1
+ and-not COREID
+ grow 5
+ or VIA1
+ grow 50
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ variants (vendor)
+ labels MET2TXT port
+ variants ()
+ labels MET2TXT text
+ variants *
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ layer m2fill MET2FILL
+ labels MET2FILL
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+ labels MET3
+ variants (vendor)
+ labels MET3TXT port
+ variants ()
+ labels MET3TXT text
+ variants *
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+ layer m3fill MET3FILL
+ labels MET3FILL
+
+
+ templayer via3base VIA3
+ and-not CAPM
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+ labels MET4
+ variants (vendor)
+ labels MET4TXT port
+ variants ()
+ labels MET4TXT text
+ variants *
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m4fill MET4FILL
+ labels MET4FILL
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ variants (vendor)
+ labels MET5TXT port
+ variants ()
+ labels MET5TXT text
+ variants *
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ layer m5fill MET5FILL
+ labels MET5FILL
+
+ templayer via4base VIA4
+ and-not CAPM2
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ variants (vendor)
+ labels RDLTXT port
+ variants ()
+ labels RDLTXT text
+ variants *
+ labels RDLPIN port
+
+ # Find diffusion not covered in
+ # NSDM or PSDM and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PSDM
+ and-not NSDM
+ and POLY
+ copyup baretrans
+
+ templayer gendiff DIFF,TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and-not COREID
+ copyup barediff
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NSDM
+ and-not HVI,hvcheck
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NSDM
+ and HVI,hvcheck
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PSDM
+ and-not HVI,hvcheck
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PSDM
+ and HVI,hvcheck
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+
+ templayer gencont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ and-not CORELI
+ copyup barelicont
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ and-not CORELI
+ copyup barecont
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ variants (vendor)
+ labels PADTXT port
+ variants ()
+ labels PADTXT text
+ variants *
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+ layer obsactive FILLOBSFOM
+
+# MOS Varactor
+
+ layer var POLY
+ and TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+ and-not HVTP
+ # NOTE: Else forms a varactor that is not in the vendor netlist.
+ and-not COREID
+ labels POLY
+
+ layer varhvt POLY
+ and TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+ and HVTP
+ labels POLY
+
+ layer mvvar POLY
+ and TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma PWRES 64 13
+ calma TAP 65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTR
+ calma HVTR 18 20
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NSDM (NPLUS)
+ calma NSDM 93 44
+ # PSDM (PPLUS)
+ calma PSDM 94 20
+ # HVI (THKOX)
+ calma HVI 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # 3.3V native FET ID mark
+ calma LVID 81 60
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 44
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+ # ESD area ID
+ calma ESDID 81 19
+ calma OUTLINE 236 0
+
+ # LICON
+ calma CONT 66 44
+ calma LI 67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+ calma RDL 74 20
+ calma GLASS 76 20
+
+ calma SUBTXT 64 59
+ calma PADTXT 76 5
+ calma DIFFTXT 65 6
+ calma TAPTXT 65 5
+ calma WELLTXT 64 5
+ calma LITXT 67 5
+ calma POLYTXT 66 5
+ calma MET1TXT 68 5
+ calma MET2TXT 69 5
+ calma MET3TXT 70 5
+ calma MET4TXT 71 5
+ calma MET5TXT 72 5
+ calma RDLTXT 74 5
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+
+ calma LIFILL 56 28
+ calma MET1FILL 36 28
+ calma MET2FILL 41 28
+ calma MET3FILL 34 28
+ calma MET4FILL 51 28
+ calma MET5FILL 59 28
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+
+ calma SUBPIN 122 16
+ calma PADPIN 76 16
+ calma DIFFPIN 65 16
+ calma POLYPIN 66 16
+ calma WELLPIN 64 16
+ calma LIPIN 67 16
+ calma MET1PIN 68 16
+ calma MET2PIN 69 16
+ calma MET3PIN 70 16
+ calma MET4PIN 71 16
+ calma MET5PIN 72 16
+ calma RDLPIN 74 16
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+ calma CAPM 89 44
+ calma CAPM2 97 44
+
+ calma FILLOBSM1 62 24
+ calma FILLOBSM2 105 52
+ calma FILLOBSM3 107 24
+ calma FILLOBSM4 112 4
+ calma FILLOBSFOM 22 24
+ calma FILLOBSPOLY 33 24
+
+ calma FOMFILL 23 28
+ calma POLYFILL 28 28
+ calma LIFILL 56 28
+ calma MET1FILL 36 28
+ calma MET2FILL 41 28
+ calma MET3FILL 34 28
+ calma MET4FILL 51 28
+ calma MET5FILL 59 28
+
+#-----------------------------------------------------------------------
+
+style rdlimport
+ # This style is for reading shapes generated with the RDL layers
+
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ layer mrdl RDL
+ layer mrdlc RDLC
+
+ calma RDL 10 0
+ calma RDLC 20 0
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+ scalefactor 10
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# DNWELL
+#-----------------------------
+
+ width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
+ spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
+ spacing allnwell dnwell 4500 surround_ok \
+ "Deep N-well spacing to N-well < %d (nwell.7)"
+
+ variants (full)
+ cifmaxwidth nwell_missing 0 bend_illegal \
+ "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
+ cifmaxwidth dnwell_missing 0 bend_illegal \
+ "SONOS nFET must be in Deep N-well (tunm.6a)"
+
+ cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
+ "P+ diff cannot straddle Deep N-well (dnwell.5)"
+ variants (fast),(full)
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 840 "N-well width < %d (nwell.1)"
+ spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
+
+ variants (full)
+ cifmaxwidth nwell_missing_tap 0 bend_illegal \
+ "All nwells must contain metal-connected N+ taps (nwell.4)"
+
+ cifspacing mvnwell lvnwell 2000 touching_illegal \
+ "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
+ cifspacing mvnwell mvnwell 2000 touching_ok \
+ "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
+ variants (fast),(full)
+
+#-----------------------------
+# DIFF
+#-----------------------------
+
+ width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
+ 150 "Diffusion width < %d (diff/tap.1)"
+ width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
+ "MV Diffusion width < %d (diff/tap.14)"
+
+ width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
+ extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
+ extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
+ extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
+ extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
+ width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
+ spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
+ "Diffusion spacing < %d (diff/tap.3)"
+ spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
+ "MV Diffusion spacing < %d (diff/tap.15a)"
+ spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
+ "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
+ spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
+ touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
+ spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
+ "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
+ spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
+ "N-Diffusion spacing to N-well < %d (diff/tap.9)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
+ "N-Diffusion spacing to N-well < %d (diff/tap.9)"
+ spacing *psd allnwell 130 touching_illegal \
+ "P-tap spacing to N-well < %d (diff/tap.11)"
+ spacing *mvpsd allnwell 130 touching_illegal \
+ "P-tap spacing to N-well < %d (diff/tap.11)"
+ surround *nsd allnwell 180 absence_illegal \
+ "N-well overlap of N-tap < %d (diff/tap.10)"
+ surround *mvnsd allnwell 330 absence_illegal \
+ "N-well overlap of MV N-tap < %d (diff/tap.19)"
+ surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
+ "N-well overlap of P-Diffusion < %d (diff/tap.8)"
+ surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
+ "N-well overlap of P-Diffusion < %d (diff/tap.17)"
+ surround mvvar allnwell 560 absence_illegal \
+ "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
+ spacing *mvndiode *mvndiode 1070 touching_ok \
+ "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
+
+variants (full)
+ cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
+ "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
+ cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \
+ "HVI to HVI or LV nwell spacing < %d (hvi.5)"
+variants (fast),(full)
+
+ spacing allnfets allpactivenonfet 270 touching_illegal \
+ "nFET cannot abut P-diffusion (diff/tap.3)"
+ spacing allpfets allnactivenonfet 270 touching_illegal \
+ "pFET cannot abut N-diffusion (diff/tap.3)"
+
+ # Butting junction rules
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
+ "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
+ "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
+ "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
+ "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
+ "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
+ "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
+ "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
+ "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
+
+ # Sandwiched butting junction restrictions
+ edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
+ edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
+
+ area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
+ area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
+
+ angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
+
+ variants (full)
+ cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
+
+ # Latchup rules
+ cifmaxwidth ptap_missing 0 bend_illegal \
+ "N-diff distance to P-tap must be < 15.0um (LU.2)"
+ cifmaxwidth dptap_missing 0 bend_illegal \
+ "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
+ cifmaxwidth ntap_missing 0 bend_illegal \
+ "P-diff distance to N-tap must be < 15.0um (LU.3)"
+
+ variants (fast),(full)
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly,polyfill 150 "poly width < %d (poly.1a)"
+ spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
+
+ spacing allpolynonfet,polyfill \
+ *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
+ 75 corner_ok allfets \
+ "poly spacing to Diffusion < %d (poly.4)"
+ spacing npres *nsd 480 touching_illegal \
+ "poly resistor spacing to N-tap < %d (poly.9)"
+ overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
+ "N-Diffusion overhang of nFET < %d (poly.7)"
+ overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
+ overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
+ overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
+ overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
+ rect_only allfets "No bends in transistors (poly.11)"
+ rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
+ extend xpc/a xhrpoly,uhrpoly 2160 \
+ "poly contact extends poly resistor by < %d (licon.1c + li.5)"
+ spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
+ "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
+
+ variants (fast)
+
+ spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
+ "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
+ spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
+ "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
+ spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
+ "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
+
+ # Minimum width requirement means actual spacing from res to ndiff has to be
+ # constructed from mask rules. These supercede the simpler checks.
+
+ variants (full)
+
+ cifmaxwidth rpm_nsd_check 0 bend_illegal \
+ "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
+ cifmaxwidth rpm_poly_check 0 bend_illegal \
+ "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
+ cifmaxwidth rpm_hvntm_check 0 bend_illegal \
+ "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
+
+ variants (fast),(full)
+
+ angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
+
+#--------------------------------------------------------------------
+# HVTP
+#--------------------------------------------------------------------
+
+ spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
+ 360 touching_illegal \
+ "Min. spacing between pFET and HVTP < %d (hvtp.4)"
+
+ spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
+ "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
+
+#--------------------------------------------------------------------
+# LVTN
+#--------------------------------------------------------------------
+
+ spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
+ allfetsnolvt 360 touching_illegal \
+ "Min. spacing between FET and LVTN < %d (lvtn.3a)"
+
+ spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
+ 740 touching_illegal \
+ "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
+
+ # Spacing across S/D direction requires edge rule
+ edge4way allfetsnolvt allactivenonfet 415 \
+ ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
+ "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
+
+#--------------------------------------------------------------------
+# NPC (Nitride poly Cut)
+#--------------------------------------------------------------------
+
+# Layer NPC is defined automatically around poly contacts (grow 0.1um)
+
+#--------------------------------------------------------------------
+# CONT (LICON, contact between poly/diff and LI)
+#--------------------------------------------------------------------
+
+ width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
+ width nsc/li 170 "N-tap contact width < %d (licon.1)"
+ width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
+ width psc/li 170 "P-tap contact width < %d (licon.1)"
+ width ndic/li 170 "N-diode contact width < %d (licon.1)"
+ width pdic/li 170 "P-diode contact width < %d (licon.1)"
+ width pc/li 170 "poly contact width < %d (licon.1)"
+
+ width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
+ area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
+ area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
+
+ width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
+ width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
+ width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
+ width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
+ width mvndic/li 170 "N-diode contact width < %d (licon.1)"
+ width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
+
+ spacing allpdiffcont allndiffcont 170 touching_illegal \
+ "Diffusion contact spacing < %d (licon.2)"
+ spacing allndiffcont allndiffcont 170 touching_ok \
+ "Diffusion contact spacing < %d (licon.2)"
+ spacing allpdiffcont allpdiffcont 170 touching_ok \
+ "Diffusion contact spacing < %d (licon.2)"
+ spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
+
+ spacing pc alldiff 190 touching_illegal \
+ "poly contact spacing to diffusion < %d (licon.14)"
+ spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
+ "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
+
+ spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
+ "Diffusion contact to gate < %d (licon.11)"
+ spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
+ "Diffusion contact to standard cell gate < %d (licon.11)"
+ spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
+ "Diffusion contact to SRAM gate < %d (licon.11)"
+ spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
+ "Diffusion contact to gate < %d (licon.11)"
+ spacing nsc varactor,varhvt 250 touching_illegal \
+ "Diffusion contact to varactor gate < %d (licon.10)"
+ spacing mvnsc mvvar 250 touching_illegal \
+ "Diffusion contact to varactor gate < %d (licon.10)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
+ "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
+ surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
+ 40 absence_illegal \
+ "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
+ surround ndic/a *ndi 40 absence_illegal \
+ "N-diode overlap of N-diode contact < %d (licon.5a)"
+ surround pdic/a *pdi 40 absence_illegal \
+ "P-diode overlap of N-diode contact < %d (licon.5a)"
+
+ spacing psc/a allnactivenontap 60 touching_illegal \
+ "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
+ spacing nsc/a allpactivenontap 60 touching_illegal \
+ "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
+ "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
+ surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
+ 60 directional \
+ "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
+ surround ndic/a *ndi 60 directional \
+ "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+ surround pdic/a *pdi 60 directional \
+ "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+
+ surround nsc/a *nsd 120 directional \
+ "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
+ surround psc/a *psd 120 directional \
+ "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
+
+ surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
+ "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
+ surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
+ "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
+ surround mvndic/a *mvndi 40 absence_illegal \
+ "N-diode overlap of N-diode contact < %d (licon.5a)"
+ surround mvpdic/a *mvpdi 40 absence_illegal \
+ "P-diode overlap of N-diode contact < %d (licon.5a)"
+
+ spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
+ "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
+ spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
+ "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
+
+ surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
+ "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
+ surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
+ "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
+ surround mvndic/a *mvndi 60 directional \
+ "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+ surround mvpdic/a *mvpdi 60 directional \
+ "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+
+ surround mvnsc/a *mvnsd 120 directional \
+ "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
+ surround mvpsc/a *mvpsd 120 directional \
+ "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
+
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
+ "poly overlap of poly contact < %d (licon.8)"
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
+ "poly overlap of poly contact < %d in one direction (licon.8a)"
+
+ exact_overlap (allcont)/a
+
+#-------------------------------------------------------------
+# LI - Local interconnect layer
+#-------------------------------------------------------------
+
+variants *
+
+ width *li 170 "Local interconnect width < %d (li.1)"
+ width rli 290 "Local interconnect width < %d (li.7)"
+
+ spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
+ "Local interconnect spacing < %d (li.3)"
+
+ # Local interconnect in core (SRAM) cells has more relaxed rules. There are
+ # no special layers for the contacts in core cells, so they must be included
+ # in the rule.
+ width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
+ "Core local interconnect width < %d (li.c1)"
+
+ spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
+ "Core local interconnect spacing < %d (li.c2)"
+
+ surround pc/li *li,coreli 80 directional \
+ "Local interconnect overlap of poly contact < %d in one direction (li.5)"
+
+ surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
+ *li,rli,coreli 80 directional \
+ "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
+
+ area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
+
+ angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
+ angles coreli 45 \
+ "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
+
+#-------------------------------------------------------------
+# MCON - Contact between local interconnect and metal1
+#-------------------------------------------------------------
+
+ width mcon/m1 170 "mcon.width < %d (mcon.1)"
+ spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
+
+ exact_overlap mcon/li
+
+#-------------------------------------------------------------
+# METAL1 -
+#-------------------------------------------------------------
+
+ width *m1,rm1 140 "Metal1 width < %d (met1.1)"
+ spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
+ area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
+
+ surround mcon/m1 *met1 30 absence_illegal \
+ "Metal1 overlap of local interconnect contact < %d (met1.4)"
+ surround mcon/m1 *met1 60 directional \
+ "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
+
+ angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
+ "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
+ widespacing *obsm1 3005 allm1 280 touching_ok \
+ "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
+
+variants (full)
+ cifmaxwidth m1_hole_empty 0 bend_illegal \
+ "Min area of metal1 holes > 0.14um^2 (met1.7)"
+
+ cifspacing m1_large_halo m1_large_halo 280 touching_ok \
+ "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
+variants *
+
+#--------------------------------------------------
+# VIA1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
+ spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
+ surround v1/m1 *m1,rm1 30 directional \
+ "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
+ surround v1/m2 *m2,rm2 30 directional \
+ "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
+
+ exact_overlap v1/m1
+
+#--------------------------------------------------
+# METAL2 -
+#--------------------------------------------------
+
+ width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
+ spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
+ area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
+
+ angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
+ "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
+ widespacing obsm2 3005 allm2 280 touching_ok \
+ "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
+
+variants (full)
+ cifmaxwidth m2_hole_empty 0 bend_illegal \
+ "Min area of metal2 holes > 0.14um^2 (met2.7)"
+
+ cifspacing m2_large_halo m2_large_halo 280 touching_ok \
+ "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
+variants *
+
+#--------------------------------------------------
+# VIA2
+#--------------------------------------------------
+
+ width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)"
+
+ spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)"
+
+ surround v2/m2 *m2,rm2 45 directional \
+ "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)"
+ surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)"
+
+ exact_overlap v2/m2
+
+#--------------------------------------------------
+# METAL3 -
+#--------------------------------------------------
+
+ width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
+ spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
+ area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
+
+ angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
+ "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
+ widespacing obsm3 3005 allm3 400 touching_ok \
+ "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
+variants (full)
+ cifspacing m3_large_halo m3_large_halo 400 touching_ok \
+ "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
+variants *
+
+
+#--------------------------------------------------
+# VIA3 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)"
+ spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)"
+ surround v3/m3 *m3,rm3 30 directional \
+ "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)"
+ surround v3/m4 *m4,rm4 5 absence_illegal \
+ "Metal4 overlap of via3 < %d (met4.3 - via3.4)"
+
+ exact_overlap v3/m3
+
+#-----------------------------
+# METAL4 - METAL4 Module
+#-----------------------------
+
+variants *
+
+ width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
+ spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
+ area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
+
+ angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
+ "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
+ widespacing obsm4 3005 allm4 400 touching_ok \
+ "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
+variants (full)
+ cifspacing m4_large_halo m4_large_halo 400 touching_ok \
+ "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
+variants *
+
+#--------------------------------------------------
+# VIA4 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)"
+ spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)"
+ surround v4/m5 *m5,rm5 120 absence_illegal \
+ "Metal5 overlap of via4 < %d (met5.3 - via4.4)"
+
+ exact_overlap v4/m4
+
+#-----------------------------
+# METAL5 - METAL5 Module
+#-----------------------------
+
+ width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
+ spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
+ area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
+
+ angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
+
+
+
+variants (full)
+
+ width metrdl 10000 "RDL width < %d (rdl.1)"
+ spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
+ surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
+ spacing padl metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
+
+variants (fast),(full)
+
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ edge4way *poly allfetsstd 420 allfets 0 0 \
+ "Transistor width < %d (diff/tap.2)"
+ edge4way *poly allfetsspecial 360 allfets 0 0 \
+ "Transistor in standard cell width < %d (diff/tap.2)"
+ edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
+ "N-Transistor in SRAM core width < %d (diff/tap.2)"
+ edge4way *poly ppu 140 allfets 0 0 \
+ "P-Transistor in SRAM core width < %d (diff/tap.2)"
+
+ # Except: Note that standard cells allow transistor width minimum 0.36um
+ width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
+
+ spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
+ "poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
+ "poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
+ "poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
+ "poly spacing to diffusion tap < %d (poly.5)"
+
+ edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
+ "Butting P-tap spacing to NMOS gate < %d (poly.6)"
+ edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
+ "Butting N-tap spacing to PMOS gate < %d (poly.6)"
+ edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
+ "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
+ edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
+ "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
+
+ # No LV FETs in HV diff
+ spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
+ "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
+ "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ # No HV FETs in LV diff
+ spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
+ "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
+ "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ # Minimum length of MV FETs. Note that this is larger than the minimum
+ # width (0.29um), so an edge rule is required
+
+ edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
+ "MV NMOS minimum length < %d (poly.13)"
+
+ edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
+ "MV Varactor minimum length < %d (poly.13)"
+
+ edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
+ "MV PMOS minimum length < %d (poly.13)"
+
+#--------------------------------------------------
+# mrp1 (N+ poly resistor)
+#--------------------------------------------------
+
+ width mrp1 330 "mrp1 resistor width < %d (poly.3)"
+
+#--------------------------------------------------
+# xhrpoly (P+ poly resistor)
+# uhrpoly (P+ poly resistor, 2kOhm/sq)
+#--------------------------------------------------
+
+ # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
+ width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
+ width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
+
+ spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+ "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
+
+ spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
+ "Poly resistor spacing to poly < %d (poly.9)"
+
+ spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
+ "Poly resistor spacing to poly < %d (poly.9)"
+
+ spacing mrp1 *poly 480 touching_ok \
+ "Poly resistor spacing to poly < %d (poly.9)"
+
+ spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+ "Poly resistor spacing to diffusion < %d (poly.9)"
+
+#------------------------------------
+# nsonos
+#------------------------------------
+
+variants (full)
+ cifmaxwidth bbox_missing 0 bend_illegal \
+ "SONOS transistor must be in cell with abutment box (tunm.8)"
+variants (fast),(full)
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var,varhvt 250 \
+ "N-Tap overhang of Varactor < %d (var.4)"
+
+ overhang *mvnsd mvvar 250 \
+ "N-Tap overhang of Varactor < %d (var.4)"
+
+ width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
+ extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
+
+variants (full)
+ cifmaxwidth var_poly_no_nwell 0 bend_illegal \
+ "N-well overlap of varactor poly < 0.15um (varac.5)"
+
+ cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
+ "Varactor N-well must not contain P+ diffusion (varac.7)"
+variants (fast),(full)
+
+#-----------------------------------------------------------
+# MiM CAP (CAPM) -
+#-----------------------------------------------------------
+
+ width *mimcap 1000 "MiM cap width < %d (capm.1)"
+ spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
+ spacing *mimcap via3/m3 80 touching_illegal \
+ "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
+ surround *mimcc *mimcap 80 absence_illegal \
+ "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
+ rect_only *mimcap "MiM cap must be rectangular (capm.7)
+
+ surround *mimcap *metal3/m3 140 absence_illegal \
+ "Metal3 must surround MiM cap by %d (capm.3)"
+ spacing via2 *mimcap 100 touching_illegal \
+ "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
+ spacing *mimcap *metal3/m3 500 surround_ok \
+ "MiM cap spacing to unrelated metal3 < %d (capm.11)"
+
+variants (full)
+ cifspacing mim_bottom mim_bottom 1200 touching_ok \
+ "MiM cap bottom plate spacing < %d (capm.2b)"
+variants (fast),(full)
+
+ # MiM cap contact rules (VIA3)
+
+ width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
+ spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
+ surround mimcc/m4 *m4 5 directional \
+ "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
+ exact_overlap mimcc/c1
+
+ width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
+ spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
+ spacing *mimcap2 via4/m4 10 touching_illegal \
+ "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
+ surround *mim2cc *mimcap2 10 absence_illegal \
+ "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
+ rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
+
+ surround *mimcap2 *metal4/m4 140 absence_illegal \
+ "Metal4 must surround MiM2 cap by %d (cap2m.3)"
+ spacing via3 *mimcap2 80 touching_illegal \
+ "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
+ spacing *mimcap2 *metal4/m4 500 surround_ok \
+ "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
+
+variants (full)
+ cifmaxwidth mim2_contact_overlap 0 bend_illegal \
+ "MiM2 cap contact must not cross MiM cap contact (cap2m.8)"
+
+ cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
+ "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
+variants (fast),(full)
+
+ # MiM cap contact rules (VIA4)
+
+ width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
+ spacing mim2cc mim2cc 420 touching_ok \
+ "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
+ surround mim2cc/m5 *m5 120 absence_illegal \
+ "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
+ exact_overlap mim2cc/c2
+
+
+#----------------------------
+# HVNTM
+#----------------------------
+variants (full)
+ cifspacing hvntm_generate hvntm_generate 700 touching_ok \
+ "HVNTM spacing < %d (hvntm.2)"
+variants (fast),(full)
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ masterslice pwell pwell PWELL substrate
+ masterslice nwell nwell NWELL
+
+ routing li li1 LI1 LI li
+
+ routing m1 met1 MET1 m1
+ routing m2 met2 MET2 m2
+ routing m3 met3 MET3 m3
+ routing m4 met4 MET4 m4
+ routing m5 met5 MET5 m5
+ routing mrdl met6 MET6 m6 MRDL METRDL
+
+ cut mcon mcon MCON Mcon
+ cut m2c via via1 VIA VIA1 cont2 via12
+ cut m3c via2 VIA2 cont3 via23
+ cut via3 via3 VIA3 cont4 via34
+ cut via4 via4 VIA4 cont5 via45
+
+ obs obsli li1
+ obs obsm1 met1
+ obs obsm2 met2
+ obs obsm3 met3
+
+ obs obsm4 met4
+ obs obsm5 met5
+ obs obsmrdl met6
+
+ # NOTE: obsmcon only used with li1, not obsli.
+ obs obsmcon mcon
+
+ # Vias on obstruction layers should be ignored, so cast to obstruction metal.
+ obs obsm1 via
+ obs obsm2 via2
+ obs obsm3 via3
+ obs obsm4 via4
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+
+extract
+ style ngspice variants (),(orig),(si)
+ cscale 1
+ # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
+ # dimensions must be in units of microns in the extract file.
+ # Use extract style "ngspice(si)" to override this and produce
+ # a file with SI units for length/area.
+
+ variants (),(orig)
+ lambda 1E6
+ variants (si)
+ lambda 1.0
+ variants *
+
+ units microns
+ step 7
+ sidehalo 2
+
+ # NOTE: MiM cap layers have been purposely put out of order,
+ # may want to reconsider.
+
+ planeorder dwell 0
+ planeorder well 1
+ planeorder active 2
+ planeorder locali 3
+ planeorder metal1 4
+ planeorder metal2 5
+ planeorder metal3 6
+ planeorder metal4 7
+ planeorder metal5 8
+ planeorder metali 9
+ planeorder block 10
+ planeorder comment 11
+ planeorder cap1 12
+ planeorder cap2 13
+
+ height dnwell -0.1 0.1
+ height nwell,pwell 0.0 0.2062
+ height alldiff 0.2062 0.12
+ height fomfill 0.2062 0.12
+ height allpoly 0.3262 0.18
+ height polyfill 0.3262 0.18
+ height alldiffcont 0.3262 0.61
+ height pc 0.5062 0.43
+ height allli 0.9361 0.10
+ height mcon 1.0361 0.34
+ height allm1 1.3761 0.36
+ height m1fill 1.3761 0.36
+ height v1 1.7361 0.27
+ height allm2 2.0061 0.36
+ height m2fill 1.3761 0.36
+ height v2 2.3661 0.42
+ height allm3 2.7861 0.845
+ height m3fill 1.3761 0.36
+ height v3 3.6311 0.39
+ height allm4 4.0211 0.845
+ height m4fill 1.3761 0.36
+ height v4 4.8661 0.505
+ height allm5 5.3711 1.26
+ height m5fill 1.3761 0.36
+ height mimcap 2.4661 0.2
+ height mimcap2 3.7311 0.2
+ height mimcc 2.6661 0.12
+ height mim2cc 3.9311 0.09
+ height mrdlc 6.6311 0.63
+ height mrdl 7.2611 3.0
+
+ # Antenna check parameters
+ # Note that checks w/diode diffusion are not modeled
+ model partial
+ antenna poly sidewall 50 none
+ antenna allcont surface 3 none
+ antenna li sidewall 75 0 450
+ antenna mcon surface 3 0 18
+ antenna m1,m2,m3 sidewall 400 2600 400
+ antenna v1 surface 3 0 18
+ antenna v2 surface 6 0 36
+ antenna m4,m5 sidewall 400 2600 400
+ antenna v3,v4 surface 6 0 36
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
+
+# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# Device values come from trtc.cor (typical corner)
+ resist (dnwell)/dwell 2200000
+ resist (pwell)/well 3050000
+ resist (nwell)/well 1700000
+ resist (rpw)/well 3050000 0.5
+ resist (*ndiff,nsd)/active 120000
+ resist (*pdiff,*psd)/active 197000
+ resist (*mvndiff,mvnsd)/active 114000
+ resist (*mvpdiff,*mvpsd)/active 191000
+
+ resist ndiffres/active 120000 0.5
+ resist pdiffres/active 197000 0.5
+ resist mvndiffres/active 114000 0.5
+ resist mvpdiffres/active 191000 0.5
+ resist mrp1/active 48200 0.5
+ resist xhrpoly/active 319800 0.5
+ resist uhrpoly/active 2000000 0.5
+
+ resist (allpolynonres)/active 48200
+ resist rmp/active 48200
+
+ resist (allli)/locali 12200
+ resist (allm1)/metal1 125
+ resist (allm2)/metal2 125
+ resist (allm3)/metal3 47
+ resist (allm4)/metal4 47
+ resist (allm5)/metal5 29
+ resist mrdl/metali 5
+
+ contact ndc,nsc 15000
+ contact pdc,psc 15000
+ contact mvndc,mvnsc 15000
+ contact mvpdc,mvpsc 15000
+ contact pc 15000
+ contact mcon 152000
+ contact m2c 4500
+ contact m3c 3410
+ contact mimcc 4500
+ contact mim2cc 3410
+ contact via3 3410
+ contact via4 380
+ contact mrdlc 6
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values: Use document (...)
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement. All values are taken from the
+# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
+# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models. Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly. Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps. Technically, the capacitance probably
+# should be split between the two terminals. Unsure of the correct model.
+#-------------------------------------------------------------------------
+
+#n-well
+# NOTE: This value not found in PEX files
+defaultareacap nwell well 120
+
+#n-active
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap allnactivenonfet active 790
+# defaultperimeter allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap allpactivenonfet active 810
+# defaultperimeter allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall allpolynonfet active 22
+# defaultareacap allpolynonfet active 106
+# defaultperimeter allpolynonfet active 57
+
+ defaultsidewall *poly active 23
+ defaultareacap *poly active nwell,obswell,pwell well 106
+ defaultperimeter *poly active nwell,obswell,pwell well 55
+
+#locali
+ defaultsidewall allli locali 33
+ defaultareacap allli locali nwell,obswell,pwell well 37
+ defaultperimeter allli locali nwell,obswell,pwell well 55
+ defaultoverlap allli locali nwell well 37
+
+#locali->diff
+ defaultoverlap allli locali allactivenonfet active 37
+ defaultsideoverlap allli locali allactivenonfet active 55
+
+#locali->poly
+ defaultoverlap allli locali allpolynonres active 94
+ defaultsideoverlap allli locali allpolynonres active 52
+ defaultsideoverlap *poly active allli locali 25
+
+#metal1
+ defaultsidewall allm1 metal1 45
+ defaultareacap allm1 metal1 nwell,obswell,pwell well 26
+ defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
+ defaultoverlap allm1 metal1 nwell well 26
+
+#metal1->diff
+ defaultoverlap allm1 metal1 allactivenonfet active 26
+ defaultsideoverlap allm1 metal1 allactivenonfet active 41
+
+#metal1->poly
+ defaultoverlap allm1 metal1 allpolynonres active 45
+ defaultsideoverlap allm1 metal1 allpolynonres active 47
+ defaultsideoverlap *poly active allm1 metal1 17
+
+#metal1->locali
+ defaultoverlap allm1 metal1 allli locali 114
+ defaultsideoverlap allm1 metal1 allli locali 59
+ defaultsideoverlap allli locali allm1 metal1 35
+
+#metal2
+ defaultsidewall allm2 metal2 50
+ defaultareacap allm2 metal2 nwell,obswell,pwell well 17
+ defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
+ defaultoverlap allm2 metal2 nwell well 38
+
+#metal2->diff
+ defaultoverlap allm2 metal2 allactivenonfet active 17
+ defaultsideoverlap allm2 metal2 allactivenonfet active 41
+
+#metal2->poly
+ defaultoverlap allm2 metal2 allpolynonres active 24
+ defaultsideoverlap allm2 metal2 allpolynonres active 41
+ defaultsideoverlap *poly active allm2 metal2 11
+
+#metal2->locali
+ defaultoverlap allm2 metal2 allli locali 38
+ defaultsideoverlap allm2 metal2 allli locali 46
+ defaultsideoverlap allli locali allm2 metal2 22
+
+#metal2->metal1
+ defaultoverlap allm2 metal2 allm1 metal1 134
+ defaultsideoverlap allm2 metal2 allm1 metal1 67
+ defaultsideoverlap allm1 metal1 allm2 metal2 48
+
+#metal3
+ defaultsidewall allm3 metal3 63
+ defaultoverlap allm3 metal3 nwell well 12
+ defaultareacap allm3 metal3 nwell,obswell,pwell well 12
+ defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
+
+#metal3->diff
+ defaultoverlap allm3 metal3 allactive active 12
+ defaultsideoverlap allm3 metal3 allactive active 41
+
+#metal3->poly
+ defaultoverlap allm3 metal3 allpolynonres active 16
+ defaultsideoverlap allm3 metal3 allpolynonres active 44
+ defaultsideoverlap *poly active allm3 metal3 9
+
+#metal3->locali
+ defaultoverlap allm3 metal3 allli locali 21
+ defaultsideoverlap allm3 metal3 allli locali 47
+ defaultsideoverlap allli locali allm3 metal3 15
+
+#metal3->metal1
+ defaultoverlap allm3 metal3 allm1 metal1 35
+ defaultsideoverlap allm3 metal3 allm1 metal1 55
+ defaultsideoverlap allm1 metal1 allm3 metal3 27
+
+#metal3->metal2
+ defaultoverlap allm3 metal3 allm2 metal2 86
+ defaultsideoverlap allm3 metal3 allm2 metal2 70
+ defaultsideoverlap allm2 metal2 allm3 metal3 44
+
+#metal4
+ defaultsidewall allm4 metal4 67
+# defaultareacap alltopm metal4 well 6
+ areacap allm4/m4 8
+ defaultoverlap allm4 metal4 nwell well 8
+ defaultperimeter allm4 metal4 well 37
+
+#metal4->diff
+ defaultoverlap allm4 metal4 allactivenonfet active 8
+ defaultsideoverlap allm4 metal4 allactivenonfet active 37
+
+#metal4->poly
+ defaultoverlap allm4 metal4 allpolynonres active 10
+ defaultsideoverlap allm4 metal4 allpolynonres active 38
+ defaultsideoverlap *poly active allm4 metal4 6
+
+#metal4->locali
+ defaultoverlap allm4 metal4 allli locali 12
+ defaultsideoverlap allm4 metal4 allli locali 40
+ defaultsideoverlap allli locali allm4 metal4 10
+
+#metal4->metal1
+ defaultoverlap allm4 metal4 allm1 metal1 15
+ defaultsideoverlap allm4 metal4 allm1 metal1 43
+ defaultsideoverlap allm1 metal1 allm4 metal4 16
+
+#metal4->metal2
+ defaultoverlap allm4 metal4 allm2 metal2 20
+ defaultsideoverlap allm4 metal4 allm2 metal2 46
+ defaultsideoverlap allm2 metal2 allm4 metal4 22
+
+#metal4->metal3
+ defaultoverlap allm4 metal4 allm3 metal3 84
+ defaultsideoverlap allm4 metal4 allm3 metal3 71
+ defaultsideoverlap allm3 metal3 allm4 metal4 43
+
+#metal5
+ defaultsidewall allm5 metal5 127
+# defaultareacap allm5 metal5 well 6
+ areacap allm5/m5 6
+ defaultoverlap allm5 metal5 nwell well 6
+ defaultperimeter allm5 metal5 well 39
+
+#metal5->diff
+ defaultoverlap allm5 metal5 allactivenonfet active 6
+ defaultsideoverlap allm5 metal5 allactivenonfet active 39
+
+#metal5->poly
+ defaultoverlap allm5 metal5 allpolynonres active 7
+ defaultsideoverlap allm5 metal5 allpolynonres active 40
+ defaultsideoverlap *poly active allm5 metal5 6
+
+#metal5->locali
+ defaultoverlap allm5 metal5 allli locali 8
+ defaultsideoverlap allm5 metal5 allli locali 41
+ defaultsideoverlap allli locali allm5 metal5 8
+
+#metal5->metal1
+ defaultoverlap allm5 metal5 allm1 metal1 9
+ defaultsideoverlap allm5 metal5 allm1 metal1 43
+ defaultsideoverlap allm1 metal1 allm5 metal5 12
+
+#metal5->metal2
+ defaultoverlap allm5 metal5 allm2 metal2 11
+ defaultsideoverlap allm5 metal5 allm2 metal2 46
+ defaultsideoverlap allm2 metal2 allm5 metal5 16
+
+#metal5->metal3
+ defaultoverlap allm5 metal5 allm3 metal3 20
+ defaultsideoverlap allm5 metal5 allm3 metal3 54
+ defaultsideoverlap allm3 metal3 allm5 metal5 28
+
+#metal5->metal4
+ defaultoverlap allm5 metal5 allm4 metal4 68
+ defaultsideoverlap allm5 metal5 allm4 metal4 83
+ defaultsideoverlap allm4 metal4 allm5 metal5 47
+
+
+# Devices: Base models (not subcircuit wrappers)
+
+variants (),(si)
+
+ device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+
+ device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_nfet_latch npd \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_nfet_latch npd \
+ *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_nfet_pass npass \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device subcircuit sky130_fd_pr__cap_var_lvt varactor \
+ *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
+ device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
+ *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
+ device subcircuit sky130_fd_pr__cap_var mvvaractor \
+ *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
+
+ # Bipolars
+ device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
+ error +npn1p00
+ device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
+ error +npn2p00
+ device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
+ device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
+ pwell,space/w +pnp0p68
+ device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
+ pwell,space/w +pnp3p40
+ device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
+ device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
+ dnwell space/w error +npn11p0
+ device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
+
+ # Ignore the extended-drain FET geometry that forms part of the high-voltage
+ # bipolar devices.
+ device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
+ device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
+
+ # Extended drain devices (must appear before the regular devices)
+ device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
+ device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
+ device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
+ pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
+
+ device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
+ *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
+ *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
+ *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
+ *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
+ *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
+ *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
+ a1=as p1=ps a2=ad p2=pd
+
+ device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
+ device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
+ device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
+ device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
+ device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
+ device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
+
+ device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
+ xpc pwell,space/w error +res0p35 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
+ xpc pwell,space/w error +res0p69 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
+ xpc pwell,space/w error +res1p41 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
+ xpc pwell,space/w error +res2p85 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
+ xpc pwell,space/w error +res5p73 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
+ xpc pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
+ xpc pwell,space/w error +res0p35 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
+ xpc pwell,space/w error +res0p69 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
+ xpc pwell,space/w error +res1p41 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
+ xpc pwell,space/w error +res2p85 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
+ xpc pwell,space/w error +res5p73 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
+ xpc pwell,space/w error l=l w=w
+
+ device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
+ *ndiff pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
+ *pdiff nwell error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
+ pwell dnwell error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
+ *mvndiff pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
+ *mvpdiff nwell error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_po rmp *poly
+ device resistor sky130_fd_pr__res_generic_po mrp1 *poly
+
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
+ device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
+
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
+ device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
+
+ device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
+ device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
+
+ variants (orig)
+
+ device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
+ pwell,space/w
+
+ # Note that corenvar, corepvar are not considered devices, and extract as
+ # parasitic capacitance instead (but cap values need to be added).
+
+ # Extended drain devices (must appear before the regular devices)
+ device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error
+ device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error
+ device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
+ pwell,space/w nwell error
+
+ device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
+ device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
+ device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
+ device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
+
+ # These devices always extract as subcircuits
+ device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_po rmp *poly
+ device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
+ device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
+ device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
+ device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
+ device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
+ device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
+
+ device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
+ device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
+ device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
+ device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
+ device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
+ device resistor sky130_fd_pr__res_high_po xhrpoly xpc
+ device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
+ device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
+ device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
+ device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
+ device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
+ device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
+ device resistor sky130_fd_pr__res_generic_po mrp1 *poly
+ device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
+ device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
+ device resistor mrdn_hv mvndiffres *mvndiff
+ device resistor mrdp_hv mvpdiffres *mvpdiff
+ device resistor sky130_fd_pr__res_iso_pw rpw pwell
+
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
+
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
+
+ device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
+ device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
+ device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
+ device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
+ device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
+ device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
+ device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
+ device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
+
+ device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
+ device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ # All wiring values are in nanometers
+ scalefactor 10
+
+ contact mcon 170 li 0 0 m1 30 60
+ contact v1 260 m1 0 30 m2 0 30
+ contact v2 280 m2 0 45 m3 25 0
+ contact v3 320 m3 0 30 m4 5 5
+ contact v4 1180 m4 0 m5 120
+
+ contact pc 170 poly 50 80 li 0 80
+ contact pdc 170 pdiff 40 60 li 0 80
+ contact ndc 170 ndiff 40 60 li 0 80
+ contact psc 170 psd 40 60 li 0 80
+ contact nsc 170 nsd 40 60 li 0 80
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . .
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+ style pnm
+ default
+ draw fillblock no_color_at_all
+ draw fillblock4 no_color_at_all
+ draw fomfill no_color_at_all
+ draw polyfill no_color_at_all
+ draw m1fill no_color_at_all
+ draw m2fill no_color_at_all
+ draw m3fill no_color_at_all
+ draw m4fill no_color_at_all
+ draw m5fill no_color_at_all
+ draw nwell cwell
+end
+
diff --git a/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.mag b/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.mag
new file mode 100644
index 0000000..6a6475d
--- /dev/null
+++ b/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.mag
@@ -0,0 +1,425 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1615375237
+<< pwell >>
+rect 0 643 796 796
+rect 0 153 153 643
+rect 643 153 796 643
+rect 0 0 796 153
+<< nbase >>
+rect 153 153 643 643
+<< pdiff >>
+rect 330 449 466 466
+rect 330 347 347 449
+rect 449 347 466 449
+rect 330 330 466 347
+<< pdiffc >>
+rect 347 347 449 449
+<< psubdiff >>
+rect 26 736 770 770
+rect 26 702 60 736
+rect 94 702 128 736
+rect 162 702 196 736
+rect 230 702 264 736
+rect 298 702 498 736
+rect 532 702 566 736
+rect 600 702 634 736
+rect 668 702 702 736
+rect 736 702 770 736
+rect 26 669 770 702
+rect 26 668 127 669
+rect 26 634 60 668
+rect 94 634 127 668
+rect 26 600 127 634
+rect 669 668 770 669
+rect 669 634 702 668
+rect 736 634 770 668
+rect 26 566 60 600
+rect 94 566 127 600
+rect 26 532 127 566
+rect 26 498 60 532
+rect 94 498 127 532
+rect 26 298 127 498
+rect 26 264 60 298
+rect 94 264 127 298
+rect 26 230 127 264
+rect 26 196 60 230
+rect 94 196 127 230
+rect 26 162 127 196
+rect 669 600 770 634
+rect 669 566 702 600
+rect 736 566 770 600
+rect 669 532 770 566
+rect 669 498 702 532
+rect 736 498 770 532
+rect 669 298 770 498
+rect 669 264 702 298
+rect 736 264 770 298
+rect 669 230 770 264
+rect 669 196 702 230
+rect 736 196 770 230
+rect 26 128 60 162
+rect 94 128 127 162
+rect 26 127 127 128
+rect 669 162 770 196
+rect 669 128 702 162
+rect 736 128 770 162
+rect 669 127 770 128
+rect 26 94 770 127
+rect 26 60 60 94
+rect 94 60 128 94
+rect 162 60 196 94
+rect 230 60 264 94
+rect 298 60 498 94
+rect 532 60 566 94
+rect 600 60 634 94
+rect 668 60 702 94
+rect 736 60 770 94
+rect 26 26 770 60
+<< nsubdiff >>
+rect 189 583 607 607
+rect 189 549 213 583
+rect 247 549 281 583
+rect 315 549 481 583
+rect 515 549 549 583
+rect 583 549 607 583
+rect 189 535 607 549
+rect 189 515 261 535
+rect 189 481 213 515
+rect 247 481 261 515
+rect 189 315 261 481
+rect 535 515 607 535
+rect 535 481 549 515
+rect 583 481 607 515
+rect 189 281 213 315
+rect 247 281 261 315
+rect 189 261 261 281
+rect 535 315 607 481
+rect 535 281 549 315
+rect 583 281 607 315
+rect 535 261 607 281
+rect 189 247 607 261
+rect 189 213 213 247
+rect 247 213 281 247
+rect 315 213 481 247
+rect 515 213 549 247
+rect 583 213 607 247
+rect 189 189 607 213
+<< psubdiffcont >>
+rect 60 702 94 736
+rect 128 702 162 736
+rect 196 702 230 736
+rect 264 702 298 736
+rect 498 702 532 736
+rect 566 702 600 736
+rect 634 702 668 736
+rect 702 702 736 736
+rect 60 634 94 668
+rect 702 634 736 668
+rect 60 566 94 600
+rect 60 498 94 532
+rect 60 264 94 298
+rect 60 196 94 230
+rect 702 566 736 600
+rect 702 498 736 532
+rect 702 264 736 298
+rect 702 196 736 230
+rect 60 128 94 162
+rect 702 128 736 162
+rect 60 60 94 94
+rect 128 60 162 94
+rect 196 60 230 94
+rect 264 60 298 94
+rect 498 60 532 94
+rect 566 60 600 94
+rect 634 60 668 94
+rect 702 60 736 94
+<< nsubdiffcont >>
+rect 213 549 247 583
+rect 281 549 315 583
+rect 481 549 515 583
+rect 549 549 583 583
+rect 213 481 247 515
+rect 549 481 583 515
+rect 213 281 247 315
+rect 549 281 583 315
+rect 213 213 247 247
+rect 281 213 315 247
+rect 481 213 515 247
+rect 549 213 583 247
+<< locali >>
+rect 26 736 770 770
+rect 26 702 60 736
+rect 94 702 128 736
+rect 162 702 196 736
+rect 230 702 264 736
+rect 298 702 498 736
+rect 532 702 566 736
+rect 600 702 634 736
+rect 668 702 702 736
+rect 736 702 770 736
+rect 26 669 770 702
+rect 26 668 127 669
+rect 26 634 60 668
+rect 94 634 127 668
+rect 26 600 127 634
+rect 669 668 770 669
+rect 669 634 702 668
+rect 736 634 770 668
+rect 26 566 60 600
+rect 94 566 127 600
+rect 26 532 127 566
+rect 26 498 60 532
+rect 94 498 127 532
+rect 26 298 127 498
+rect 26 264 60 298
+rect 94 264 127 298
+rect 26 230 127 264
+rect 26 196 60 230
+rect 94 196 127 230
+rect 26 162 127 196
+rect 189 583 607 607
+rect 189 549 213 583
+rect 247 549 281 583
+rect 315 549 481 583
+rect 515 549 549 583
+rect 583 549 607 583
+rect 189 535 607 549
+rect 189 515 261 535
+rect 189 481 213 515
+rect 247 481 261 515
+rect 189 315 261 481
+rect 535 515 607 535
+rect 535 481 549 515
+rect 583 481 607 515
+rect 319 463 477 477
+rect 319 429 333 463
+rect 367 449 429 463
+rect 463 429 477 463
+rect 319 367 347 429
+rect 449 367 477 429
+rect 319 333 333 367
+rect 367 333 429 347
+rect 463 333 477 367
+rect 319 319 477 333
+rect 189 281 213 315
+rect 247 281 261 315
+rect 189 261 261 281
+rect 535 315 607 481
+rect 535 281 549 315
+rect 583 281 607 315
+rect 535 261 607 281
+rect 189 247 607 261
+rect 189 213 213 247
+rect 247 213 281 247
+rect 315 213 481 247
+rect 515 213 549 247
+rect 583 213 607 247
+rect 189 189 607 213
+rect 669 600 770 634
+rect 669 566 702 600
+rect 736 566 770 600
+rect 669 532 770 566
+rect 669 498 702 532
+rect 736 498 770 532
+rect 669 298 770 498
+rect 669 264 702 298
+rect 736 264 770 298
+rect 669 230 770 264
+rect 669 196 702 230
+rect 736 196 770 230
+rect 26 128 60 162
+rect 94 128 127 162
+rect 26 127 127 128
+rect 669 162 770 196
+rect 669 128 702 162
+rect 736 128 770 162
+rect 669 127 770 128
+rect 26 94 770 127
+rect 26 60 60 94
+rect 94 60 128 94
+rect 162 60 196 94
+rect 230 60 264 94
+rect 298 60 498 94
+rect 532 60 566 94
+rect 600 60 634 94
+rect 668 60 702 94
+rect 736 60 770 94
+rect 26 26 770 60
+<< viali >>
+rect 333 449 367 463
+rect 429 449 463 463
+rect 333 429 347 449
+rect 347 429 367 449
+rect 429 429 449 449
+rect 449 429 463 449
+rect 333 347 347 367
+rect 347 347 367 367
+rect 429 347 449 367
+rect 449 347 463 367
+rect 333 333 367 347
+rect 429 333 463 347
+<< metal1 >>
+rect 315 463 481 481
+rect 315 429 333 463
+rect 367 429 429 463
+rect 463 429 481 463
+rect 315 367 481 429
+rect 315 333 333 367
+rect 367 333 429 367
+rect 463 333 481 367
+rect 315 315 481 333
+<< comment >>
+rect 26 782 27 795
+tri 27 782 31 786 se
+tri 765 782 769 786 sw
+rect 769 782 770 795
+rect 26 781 371 782
+rect 424 781 770 782
+rect 26 769 27 781
+tri 27 777 31 781 ne
+tri 765 777 769 781 nw
+rect 769 769 770 781
+rect 153 620 154 633
+tri 154 620 158 624 se
+tri 638 620 642 624 sw
+rect 642 620 643 633
+rect 153 619 345 620
+rect 452 619 643 620
+rect 153 607 154 619
+tri 154 615 158 619 ne
+tri 638 615 642 619 nw
+rect 642 607 643 619
+rect 189 565 190 578
+tri 190 565 194 569 se
+tri 208 565 212 569 sw
+rect 212 565 213 578
+rect 189 564 213 565
+rect 189 552 190 564
+tri 190 560 194 564 ne
+rect 208 563 211 564
+tri 211 563 212 564 nw
+tri 199 560 201 563 se
+tri 208 560 211 563 nw
+tri 198 557 199 560 se
+rect 199 557 201 560
+tri 201 557 202 560 sw
+rect 197 556 198 557
+tri 198 556 199 557 nw
+rect 201 556 202 557
+rect 195 524 200 556
+rect 212 552 213 564
+rect 607 533 608 546
+tri 608 533 612 537 se
+tri 664 533 668 537 sw
+rect 668 533 669 546
+rect 607 532 669 533
+rect 607 520 608 532
+tri 608 528 612 532 ne
+tri 664 528 668 532 nw
+rect 668 520 669 532
+rect 330 479 331 492
+tri 331 479 335 483 se
+tri 461 479 465 483 sw
+rect 465 479 466 492
+rect 330 478 377 479
+rect 419 478 466 479
+rect 330 466 331 478
+tri 331 474 335 478 ne
+tri 461 474 465 478 nw
+rect 465 466 466 478
+rect 189 442 190 455
+tri 190 442 194 446 se
+tri 256 442 260 446 sw
+rect 260 442 261 455
+rect 189 441 261 442
+rect 189 429 190 441
+tri 190 437 194 441 ne
+tri 256 437 260 441 nw
+rect 260 429 261 441
+tri 390 404 392 406 se
+tri 392 404 393 406 sw
+tri 403 404 404 406 se
+tri 404 404 406 406 sw
+tri 390 403 392 404 ne
+rect 392 403 393 404
+tri 393 403 395 404 sw
+tri 401 403 403 404 se
+tri 392 400 395 403 ne
+tri 395 401 396 403 sw
+tri 400 401 401 403 se
+rect 401 401 403 403
+tri 403 401 406 404 nw
+rect 395 400 396 401
+tri 396 400 398 401 sw
+tri 398 400 400 401 se
+tri 395 398 396 400 ne
+tri 393 395 396 398 se
+rect 396 396 400 400
+tri 400 398 403 401 nw
+rect 396 395 397 396
+tri 397 395 398 396 nw
+tri 398 395 399 396 ne
+rect 399 395 400 396
+tri 400 395 403 398 sw
+tri 390 392 393 395 se
+tri 393 392 396 395 nw
+tri 400 392 403 395 ne
+tri 403 392 406 395 sw
+tri 390 390 392 392 ne
+tri 392 390 393 392 nw
+tri 403 390 404 392 ne
+tri 404 390 406 392 nw
+rect 466 330 467 343
+tri 467 330 471 334 se
+tri 530 330 534 334 sw
+rect 534 330 535 343
+rect 466 329 535 330
+rect 466 317 467 329
+tri 467 325 471 329 ne
+tri 530 325 534 329 nw
+rect 534 317 535 329
+rect 669 330 670 343
+tri 670 330 674 334 se
+tri 765 330 769 334 sw
+rect 769 330 770 343
+rect 669 329 770 330
+rect 669 317 670 329
+tri 670 325 674 329 ne
+tri 765 325 769 329 nw
+rect 769 317 770 329
+rect 189 176 190 189
+tri 190 176 194 180 se
+tri 602 176 606 180 sw
+rect 606 176 607 189
+rect 189 175 377 176
+rect 419 175 607 176
+rect 189 163 190 175
+tri 190 171 194 175 ne
+tri 602 171 606 175 nw
+rect 606 163 607 175
+rect 362 136 363 149
+tri 363 136 367 140 se
+tri 429 136 433 140 sw
+rect 433 136 434 149
+rect 362 135 434 136
+rect 362 123 363 135
+tri 363 131 367 135 ne
+tri 429 131 433 135 nw
+rect 433 123 434 135
+<< labels >>
+flabel comment s 404 90 404 90 0 FreeSans 180 0 0 0 Use 28 licons in collector to match PNP model
+flabel comment s 404 222 404 222 0 FreeSans 140 0 0 0 Use 12 licons in base to match PNP model
+flabel comment s 168 516 168 516 0 FreeSans 100 0 0 0 0.12 min
+flabel comment s 168 496 168 496 0 FreeSans 100 0 0 0 adj. sides
+flabel comment s 396 148 396 148 0 FreeSans 100 0 0 0 0.360
+flabel comment s 398 782 398 782 0 FreeSans 100 0 0 0 3.720
+flabel comment s 398 620 398 620 0 FreeSans 100 0 0 0 2.450(nwell)
+flabel comment s 718 342 718 342 0 FreeSans 100 0 0 0 0.505
+flabel comment s 638 544 638 544 0 FreeSans 100 0 0 0 0.310
+flabel comment s 224 454 224 454 0 FreeSans 100 0 0 0 0.360
+flabel comment s 500 342 500 342 0 FreeSans 100 0 0 0 0.345
+flabel comment s 398 176 398 176 0 FreeSans 100 0 0 0 2.090
+flabel comment s 398 480 398 480 0 FreeSans 100 0 0 0 0.068
+<< end >>
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b33e032..dd265cc 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -49,122 +49,43 @@
inout vssd2, // User area 2 digital ground
`endif
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
// IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
+ input en,
+ output vbgp
- // IRQ
- output [2:0] irq
);
- wire clk;
- wire rst;
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
- // IRQ
- assign irq = 3'b000; // Unused
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
-
- counter #(
+ bandgap #(
.BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
+ ) bandgap(
+ .EN(en),
+ .VBGP(vbgp)
);
endmodule
-module counter #(
+module bandgap #(
parameter BITS = 32
)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
+ input EN,
+ output VBGP
);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
+ reg real VBGP;
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
+ initial begin
+ if (EN == 1'b1) begin
+ VBGP <= 1.201;
+ end else begin
+ VBGP <= 0.0;
+ end
+ end
+
+ always @(EN) begin
+ if (EN == 1'b1) begin
+ VBGP <= 1.201;
+ end else begin
+ VBGP <= 0.0;
+ end
end
endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2a3462b..58791aa 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -94,34 +94,11 @@
.vssd2(vssd2), // User area 2 digital ground
`endif
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
// IO Pads
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
+ .en (io_in[23]),
+ .vbgp(io_out[23]),
- // IRQ
- .irq(user_irq)
);
endmodule // user_project_wrapper