blob: d883e52f9009bb10fa26e61a3da8d290fdd8b10a [file] [log] [blame]
---
project:
description: "A bandgap reference design with sky130"
foundry: "SkyWater"
git_url: "https://github.com/swarup-p/bandgap_caravel.git"
organization: "VLSI System Design Corporation"
organization_url: "http://vlsisystemdesign.com"
owner: "Swarup Pulujkar"
process: "SKY130"
project_name: "Bandgap"
project_id: "00000000"
tags:
- "Open MPW"
- "Test Harness"
category: "Test Harness"
top_level_netlist: "caravel/verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "docs/source/_static/caravel_harness.png"