| **.subckt top_pll_v1_pex_no_integration vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset |
| *+ cp_nswitch cp_pswitch cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_pad out_to_div |
| *+ out_by_2 n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 div_5_Q1 div_5_Q1_shift |
| *+ div_5_nQ0 div_5_Q0 div_5_nQ2 out_div_by_5 |
| *.iopin vdd |
| *.iopin vss |
| *.ipin in_ref |
| *.iopin pfd_QA |
| *.iopin pfd_QB |
| *.iopin Up |
| *.iopin nUp |
| *.iopin Down |
| *.iopin nDown |
| *.iopin pfd_reset |
| *.iopin cp_nswitch |
| *.iopin cp_pswitch |
| *.iopin cp_biasp |
| *.ipin iref_cp |
| *.iopin lf_vc |
| *.iopin vco_D0 |
| *.iopin vco_vctrl |
| *.iopin vco_out |
| *.iopin out_first_buffer |
| *.opin out_to_pad |
| *.iopin out_to_div |
| *.iopin out_by_2 |
| *.iopin n_out_by_2 |
| *.iopin out_div_2 |
| *.iopin n_out_div_2 |
| *.iopin out_buffer_div_2 |
| *.iopin n_out_buffer_div_2 |
| *.iopin div_5_Q1 |
| *.iopin div_5_Q1_shift |
| *.iopin div_5_nQ0 |
| *.iopin div_5_Q0 |
| *.iopin div_5_nQ2 |
| *.iopin out_div_by_5 |
| x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD_pex_c |
| x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c |
| x3 vdd vco_out vco_vctrl vss vco_D0 csvco_pex_c |
| x5 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift |
| + div_by_5_pex_c |
| x6 vss vco_vctrl lf_vc loop_filter_pex_c |
| x7 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c |
| x8 vdd vco_out out_to_pad out_to_div vss out_first_buffer ring_osc_buffer_pex_c |
| x4 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 |
| + div_by_2_pex_c |
| **.ends |
| ** flattened .save nodes |
| .end |
