| **.subckt tb_div_by_5 |
| VSS vss GND {vss} |
| VDD vdd vss {vdd} |
| Vref CLK vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 |
| C2 clk_10 vss 10f m=1 |
| x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2 |
| x1 vdd clk_10 clk_2 vss nclk_2 net5 net6 net7 net8 net9 div_by_5 |
| **** begin user architecture code |
| |
| |
| |
| * Parameters |
| .param kp = 1.0 |
| .param vdd = kp*1.8 |
| .param vss = 0.0 |
| .param vin = vdd |
| .param fref = 100e6 |
| .param Tref = 1/fref |
| .param C = 1f |
| .param iref=100u |
| |
| .options TEMP = 100.0 |
| .options RSHUNT = 1e20 |
| |
| * Models |
| .lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS |
| |
| * Data to save |
| .save all |
| |
| .ic v(CLK) = 0.0 |
| .ic v(x1.q2) = 0.0 |
| .ic v(x1.q1) = 0.0 |
| .ic v(x1.q1_shift) = 0.0 |
| .ic v(x1.q0) = 0.0 |
| .ic v(x1.x1.a) = 0.0 |
| .ic v(x1.x1.D_d) = 0.0 |
| .ic v(x1.x1.nD_d) = 0.0 |
| |
| * Simulation |
| .control |
| tran 0.01ns 600ns |
| *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15 |
| *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6 |
| *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6 |
| *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5 |
| *let T = Tosc/10.0 |
| *let f = 1/T |
| *let Td = 1/(2*3*f) |
| *print T f Td |
| write tb_div_by_5_tran.raw |
| plot v(clk_10) v(clk) v(clk_2) v(clk_2)+3 v(clk)+6 |
| plot v(x1.Q2) v(x1.Q1)+2 v(clk_Q0)+4 v(x1.Q1_shift)+6 v(clk_10)+8 |
| |
| .endc |
| |
| |
| |
| **** end user architecture code |
| **.ends |
| |
| * expanding symbol: div_by_2.sym # of pins=9 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch |
| .subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2 |
| *.ipin CLK |
| *.opin CLK_2 |
| *.iopin vss |
| *.iopin vdd |
| *.opin nCLK_2 |
| *.iopin nout_div |
| *.iopin o2 |
| *.iopin o1 |
| *.iopin out_div |
| x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop |
| x2 vdd CLK_d CLK nCLK_d vss clock_inverter |
| x3 vdd o1 out_div vss inverter_min_x2 |
| x4 vdd CLK_2 o1 vss inverter_min_x4 |
| x5 vdd o2 nout_div vss inverter_min_x2 |
| x6 vdd nCLK_2 o2 vss inverter_min_x4 |
| .ends |
| |
| |
| * expanding symbol: div_by_5.sym # of pins=10 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch |
| .subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift |
| *.iopin vdd |
| *.iopin vss |
| *.ipin CLK |
| *.opin CLK_5 |
| *.ipin nCLK |
| *.iopin nQ2 |
| *.iopin Q1 |
| *.iopin Q0 |
| *.iopin nQ0 |
| *.iopin Q1_shift |
| x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1 |
| x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1 |
| x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1 |
| x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1 |
| x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop |
| x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop |
| x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop |
| x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop |
| .ends |
| |
| |
| * expanding symbol: DFlipFlop.sym # of pins=7 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch |
| .subckt DFlipFlop vdd Q nQ vss D CLK nCLK |
| *.iopin vdd |
| *.iopin vss |
| *.opin Q |
| *.opin nQ |
| *.ipin D |
| *.ipin CLK |
| *.ipin nCLK |
| x1 vdd D_d D nD_d vss clock_inverter |
| x2 vdd nA A D_d nD_d CLK vss latch_diff |
| x3 vdd nQ Q A nA nCLK vss latch_diff |
| .ends |
| |
| |
| * expanding symbol: clock_inverter.sym # of pins=5 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch |
| .subckt clock_inverter vdd CLK_d CLK nCLK_d vss |
| *.ipin CLK |
| *.iopin vdd |
| *.iopin vss |
| *.opin nCLK_d |
| *.opin CLK_d |
| x5 vdd nCLK_d net1 vss trans_gate |
| x1 vdd CLK_d net2 vss inverter_cp_x1 |
| x2 vdd net2 CLK vss inverter_cp_x1 |
| x3 vdd net1 CLK vss inverter_cp_x1 |
| .ends |
| |
| |
| * expanding symbol: inverter_min_x2.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch |
| .subckt inverter_min_x2 vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| .ends |
| |
| |
| * expanding symbol: inverter_min_x4.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch |
| .subckt inverter_min_x4 vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=4 m=4 |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=4 m=4 |
| .ends |
| |
| |
| * expanding symbol: latch_diff.sym # of pins=7 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch |
| .subckt latch_diff vdd nQ Q D nD CLK vss |
| *.iopin vdd |
| *.iopin vss |
| *.ipin D |
| *.opin nQ |
| *.ipin CLK |
| *.ipin nD |
| *.opin Q |
| XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| .ends |
| |
| |
| * expanding symbol: trans_gate.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch |
| .subckt trans_gate vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| .ends |
| |
| |
| * expanding symbol: inverter_cp_x1.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch |
| .subckt inverter_cp_x1 vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| .ends |
| |
| .GLOBAL GND |
| **** begin user architecture code |
| .include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice |
| .include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice |
| .include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice |
| |
| **** end user architecture code |
| ** flattened .save nodes |
| .end |
