| **.subckt div_by_2 CLK CLK_2 vss vdd nCLK_2 nout_div o2 o1 out_div |
| *.ipin CLK |
| *.opin CLK_2 |
| *.iopin vss |
| *.iopin vdd |
| *.opin nCLK_2 |
| *.iopin nout_div |
| *.iopin o2 |
| *.iopin o1 |
| *.iopin out_div |
| x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop |
| x2 vdd CLK_d CLK nCLK_d vss clock_inverter |
| x3 vdd o1 out_div vss inverter_min_x2 |
| x4 vdd CLK_2 o1 vss inverter_min_x4 |
| x5 vdd o2 nout_div vss inverter_min_x2 |
| x6 vdd nCLK_2 o2 vss inverter_min_x4 |
| **.ends |
| |
| * expanding symbol: DFlipFlop.sym # of pins=7 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch |
| .subckt DFlipFlop vdd Q nQ vss D CLK nCLK |
| *.iopin vdd |
| *.iopin vss |
| *.opin Q |
| *.opin nQ |
| *.ipin D |
| *.ipin CLK |
| *.ipin nCLK |
| x1 vdd D_d D nD_d vss clock_inverter |
| x2 vdd nA A D_d nD_d CLK vss latch_diff |
| x3 vdd nQ Q A nA nCLK vss latch_diff |
| .ends |
| |
| |
| * expanding symbol: clock_inverter.sym # of pins=5 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch |
| .subckt clock_inverter vdd CLK_d CLK nCLK_d vss |
| *.ipin CLK |
| *.iopin vdd |
| *.iopin vss |
| *.opin nCLK_d |
| *.opin CLK_d |
| x5 vdd nCLK_d net1 vss trans_gate |
| x1 vdd CLK_d net2 vss inverter_cp_x1 |
| x2 vdd net2 CLK vss inverter_cp_x1 |
| x3 vdd net1 CLK vss inverter_cp_x1 |
| .ends |
| |
| |
| * expanding symbol: inverter_min_x2.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch |
| .subckt inverter_min_x2 vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| .ends |
| |
| |
| * expanding symbol: inverter_min_x4.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch |
| .subckt inverter_min_x4 vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=4 m=4 |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=4 m=4 |
| .ends |
| |
| |
| * expanding symbol: latch_diff.sym # of pins=7 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch |
| .subckt latch_diff vdd nQ Q D nD CLK vss |
| *.iopin vdd |
| *.iopin vss |
| *.ipin D |
| *.opin nQ |
| *.ipin CLK |
| *.ipin nD |
| *.opin Q |
| XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| .ends |
| |
| |
| * expanding symbol: trans_gate.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch |
| .subckt trans_gate vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| .ends |
| |
| |
| * expanding symbol: inverter_cp_x1.sym # of pins=4 |
| * sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym |
| * sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch |
| .subckt inverter_cp_x1 vdd out in vss |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| *.iopin vdd |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=3 m=3 |
| .ends |
| |
| ** flattened .save nodes |
| .end |
