blob: ed43aba0c5fb11f1a379d62246ff4a5850cdfb90 [file] [log] [blame]
---
project:
description: "Analog Test Chip of several circuits used as master tesis"
foundry: "SkyWater"
git_url: "https://https://github.com/fredysolis/caravel_analog_fulgor.git"
organization: "FundaciĆ³n Fulgor"
organization_url: "http://www.fundacionfulgor.org.ar/sitio/index.php"
owner: "Diego Hernando"
process: "SKY130"
project_name: "Caravel Analog Fulgor"
project_id: "00000000"
tags:
- "Open MPW"
- "Test Harness"
category: "Test Harness"
top_level_netlist: "caravel/verilog/gl/caravan.v"
user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
version: "1.00"
cover_image: "docs/source/_static/caravel_harness.png"