Possible fix to XOR error
11 files changed
tree: b2fefd6e7d0651ce0ccde2913bb5a1b6bbe94e3e
  1. .github/
  2. checks/
  3. docs/
  4. gds/
  5. mag/
  6. netgen/
  7. openlane/
  8. verilog/
  9. xschem/
  10. .gitignore
  11. .gitmodules
  12. ext.sh
  13. ext_port.sh
  14. info.yaml
  15. LICENSE
  16. lvs.sh
  17. Makefile
  18. README.md
  19. skywater_setup.sh
README.md

Caravel Analog Fulgor

License UPRJ_CI Caravan Build


Repo Setup

In order to get de PDK, tools and paths needed to get the desing working just run the skywater_setup.sh script.

./skywater_setup.sh

This script creates a directory named skywater in $HOME. Under this directory you will find the Google-Skywater 130nm Open Source PDK and several tools and configurations needed, in order to work with the analog desing flow.

This script does the following:

Running the tools

Xschem

In the xschem folder all the schematics and spice symbols are located. To open one of those shematics the following commands need to be run:

cd caravel_analog_fulgor/xschem
xschem {schematic_name.sch}

In the xschem folder it is found the xschemrc file, where the paths to the xschem libraries are defined. There is also a simualtions folder where all the .spice and .raw files are stored.

Magic

To run magic and be able to edit or desing a layout the following commands need to be run:

cd caravel_analog_fulgor/mag
magic -rcfile magicrc {layout_name.mag}

The magicrc file specifies where the open_pdk layout libraries are located. If magic is used without the -rcfile specification, the sky130 library won't be loaded.

Extractions

In order to get the .spice files form layout or extract parasitics from the desings, extractions must be run. The following scripts make easy this step:

  • ext.sh: extraction without creating ports. It extract files for LVS and PEX with C parasitics and RC parasitics.
  • ext_port.sh: creates ports from the layout labels. It generates the same files as the previous script.

To run them, just tipe:

./ext.sh
./ext_port.sh

The script will ask you for the cellname. You need to make sure that the schematic and the layout views of the cell match in names :exclamation:.

LVS

netgen is used as the LVS test tool. You need to provide to it the path to the .spice files to compare (from layout and schematic) and with the design rools from the PDK. To make this step easier, there is also a script:

  • lvs.sh: compares the layout and schematic .spice files, and check if they match. The script will ask you for the cellname. You need to make sure that the schematic and the layout views of the cell match in names :exclamation:. The LVS report can be found in mag/extractions/lvs_{cellname}.out

Desing Description

As posgraduate students, we are training ourselves and testing several analog desings from various mixed signal circuits.

In this run you can find:

  • A 1GHz Current Starved VCO based PLL