Create README.md
Added links to various files in the repository
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@@ -6,9 +6,11 @@
- Ivan Rodriguez-Ferrandez (UPC¹-BSC²)
- Alvaro Jover-Alvarez (UPC¹-BSC²)
- Leonidas Kosmidis (BSC²-UPC¹)
+- David Steenari (ESA³)
<br/>
¹ Universitat Politècnica de Catalunya (UPC) <br/>
-² Barcelona Supercomputing Center (BSC)
+² Barcelona Supercomputing Center (BSC) <br/>
+³ European Space Agency (ESA)
@@ -64,7 +66,7 @@
The most vulnerable parts of a hardware design are its memory structures because they retain their previous values. Therefore, in our chip we have decided to focus on error detection and error correction specifically on flip-flops and registers which are the primary memory storage primitives. Therefore, our design is centered around a register file with 32, 32-bit registers implemented with flip-flops. We have implemented multiple reliability solutions such as different degrees of replication and ECC around this register file, which can be selectively configured and combined (with some limitations), in order to reliably detect whether errors occur, and in case they do, whether they can be corrected. Moreover, we include a redundant Monitoring Unit consisting of detailed event counters for each of the registers. This way, we can also assess the protection level offered by these different reliability methods and study their trade-offs in order to guide future developments.
In particular, our design has the following characteristics:
-- 32, 32-bit register file implemented with flip-flops, organised in 8 banks which can be used in parallel. Each register value can be individually set or inspected. The register file can be either clocked with a user controled signal, offering full control, or with the default chip clock.
+- 32, 32-bit register file implemented with flip-flops, organised in 4 banks which can be used in parallel. Each register value can be individually set or inspected. The register file can be either clocked with a user controled signal, offering full control, or with the default chip clock.
- 4 different protection mechanisms, each of which can be enabled selectively and in combination with others:
- Error Correction Code (ECC): ECC with 1 bit correction and 2 bit correction.
@@ -209,9 +211,9 @@
## **Block Description**
-The main code part is in the [ecc_registers](verilog/rtl/ecc_registers) directory inside the [rtl](verilog/rtl) directory. The user_proj.v contains only the connections to connect the project wrapper with the register file. The module works in a black box manner, the values are inserted to the module and you can ask for a value inside of the memory and the output is the value requested with a status signal that tells if the value is correct without modifications, the value has been corrected or if the value data is invalid. It is important to note that if more that two bits are flip in the register value the system can not reliable determine if the value is incorrect.
+The main code part is in the [ecc_registers](verilog/rtl/ecc_registers) directory inside the [rtl](verilog/rtl) directory. The [user_proj_example.v](https://github.com/jaquerinte/caravel_radiation_harden/blob/main/verilog/rtl/user_proj_example.v) contains only the connections to connect the project wrapper with the register file. The module works in a black box manner, the values are inserted to the module and you can ask for a value inside of the memory and the output is the value requested with a status signal that tells if the value is correct without modifications, the value has been corrected or if the value data is invalid. It is important to note that if more that two bits are flip in the register value the system can not reliable determine if the value is incorrect.
-The module is implemented with 32 registers of 32-bit words, organised in 8 banks. The counters of monitoring unit have a 32-bit width, too.
+The module is implemented with 32 registers of 32-bit words, organised in 4 banks. The counters of monitoring unit have a 32-bit width, too.
## Module Ports:
@@ -269,9 +271,9 @@
- Input probes:
- la_data_in [0] ⟶ rregister_i.
- la_data_in [1] ⟶ wregister_i.
- - la_data_in [4:2] ⟶ operation_type_i .
- - la_data_in [9:5] ⟶ register_i [5:0].
- - la_data_in [31:10] ⟶ Not connected.
+ - la_data_in [2] ⟶ operation_type_i .
+ - la_data_in [7:3] ⟶ register_i [4:0].
+ - la_data_in [31:8] ⟶ Not connected.
- la_data_in [63:32] ⟶ data_to_register_i [31:0].
- la_data_in [64] ⟶ clk_i.
- la_data_in [65] ⟶ rst_i.
@@ -443,38 +445,38 @@
We provide a set of tests that verifies all the described functionality. All tests have been tested both at RTL as well as at gate-level simulation. The test are the following:
-- la_test1: This test is the most basic test, which writes a value with ECC to a register and then reads that value from the memory.
+- [la_test1](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test1): This test is the most basic test, which writes a value with ECC to a register and then reads that value from the memory.
-- la_test2: This test, writes and reads all of the 32 registers of chip using ECC.
+- [la_test2](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test2): This test, writes and reads all of the 32 registers of chip using ECC.
-- la_test3: This test, writes and reads from one of the triple redundancy registers.
+- [la_test3](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test3): This test, writes and reads from one of the triple redundancy registers.
-- la_test4: This test, writes in a triple redundant register and modify two of the copies of the data stored to test that the error state is detected.
+- [la_test4](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test4): This test, writes in a triple redundant register and modify two of the copies of the data stored to test that the error state is detected.
-- la_test5: This test writes and reads from one of the shadow registers.
+- [la_test5](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test5): This test writes and reads from one of the shadow registers.
-- la_test6: This test, writes and reads all of the 16 registers using shadow registers.
+- [la_test6](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test6): This test, writes and reads all of the 16 registers using shadow registers.
-- la_test7: This test, writes in a register using a shadow register and modifies the shadow register to verify that the error is detected.
+- [la_test7](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test7): This test, writes in a register using a shadow register and modifies the shadow register to verify that the error is detected.
-- la_test8: This test writes and reads from one of the ECC shadow registers.
+- [la_test8](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test8): This test writes and reads from one of the ECC shadow registers.
-- la_test9: This test, writes and reads all of the 16 registers using ECC shadow registers.
+- [la_test9](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test9): This test, writes and reads all of the 16 registers using ECC shadow registers.
-- la_test10: This test, writes in a register using a ECC shadow register and modify the shadow register to verify that the error is detected.
+- [la_test10](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test10): This test, writes in a register using a ECC shadow register and modify the shadow register to verify that the error is detected.
-- la_test11: This test writes and reads from one register without using any protection.
+- [la_test11](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/la_test11): This test writes and reads from one register without using any protection.
-- wb_test1: This test uses the wishbone interface to modify one bit of an internal register in order to test the ECC functionality.
+- [wb_test1](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test1): This test uses the wishbone interface to modify one bit of an internal register in order to test the ECC functionality.
-- wb_test2: This test uses the wishbone interface to modify one bit of an internal register and also makes some reads in oder to check the monitoring counters.
+- [wb_test2](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test2): This test uses the wishbone interface to modify one bit of an internal register and also makes some reads in oder to check the monitoring counters.
-- wb_test3: This test uses the wishbone interface to modify one value of an internal triple redundant register and also makes a read to check that the output value is correct and the corrected stage is detected.
+- [wb_test3](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test3): This test uses the wishbone interface to modify one value of an internal triple redundant register and also makes a read to check that the output value is correct and the corrected stage is detected.
-- wb_test4: This test uses the wishbone interface to add a value per each of the 32 registers and then using the chip we read the 32 values. This is for testing the proper access of all of the registers.
+- [wb_test4](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test4): This test uses the wishbone interface to add a value per each of the 32 registers and then using the chip we read the 32 values. This is for testing the proper access of all of the registers.
-- wb_test5: This test is similar to the wb_test2 but verifies that the two copies of the monitoring unit (PMU-1 and PMU-2) have the same values for the total reads and corrected errors.
+- [wb_test5](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test5): This test is similar to the wb_test2 but verifies that the two copies of the monitoring unit (PMU-1 and PMU-2) have the same values for the total reads and corrected errors.
-- wb_test6. Using the base of the wb_test2 this test tries to access a non valid address. The expected result is that the program finishes without problems and without halting the processor, because our implementation ignores the invalid access.
+- [wb_test6](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test6). Using the base of the wb_test2 this test tries to access a non valid address. The expected result is that the program finishes without problems and without halting the processor, because our implementation ignores the invalid access.
-- wb_test7. Using as a base the la_test2, we write to all registers and we read them again. We check some of the individual counters to check that the number of reads are correct, as well the total reads and writes from the PMU-1 and PMU-2.
+- [wb_test7](https://github.com/jaquerinte/caravel_radiation_harden/tree/main/verilog/dv/wb_test7). Using as a base the la_test2, we write to all registers and we read them again. We check some of the individual counters to check that the number of reads are correct, as well the total reads and writes from the PMU-1 and PMU-2.
