stable version of the code ready for testing

diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 3d0f09b..1ded7ae 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile

@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = la_test1 la_test2 la_test3 la_test4 la_test5 la_test6 la_test7 la_test8 la_test9 la_test10 la_test11 wb_test1 wb_test2 wb_test3
+PATTERNS = la_test1 la_test2 la_test3 la_test4 la_test5 la_test6 la_test7 la_test8 la_test9 la_test10 la_test11 wb_test1 wb_test2 wb_test3 wb_test4 wb_test5 wb_test6 wb_test7
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \

diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
index 42d40ac..0b20dfb 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/verilog/dv/la_test1/la_test1.c

@@ -119,7 +119,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test10/la_test10.c b/verilog/dv/la_test10/la_test10.c
index effcf1d..c837277 100644
--- a/verilog/dv/la_test10/la_test10.c
+++ b/verilog/dv/la_test10/la_test10.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test11/la_test11.c b/verilog/dv/la_test11/la_test11.c
index 52fd544..defd3ff 100644
--- a/verilog/dv/la_test11/la_test11.c
+++ b/verilog/dv/la_test11/la_test11.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
index 4d51ec2..705e96d 100644
--- a/verilog/dv/la_test2/la_test2.c
+++ b/verilog/dv/la_test2/la_test2.c

@@ -126,7 +126,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test3/la_test3.c b/verilog/dv/la_test3/la_test3.c
index 299c09b..093035c 100644
--- a/verilog/dv/la_test3/la_test3.c
+++ b/verilog/dv/la_test3/la_test3.c

@@ -132,7 +132,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test4/la_test4.c b/verilog/dv/la_test4/la_test4.c
index 94cd59a..863ddbb 100644
--- a/verilog/dv/la_test4/la_test4.c
+++ b/verilog/dv/la_test4/la_test4.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test5/la_test5.c b/verilog/dv/la_test5/la_test5.c
index e5f5162..2468493 100644
--- a/verilog/dv/la_test5/la_test5.c
+++ b/verilog/dv/la_test5/la_test5.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test6/la_test6.c b/verilog/dv/la_test6/la_test6.c
index eec33a2..98686c6 100644
--- a/verilog/dv/la_test6/la_test6.c
+++ b/verilog/dv/la_test6/la_test6.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test7/la_test7.c b/verilog/dv/la_test7/la_test7.c
index 9b6e2e2..d2e5370 100644
--- a/verilog/dv/la_test7/la_test7.c
+++ b/verilog/dv/la_test7/la_test7.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test8/la_test8.c b/verilog/dv/la_test8/la_test8.c
index d21f730..6cbb184 100644
--- a/verilog/dv/la_test8/la_test8.c
+++ b/verilog/dv/la_test8/la_test8.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/la_test9/la_test9.c b/verilog/dv/la_test9/la_test9.c
index 47b4744..5911dc6 100644
--- a/verilog/dv/la_test9/la_test9.c
+++ b/verilog/dv/la_test9/la_test9.c

@@ -138,7 +138,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/wb_test1/wb_test1.c b/verilog/dv/wb_test1/wb_test1.c
index d69cbcb..71b9d90 100644
--- a/verilog/dv/wb_test1/wb_test1.c
+++ b/verilog/dv/wb_test1/wb_test1.c

@@ -48,7 +48,7 @@
 
 }
 
-#define reg_wb_register  (*(volatile uint32_t*)0x30000000)
+#define reg_wb_register  (*(volatile uint32_t*)0x30100000)
 
 void main()
 {
@@ -131,7 +131,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/wb_test2/wb_test2.c b/verilog/dv/wb_test2/wb_test2.c
index 6768714..9f2b868 100644
--- a/verilog/dv/wb_test2/wb_test2.c
+++ b/verilog/dv/wb_test2/wb_test2.c

@@ -47,10 +47,9 @@
 	reg_la0_data = (selected_regsiter << 5| 1 & 0x1F);
 
 }
-
-#define reg_wb_register        (*(volatile uint32_t*)0x30000010)
-#define reg_wb_reads           (*(volatile uint32_t*)0x41000000)
-#define reg_wb_ecc_corrected   (*(volatile uint32_t*)0x41000008)
+#define reg_wb_register        (*(volatile uint32_t*)0x30100010)
+#define reg_wb_reads           (*(volatile uint32_t*)0x30001000)
+#define reg_wb_ecc_corrected   (*(volatile uint32_t*)0x30001008)
 
 void main()
 {
@@ -133,7 +132,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	

diff --git a/verilog/dv/wb_test2/wb_test2.gtkw b/verilog/dv/wb_test2/wb_test2.gtkw
index f9d2c9f..4d8966a 100644
--- a/verilog/dv/wb_test2/wb_test2.gtkw
+++ b/verilog/dv/wb_test2/wb_test2.gtkw

@@ -1,22 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Sun May 23 12:10:10 2021
+[*] Sun Jun 13 09:45:33 2021
 [*]
 [dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test2/wb_test2.vcd"
-[dumpfile_mtime] "Sun May 23 11:41:09 2021"
-[dumpfile_size] 1179668140
+[dumpfile_mtime] "Sat Jun 12 22:44:29 2021"
+[dumpfile_size] 1649511525
 [savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test2/wb_test2.gtkw"
-[timestart] 613400000
+[timestart] 1227360000
 [size] 1848 1016
 [pos] -1 -1
-*-26.000000 2444300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-23.000000 746087500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] wb_test2_tb.
 [treeopen] wb_test2_tb.uut.
 [treeopen] wb_test2_tb.uut.mprj.
 [treeopen] wb_test2_tb.uut.mprj.mprj.
 [treeopen] wb_test2_tb.uut.mprj.mprj.register_file.
 [sst_width] 233
-[signals_width] 222
+[signals_width] 442
 [sst_expanded] 1
 [sst_vpaned_height] 289
 @200
@@ -38,24 +38,43 @@
 -
 -WB TOP
 @22
-wb_test2_tb.uut.mprj.mprj.register_file.whisbone_addr_i[31:0]
 wb_test2_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+@28
 wb_test2_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.wbs_adr_i[31:0]
 @28
 wb_test2_tb.uut.mprj.mprj.register_file.valid_i
+>96000000
 wb_test2_tb.uut.mprj.mprj.register_file.wbs_we_i
+>0
 wb_test2_tb.uut.mprj.mprj.register_file.ready_o
 @22
 wb_test2_tb.uut.mprj.mprj.register_file.rdata_o[31:0]
 @200
 -
--GPIO
+-PMU
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMU.wregister_i
+@29
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMU.rregister_i
 @22
-wb_test2_tb.mprj_io[37:0]
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMU.rdata_o[31:0]
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMU.ready_o
 @200
 -
--PMU
-@23
-wb_test2_tb.uut.mprj.mprj.register_file.inst_PMU.rdata_o[31:0]
+-PMUBACK
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMUBACKUP.rdata_o[31:0]
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMUBACKUP.ready_o
+@200
+-
+-DATA REGISTER
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.inst_RD.ready_o
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.inst_RD.rdata_o[31:0]
 [pattern_trace] 1
 [pattern_trace] 0

diff --git a/verilog/dv/wb_test3/wb_test3.c b/verilog/dv/wb_test3/wb_test3.c
index ceb3403..e7fa865 100644
--- a/verilog/dv/wb_test3/wb_test3.c
+++ b/verilog/dv/wb_test3/wb_test3.c

@@ -60,7 +60,7 @@
 
 }
 
-#define reg_wb_register  (*(volatile uint32_t*)0x30000000)
+#define reg_wb_register  (*(volatile uint32_t*)0x30100034)
 
 void main()
 {
@@ -143,7 +143,7 @@
 	// inputs to the cpu are outpus for my project denoted for been 1
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	
@@ -155,7 +155,7 @@
 	reg_la2_data = 0x00000000;
 	// end clock
 
-    add_value_to_triplet_register(2, 28);
+    add_value_to_triplet_register(2, 12);
     clock();
     clean_lines();
     clock();
@@ -169,7 +169,7 @@
     clock();
     reg_la2_oenb = 0xFFFFFFFC;
 
-    read_value_from_triplet_register(28);
+    read_value_from_triplet_register(12);
     clock();
     
     reg_mprj_datal = 0xAB410000;

diff --git a/verilog/dv/wb_test3/wb_test3.gtkw b/verilog/dv/wb_test3/wb_test3.gtkw
index 268299b..03efb1b 100644
--- a/verilog/dv/wb_test3/wb_test3.gtkw
+++ b/verilog/dv/wb_test3/wb_test3.gtkw

@@ -1,21 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Thu May 27 13:43:50 2021
+[*] Sun Jun 13 10:41:42 2021
 [*]
 [dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test3/wb_test3.vcd"
-[dumpfile_mtime] "Thu May 27 13:33:38 2021"
-[dumpfile_size] 284633629
+[dumpfile_mtime] "Sun Jun 13 10:19:48 2021"
+[dumpfile_size] 2292156642
 [savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test3/wb_test3.gtkw"
-[timestart] 454590000
+[timestart] 542438800
 [size] 1848 1016
-[pos] -39 -39
-*-24.000000 506437500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[pos] -1 -1
+*-15.000000 542487500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] wb_test3_tb.
 [treeopen] wb_test3_tb.uut.
 [treeopen] wb_test3_tb.uut.mprj.
 [treeopen] wb_test3_tb.uut.mprj.mprj.
+[treeopen] wb_test3_tb.uut.mprj.mprj.register_file.
 [sst_width] 233
-[signals_width] 222
+[signals_width] 317
 [sst_expanded] 1
 [sst_vpaned_height] 289
 @200
@@ -27,17 +28,17 @@
 @22
 [color] 6
 wb_test3_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+@24
 [color] 2
 wb_test3_tb.uut.mprj.mprj.register_file.register_i[4:0]
 @28
+wb_test3_tb.uut.mprj.mprj.register_file.operation_type_i[2:0]
 [color] 3
 wb_test3_tb.uut.mprj.mprj.register_file.rregister_i
 [color] 3
 wb_test3_tb.uut.mprj.mprj.register_file.wregister_i
-@29
-[color] 3
-wb_test3_tb.uut.mprj.mprj.register_file.operation_type_i
 @22
+[color] 3
 wb_test3_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
 @28
 wb_test3_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
@@ -47,13 +48,13 @@
 @28
 wb_test3_tb.uut.mprj.mprj.register_file.clk_i
 @22
-wb_test3_tb.uut.mprj.mprj.register_file.whisbone_addr_i[31:0]
 wb_test3_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
 @28
 wb_test3_tb.uut.mprj.mprj.register_file.wbs_we_i
 wb_test3_tb.uut.mprj.mprj.register_file.valid_i
 @22
 wb_test3_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+wb_test3_tb.uut.mprj.mprj.register_file.wbs_adr_i[31:0]
 @28
 wb_test3_tb.uut.mprj.mprj.register_file.ready_o
 @22
@@ -63,5 +64,26 @@
 -GPIO
 @22
 wb_test3_tb.mprj_io[37:0]
+@200
+-
+-REGISTER DATA
+@22
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.store_data_o[38:0]
+@28
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.redundat_validation_o[1:0]
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.operational_o
+@23
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.xor_1[31:0]
+@22
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.xor_2[31:0]
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.xor_3[31:0]
+@28
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.xor_reduce_1
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.xor_reduce_2
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.xor_reduce_3
+@22
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.nand_1[31:0]
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.nand_2[31:0]
+wb_test3_tb.uut.mprj.mprj.register_file.inst_RD.nand_3[31:0]
 [pattern_trace] 1
 [pattern_trace] 0

diff --git a/verilog/dv/wb_test4/Makefile b/verilog/dv/wb_test4/Makefile
new file mode 100644
index 0000000..deaacc2
--- /dev/null
+++ b/verilog/dv/wb_test4/Makefile

@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_test4
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all

diff --git a/verilog/dv/wb_test4/wb_test4.c b/verilog/dv/wb_test4/wb_test4.c
new file mode 100644
index 0000000..279b046
--- /dev/null
+++ b/verilog/dv/wb_test4/wb_test4.c

@@ -0,0 +1,183 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+void clock(){
+	// clock
+	reg_la2_data = 0x00000001;
+	reg_la2_data = 0x00000000;
+	// end clock
+}
+
+void clean_lines(){
+    reg_la0_data = 0x00000000;
+    reg_la1_data = 0x00000000;
+}
+
+void add_value_to_register_no_proteccion(uint32_t value, uint32_t selected_register){
+
+	reg_la0_data = (selected_register << 5| 18 & 0x1F);
+	reg_la1_data = value;
+}
+
+void read_value_from_register_no_proteccion(uint32_t selected_register){
+
+	reg_la0_data = (selected_register << 5| 17 & 0x1F);
+
+}
+
+void add_value_to_register(uint32_t value, uint32_t selected_register){
+
+	reg_la0_data = (selected_register << 5| 2 & 0x1F);
+	reg_la1_data = value;
+}
+
+void read_value_from_register(uint32_t selected_register){
+
+	reg_la0_data = (selected_register << 5| 1 & 0x1F);
+
+}
+
+//#define reg_wb_register  (*(volatile uint32_t*)0x30100034)
+
+void main()
+{
+    
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+
+	reg_uart_clkdiv = 625;
+	reg_uart_enable = 1;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // define whisbone data
+    volatile uint32_t *reg_wb_register;
+    reg_wb_register = 0x30100000;
+
+	// Configure LA probes 
+	// outputs from the cpu are inputs for my project denoted for been 0 
+	// inputs to the cpu are outpus for my project denoted for been 1
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+	
+	// Flag start of the test 
+	reg_mprj_datal = 0xAB400000;
+
+	// clock and reset
+	reg_la2_data = 0x00000003;
+	reg_la2_data = 0x00000000;
+	// end clock
+
+    clean_lines();
+    clock();
+    // deactivate internal clock
+    reg_la2_oenb = 0xFFFFFFFF;
+
+    for (uint32_t i = 0; i < 32; ++i ){
+        *reg_wb_register = i+1;
+        reg_wb_register = reg_wb_register + 1;
+	}
+    clock();
+    reg_la2_oenb = 0xFFFFFFFC;
+
+	for (uint32_t i = 0; i < 32; ++i ){
+		read_value_from_register_no_proteccion(i);
+		clock();
+	}
+
+    reg_mprj_datal = 0xAB410000;
+	print("\n");
+	print("Monitor: Test 4 Passed\n\n");	// Makes simulation very long!
+	reg_mprj_datal = 0xAB510000;
+}

diff --git a/verilog/dv/wb_test4/wb_test4.gtkw b/verilog/dv/wb_test4/wb_test4.gtkw
new file mode 100644
index 0000000..6032adb
--- /dev/null
+++ b/verilog/dv/wb_test4/wb_test4.gtkw

@@ -0,0 +1,57 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Sun Jun 13 20:29:56 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test4/wb_test4.vcd"
+[dumpfile_mtime] "Sun Jun 13 20:14:14 2021"
+[dumpfile_size] 2366682146
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test4/wb_test4.gtkw"
+[timestart] 1142500000
+[size] 1848 1016
+[pos] -1 -1
+*-25.000000 1207200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] wb_test4_tb.
+[treeopen] wb_test4_tb.uut.
+[treeopen] wb_test4_tb.uut.mprj.
+[treeopen] wb_test4_tb.uut.mprj.mprj.
+[sst_width] 370
+[signals_width] 222
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+wb_test4_tb.uut.mprj.mprj.register_file.clk_i
+wb_test4_tb.uut.mprj.mprj.register_file.rst_i
+@24
+wb_test4_tb.uut.mprj.mprj.register_file.register_i[4:0]
+@22
+wb_test4_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+@28
+wb_test4_tb.uut.mprj.mprj.register_file.operation_type_i[2:0]
+wb_test4_tb.uut.mprj.mprj.register_file.rregister_i
+wb_test4_tb.uut.mprj.mprj.register_file.wregister_i
+@24
+wb_test4_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@28
+wb_test4_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@200
+-
+-GPIO
+@29
+wb_test4_tb.mprj_io[37:0]
+@200
+-
+-WB TOP
+@22
+wb_test4_tb.uut.mprj.mprj.register_file.wbs_adr_i[31:0]
+wb_test4_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+@28
+wb_test4_tb.uut.mprj.mprj.register_file.wbs_we_i
+@22
+wb_test4_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
+wb_test4_tb.uut.mprj.mprj.register_file.rdata_o[31:0]
+@28
+wb_test4_tb.uut.mprj.mprj.register_file.ready_o
+[pattern_trace] 1
+[pattern_trace] 0

diff --git a/verilog/dv/wb_test4/wb_test4_tb.v b/verilog/dv/wb_test4/wb_test4_tb.v
new file mode 100644
index 0000000..f7d8950
--- /dev/null
+++ b/verilog/dv/wb_test4/wb_test4_tb.v

@@ -0,0 +1,214 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module wb_test4_tb;
+	reg clock;
+    reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    wire gpio;
+	wire uart_tx;
+    wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits  = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	initial begin
+		$dumpfile("wb_test4.vcd");
+		$dumpvars(0, wb_test4_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (200) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test WB (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test WB (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		wait(mprj_io[25:20] == 6'd0);
+		$display("WB Test 4 started");
+		wait(mprj_io[25:20] == 6'd1);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd2);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd3);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd4);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd5);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd6);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd7);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd8);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd9);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd10);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd11);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd12);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd13);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd14);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd15);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd16);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd17);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd18);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd19);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd20);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd21);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd22);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd23);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd24);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd25);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd26);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd27);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd28);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd29);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd30);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd31);
+		wait(mprj_io[37:36] == 2'b00);
+		wait(mprj_io[25:20] == 6'd32);
+		wait(mprj_io[37:36] == 2'b00);
+		
+		$display("WB Test 4 Finish correctly");
+		//wait(checkbits == 16'h0002);
+		#10000;
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("wb_test4.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/wb_test5/Makefile b/verilog/dv/wb_test5/Makefile
new file mode 100644
index 0000000..1fe7f1a
--- /dev/null
+++ b/verilog/dv/wb_test5/Makefile

@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_test5
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all

diff --git a/verilog/dv/wb_test5/wb_test5.c b/verilog/dv/wb_test5/wb_test5.c
new file mode 100644
index 0000000..1866fa4
--- /dev/null
+++ b/verilog/dv/wb_test5/wb_test5.c

@@ -0,0 +1,201 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+void clock(){
+	// clock
+	reg_la2_data = 0x00000001;
+	reg_la2_data = 0x00000000;
+	// end clock
+}
+
+void clean_lines(){
+    reg_la0_data = 0x00000000;
+    reg_la1_data = 0x00000000;
+}
+
+void add_value_to_register(uint32_t value, uint32_t selected_regsiter){
+
+	reg_la0_data = (selected_regsiter << 5| 2 & 0x1F);
+	reg_la1_data = value;
+}
+
+void read_value_from_register(uint32_t selected_regsiter){
+
+	reg_la0_data = (selected_regsiter << 5| 1 & 0x1F);
+
+}
+#define reg_wb_register               (*(volatile uint32_t*)0x30100010)
+#define reg_wb_reads                  (*(volatile uint32_t*)0x30001000)
+#define reg_wb_ecc_corrected          (*(volatile uint32_t*)0x30001008)
+#define reg_wb_reads_back             (*(volatile uint32_t*)0x30011000)
+#define reg_wb_ecc_corrected_back     (*(volatile uint32_t*)0x30011008)
+
+void main()
+{
+    
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+
+	reg_uart_clkdiv = 625;
+	reg_uart_enable = 1;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+	// Configure LA probes 
+	// outputs from the cpu are inputs for my project denoted for been 0 
+	// inputs to the cpu are outpus for my project denoted for been 1
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+	
+	// Flag start of the test 
+	reg_mprj_datal = 0xAB400000;
+
+	// clock and reset
+	reg_la2_data = 0x00000003;
+	reg_la2_data = 0x00000000;
+	// end clock
+
+    add_value_to_register(1, 4);
+    clock();
+    add_value_to_register(2, 0);
+    clock();
+    add_value_to_register(3, 1);
+    clock();
+    clean_lines();
+    clock();
+    // deactivate internal clock
+    reg_la2_oenb = 0xFFFFFFFF;
+    // data 0x1
+    // partity bits 1000011
+
+    //apply modification to the register
+    reg_wb_register = 0x00000003;
+    clock();
+    // re enable clock
+    reg_la2_oenb = 0xFFFFFFFC;
+
+    read_value_from_register(4);
+    clock();
+    read_value_from_register(1);
+    clock();
+
+    clean_lines();
+    clock();
+    // deactivate internal clock
+    reg_la2_oenb = 0xFFFFFFFF;
+    // check registers file
+    if (reg_wb_reads == reg_wb_reads_back){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    if (reg_wb_ecc_corrected == reg_wb_ecc_corrected_back){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+
+    clock();
+    // re enable clock
+    reg_la2_oenb = 0xFFFFFFFC;
+    read_value_from_register(0);
+    clock();
+    
+    reg_mprj_datal = 0xAB410000;
+	print("\n");
+	print("Monitor: Test 5 Passed\n\n");	// Makes simulation very long!
+	reg_mprj_datal = 0xAB510000;
+}

diff --git a/verilog/dv/wb_test5/wb_test5.gtkw b/verilog/dv/wb_test5/wb_test5.gtkw
new file mode 100644
index 0000000..6a33905
--- /dev/null
+++ b/verilog/dv/wb_test5/wb_test5.gtkw

@@ -0,0 +1,50 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jun 14 07:36:59 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test5/wb_test5.vcd"
+[dumpfile_mtime] "Mon Jun 14 07:34:40 2021"
+[dumpfile_size] 1223633704
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test5/wb_test5.gtkw"
+[timestart] 748541000
+[size] 1848 1016
+[pos] -1 -1
+*-18.000000 749305000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] wb_test5_tb.
+[treeopen] wb_test5_tb.uut.
+[treeopen] wb_test5_tb.uut.mprj.
+[treeopen] wb_test5_tb.uut.mprj.mprj.
+[sst_width] 233
+[signals_width] 325
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+wb_test5_tb.uut.mprj.mprj.register_file.clk_i
+wb_test5_tb.uut.mprj.mprj.register_file.rst_i
+@22
+wb_test5_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+wb_test5_tb.uut.mprj.mprj.register_file.register_i[4:0]
+@28
+wb_test5_tb.uut.mprj.mprj.register_file.operation_type_i[2:0]
+wb_test5_tb.uut.mprj.mprj.register_file.rregister_i
+wb_test5_tb.uut.mprj.mprj.register_file.wregister_i
+@22
+wb_test5_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@29
+wb_test5_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@200
+-
+-TOP WISHBONE
+@22
+wb_test5_tb.uut.mprj.mprj.register_file.wbs_adr_i[31:0]
+wb_test5_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+wb_test5_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
+@28
+wb_test5_tb.uut.mprj.mprj.register_file.wbs_we_i
+wb_test5_tb.uut.mprj.mprj.register_file.ready_o
+@22
+wb_test5_tb.uut.mprj.mprj.register_file.rdata_o[31:0]
+[pattern_trace] 1
+[pattern_trace] 0

diff --git a/verilog/dv/wb_test5/wb_test5_tb.v b/verilog/dv/wb_test5/wb_test5_tb.v
new file mode 100644
index 0000000..195d6af
--- /dev/null
+++ b/verilog/dv/wb_test5/wb_test5_tb.v

@@ -0,0 +1,155 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module wb_test5_tb;
+	reg clock;
+    reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    wire gpio;
+	wire uart_tx;
+    wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits  = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	initial begin
+		$dumpfile("wb_test5.vcd");
+		$dumpvars(0, wb_test5_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (200) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test WB (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test WB (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		wait(mprj_io[25:20] == 6'd0);
+		$display("WB Test 5 started");
+		wait(mprj_io[25:20] == 6'd1);
+		wait(mprj_io[37:36] == 2'b01);
+		wait(mprj_io[25:20] == 6'd3);
+		wait(mprj_io[25:20] == 6'd2);
+		wait(mprj_io[37:36] == 2'b00);
+		
+		$display("WB Test 5 Finish correctly");
+		//wait(checkbits == 16'h0002);
+		#10000;
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("wb_test5.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/wb_test6/Makefile b/verilog/dv/wb_test6/Makefile
new file mode 100644
index 0000000..a510d38
--- /dev/null
+++ b/verilog/dv/wb_test6/Makefile

@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_test6
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all

diff --git a/verilog/dv/wb_test6/wb_test6.c b/verilog/dv/wb_test6/wb_test6.c
new file mode 100644
index 0000000..6330b5a
--- /dev/null
+++ b/verilog/dv/wb_test6/wb_test6.c

@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+void clock(){
+	// clock
+	reg_la2_data = 0x00000001;
+	reg_la2_data = 0x00000000;
+	// end clock
+}
+
+void clean_lines(){
+    reg_la0_data = 0x00000000;
+    reg_la1_data = 0x00000000;
+}
+
+void add_value_to_register(uint32_t value, uint32_t selected_regsiter){
+
+	reg_la0_data = (selected_regsiter << 5| 2 & 0x1F);
+	reg_la1_data = value;
+}
+
+void read_value_from_register(uint32_t selected_regsiter){
+
+	reg_la0_data = (selected_regsiter << 5| 1 & 0x1F);
+
+}
+#define reg_wb_register           (*(volatile uint32_t*)0x30100010)
+#define reg_wb_invalid_register   (*(volatile uint32_t*)0x30200000)
+#define reg_wb_reads              (*(volatile uint32_t*)0x30001000)
+#define reg_wb_ecc_corrected      (*(volatile uint32_t*)0x30001008)
+
+void main()
+{
+    
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+
+	reg_uart_clkdiv = 625;
+	reg_uart_enable = 1;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+	// Configure LA probes 
+	// outputs from the cpu are inputs for my project denoted for been 0 
+	// inputs to the cpu are outpus for my project denoted for been 1
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+	
+	// Flag start of the test 
+	reg_mprj_datal = 0xAB400000;
+
+	// clock and reset
+	reg_la2_data = 0x00000003;
+	reg_la2_data = 0x00000000;
+	// end clock
+
+    add_value_to_register(1, 4);
+    clock();
+    add_value_to_register(2, 0);
+    clock();
+    add_value_to_register(3, 1);
+    clock();
+    clean_lines();
+    clock();
+    // deactivate internal clock
+    reg_la2_oenb = 0xFFFFFFFF;
+    // data 0x1
+    // partity bits 1000011
+    //apply modification to the register
+    reg_wb_register = 0x00000003;
+    // write the value to the wrong address
+    reg_wb_invalid_register = 0x0000000F;
+    clock();
+    // re enable clock
+    reg_la2_oenb = 0xFFFFFFFC;
+
+    read_value_from_register(4);
+    clock();
+    read_value_from_register(1);
+    clock();
+    clean_lines();
+    clock();
+    // deactivate internal clock
+    reg_la2_oenb = 0xFFFFFFFF;
+    // check registers file
+    if (reg_wb_reads == 0x00000002){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    if (reg_wb_ecc_corrected == 0x00000001){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+
+    clock();
+    // re enable clock
+    reg_la2_oenb = 0xFFFFFFFC;
+    read_value_from_register(0);
+    clock();
+    
+    reg_mprj_datal = 0xAB410000;
+	print("\n");
+	print("Monitor: Test 6 Passed\n\n");	// Makes simulation very long!
+	reg_mprj_datal = 0xAB510000;
+}

diff --git a/verilog/dv/wb_test6/wb_test6.gtkw b/verilog/dv/wb_test6/wb_test6.gtkw
new file mode 100644
index 0000000..091dba7
--- /dev/null
+++ b/verilog/dv/wb_test6/wb_test6.gtkw

@@ -0,0 +1,63 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jun 14 09:37:07 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test6/wb_test6.vcd"
+[dumpfile_mtime] "Mon Jun 14 09:30:39 2021"
+[dumpfile_size] 1440308782
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test6/wb_test6.gtkw"
+[timestart] 599767300
+[size] 1848 1016
+[pos] -1 -1
+*-16.705433 600062500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] wb_test6_tb.
+[treeopen] wb_test6_tb.uut.
+[treeopen] wb_test6_tb.uut.mprj.
+[treeopen] wb_test6_tb.uut.mprj.mprj.
+[treeopen] wb_test6_tb.uut.mprj.mprj.register_file.
+[sst_width] 341
+[signals_width] 246
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+wb_test6_tb.uut.mprj.mprj.register_file.clk_i
+wb_test6_tb.uut.mprj.mprj.register_file.rst_i
+@22
+wb_test6_tb.uut.mprj.mprj.register_file.register_i[4:0]
+wb_test6_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+@28
+wb_test6_tb.uut.mprj.mprj.register_file.rregister_i
+wb_test6_tb.uut.mprj.mprj.register_file.wregister_i
+@22
+wb_test6_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@c00028
+wb_test6_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@28
+(0)wb_test6_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+(1)wb_test6_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@1401200
+-group_end
+@200
+-
+-WISHBONE TOP
+@22
+wb_test6_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+wb_test6_tb.uut.mprj.mprj.register_file.wbs_adr_i[31:0]
+wb_test6_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
+@28
+wb_test6_tb.uut.mprj.mprj.register_file.wbs_we_i
+@22
+wb_test6_tb.uut.mprj.mprj.register_file.rdata_o[31:0]
+@28
+wb_test6_tb.uut.mprj.mprj.register_file.ready_o
+@200
+-
+-PMU
+@28
+wb_test6_tb.uut.mprj.mprj.register_file.inst_PMU.rregister_i
+@25
+wb_test6_tb.uut.mprj.mprj.register_file.inst_PMU.total_reads_registers[31:0]
+[pattern_trace] 1
+[pattern_trace] 0

diff --git a/verilog/dv/wb_test6/wb_test6_tb.v b/verilog/dv/wb_test6/wb_test6_tb.v
new file mode 100644
index 0000000..801a61a
--- /dev/null
+++ b/verilog/dv/wb_test6/wb_test6_tb.v

@@ -0,0 +1,155 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module wb_test6_tb;
+	reg clock;
+    reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    wire gpio;
+	wire uart_tx;
+    wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits  = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	initial begin
+		$dumpfile("wb_test6.vcd");
+		$dumpvars(0, wb_test6_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (200) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test WB (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test WB (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		wait(mprj_io[25:20] == 6'd0);
+		$display("WB Test 6 started");
+		wait(mprj_io[25:20] == 6'd1);
+		wait(mprj_io[37:36] == 2'b01);
+		wait(mprj_io[25:20] == 6'd3);
+		wait(mprj_io[25:20] == 6'd2);
+		wait(mprj_io[37:36] == 2'b00);
+		
+		$display("WB Test 6 Finish correctly");
+		//wait(checkbits == 16'h0002);
+		#10000;
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("wb_test6.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/wb_test7/Makefile b/verilog/dv/wb_test7/Makefile
new file mode 100644
index 0000000..0875215
--- /dev/null
+++ b/verilog/dv/wb_test7/Makefile

@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_test7
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all

diff --git a/verilog/dv/wb_test7/wb_test7.c b/verilog/dv/wb_test7/wb_test7.c
new file mode 100644
index 0000000..1238eb1
--- /dev/null
+++ b/verilog/dv/wb_test7/wb_test7.c

@@ -0,0 +1,243 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+void clock(){
+	// clock
+	reg_la2_data = 0x00000001;
+	reg_la2_data = 0x00000000;
+	// end clock
+}
+
+void clean_lines(){
+    reg_la0_data = 0x00000000;
+    reg_la1_data = 0x00000000;
+}
+
+void add_value_to_register(uint32_t value, uint32_t selected_regsiter){
+
+	reg_la0_data = (selected_regsiter << 5| 2 & 0x1F);
+	reg_la1_data = value;
+}
+
+void read_value_from_register(uint32_t selected_regsiter){
+
+	reg_la0_data = (selected_regsiter << 5| 1 & 0x1F);
+
+}
+
+#define reg_wb_reads                  (*(volatile uint32_t*)0x30001000)
+#define reg_wb_writes                 (*(volatile uint32_t*)0x30001004)
+#define reg_wb_ecc_corrected          (*(volatile uint32_t*)0x30001008)
+#define reg_wb_reads_back             (*(volatile uint32_t*)0x30011000)
+#define reg_wb_writes_back            (*(volatile uint32_t*)0x30001004)
+#define reg_wb_ecc_corrected_back     (*(volatile uint32_t*)0x30011008)
+
+void main()
+{
+    
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+
+	reg_uart_clkdiv = 625;
+	reg_uart_enable = 1;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // define whisbone PMU and BACKUP PMU
+    volatile uint32_t *reg_wb_pmu;
+    volatile uint32_t *reg_wb_pmu_back;
+    reg_wb_pmu = 0x30000000;
+    reg_wb_pmu_back = 0x30010000;
+
+	// Configure LA probes 
+	// outputs from the cpu are inputs for my project denoted for been 0 
+	// inputs to the cpu are outpus for my project denoted for been 1
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFF8;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+	
+	// Flag start of the test 
+	reg_mprj_datal = 0xAB400000;
+
+	// clock and reset
+	reg_la2_data = 0x00000003;
+	reg_la2_data = 0x00000000;
+	// end clock
+
+
+    // fill up all registers
+    for (uint32_t i = 0; i < 32; ++i ){
+		add_value_to_register(i+1, i);
+		clock();
+	}
+    // read all values from all regsiters
+	for (uint32_t i = 0; i < 32; ++i ){
+		read_value_from_register(i);
+		clock();
+	}
+    clock();
+    clean_lines();
+    clock();
+    // deactivate internal clock
+    reg_la2_oenb = 0xFFFFFFFF;
+    // check PMU
+    for (uint32_t i = 0; i < 2; ++i ){
+        if (*reg_wb_pmu == 1){
+            print("OK\n\n");
+        }
+        else{
+            print("ERROR\n\n");
+        }
+        reg_wb_pmu = reg_wb_pmu + 4; // reads
+
+        if (*reg_wb_pmu_back == 1){
+            print("OK\n\n");
+        }
+        else{
+            print("ERROR\n\n");
+        }
+        reg_wb_pmu_back = reg_wb_pmu_back + 4; // reads
+	} 
+    // check the total values
+    // reads
+    if (reg_wb_reads == 32){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    if (reg_wb_reads_back == 32){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    // writes
+    if (reg_wb_writes == 32){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    if (reg_wb_writes_back == 32){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    // ECC errors
+    if (reg_wb_ecc_corrected == 0){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    if (reg_wb_ecc_corrected_back == 0){
+        print("OK\n\n");
+    }
+    else{
+        print("ERROR\n\n");
+    }
+    clock();
+    // re enable clock
+    reg_la2_oenb = 0xFFFFFFFC;
+    add_value_to_register(50, 0);
+    clock();
+    read_value_from_register(0);
+    clock();
+    
+    reg_mprj_datal = 0xAB410000;
+	print("\n");
+	print("Monitor: Test 7 Passed\n\n");	// Makes simulation very long!
+	reg_mprj_datal = 0xAB510000;
+}

diff --git a/verilog/dv/wb_test7/wb_test7.gtkw b/verilog/dv/wb_test7/wb_test7.gtkw
new file mode 100644
index 0000000..3a58e68
--- /dev/null
+++ b/verilog/dv/wb_test7/wb_test7.gtkw

@@ -0,0 +1,43 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jun 14 11:07:54 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test7/wb_test7.vcd"
+[dumpfile_mtime] "Mon Jun 14 11:04:45 2021"
+[dumpfile_size] 2405440421
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test7/wb_test7.gtkw"
+[timestart] 4999099400
+[size] 1848 1016
+[pos] -1 -1
+*-17.000000 4734071900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] wb_test7_tb.
+[treeopen] wb_test7_tb.uut.
+[treeopen] wb_test7_tb.uut.mprj.
+[treeopen] wb_test7_tb.uut.mprj.mprj.
+[sst_width] 233
+[signals_width] 214
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+wb_test7_tb.uut.mprj.mprj.register_file.clk_i
+@22
+wb_test7_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@28
+wb_test7_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@200
+-
+-WISHBONE TOP
+@22
+wb_test7_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+wb_test7_tb.uut.mprj.mprj.register_file.wbs_adr_i[31:0]
+wb_test7_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
+@28
+wb_test7_tb.uut.mprj.mprj.register_file.wbs_we_i
+@29
+wb_test7_tb.uut.mprj.mprj.register_file.ready_o
+@22
+wb_test7_tb.uut.mprj.mprj.register_file.rdata_o[31:0]
+[pattern_trace] 1
+[pattern_trace] 0

diff --git a/verilog/dv/wb_test7/wb_test7_tb.v b/verilog/dv/wb_test7/wb_test7_tb.v
new file mode 100644
index 0000000..6bafa78
--- /dev/null
+++ b/verilog/dv/wb_test7/wb_test7_tb.v

@@ -0,0 +1,152 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module wb_test7_tb;
+	reg clock;
+    reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    wire gpio;
+	wire uart_tx;
+    wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits  = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	initial begin
+		$dumpfile("wb_test7.vcd");
+		$dumpvars(0, wb_test7_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (1000) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test WB (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test WB (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		wait(mprj_io[25:20] == 6'd0);
+		$display("WB Test 7 started");
+		wait(mprj_io[25:20] == 6'd50);
+		wait(mprj_io[37:36] == 2'b00);
+		
+		$display("WB Test 7 Finish correctly");
+		//wait(checkbits == 16'h0002);
+		#10000;
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("wb_test7.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire