blob: 2312319376dacb8cd6606e4abf62826ba0d72346 [file] [log] [blame]
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
//-----------------------------------------------------
// Project Name : a.out
// Function : Main processor
// Description : This is the main processor
// Coder : Jaquer AND VORIXO
//***Headers***
//***Module***
module decoder_output #(
parameter integer WORD_SIZE = 32
)
(
`ifdef USE_POWER_PINS
inout wire vdda1, // User area 1 3.3V supply
inout wire vdda2, // User area 2 3.3V supply
inout wire vssa1, // User area 1 analog ground
inout wire vssa2, // User area 2 analog ground
inout wire vccd1, // User area 1 1.8V supply
inout wire vccd2, // User area 2 1.8v supply
inout wire vssd1, // User area 1 digital ground
inout wire vssd2, // User area 2 digital ground
`endif
input wire [1 : 0] operation_result_i ,
input wire [WORD_SIZE - 1 : 0] store_data_i ,
output wire [1 : 0] operation_result_o ,
output wire [WORD_SIZE - 1 : 0] store_data_o
);
//***Internal logic generated by compiler***
//***Dumped Internal logic***
assign operation_result_o = operation_result_i;
assign store_data_o = store_data_i;
//***Handcrafted Internal logic***
//TODO
endmodule